JPS59153324A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain a switched capacitor type A/D converter where offset of a comparator does not give effect on the accuracy by providing plural switched capacitors, an inverse amplifier and a control circuit. CONSTITUTION:Switches S21, S23 connected to an input signal terminal 21, a switch S22 connected to a reference voltage terminal 22, a switch S24 connected to a common terminal, a capacitor C21 connected to the other end of the switches S21, S22, a capacitor C22 connected to the other end of the switches S23, S24, and the inverse amplifier whose input is connected to the other end of the capacitors C21, C22 are provided to this A/D converter. Further, said A/D converter is provided with a switch S25 whose one end is connected to an output terminal of the amplifier 23 and whose other end is connected to the other end of the capacitor C21, a switch S26 whose one end is connected to the output terminal 23 of the amplifier 23 and whose other end is connected to the input terminal, a switch S27 whose one end is connected to a feedback input terminal 25 and whose other end is connected to the capacitor C22, and a control circuit 27 inputting a comparison output Vc and an external clock and generating a control signal to the switches S21-S27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention (-1) relates to an improvement of a Chidogaba/reverse type A/D converter.

[Prior art]

Figure 1 shows 11911 of a conventional charge distribution type D/A converter.
It is an explanatory diagram showing the principle of a prototype made by Caliph A. Runia University. '8 Two equal capacitors / C1l,
C12 is initially left alone. 1. Open all switches and start conversion from LST3. LSB state d =
1. At this time, the switch 812 is momentarily closed and the capacitor C1l is charged with the reference voltage V-. When d□-0,
Close switch S13. Next, only switch Sll is momentarily closed to redistribute the charge.

At this time, the terminal voltage Vll of capacitors C1l and C12
(1).

V12 (1) becomes diVR/2. Continuation,
The state d2 of the bit on LSB(7)-2 momentarily closes switch S12 or 813. Then switch S
If the charge is redistributed only by IRI, the terminal voltages of the capacitors C11, C12 will be Vll(2), V1
2(2) is expressed as follows.

Vll(2) = V12(2) −T (d2+T
dl) VR (1) When the above operation is repeated, after the completion of the k-th charge redistribution, the capacitor C1l,
The terminal voltage of C12 Vll (K), V12 (K
) becomes ), and the k-bit D/A conversion is completed.

As above / A converter can be used / Yu 2 (1
It consists of a /I and an analog switch, and is suitable for IC implementation, but if you use this circuit to assemble a successive approximation type SUI, CHIDOKAPANOTA/D converter, the conversion time will be slow, It rarely has drawbacks such as being unsuitable for high-precision applications because the offset of the comparator affects accuracy.

1. Journal of the Institute of Electronics and Communication Engineers' 81/9 + Vol.
In the case of the switched capacitor type A/D converter by Isaka et al. K. published in J64-C+ No. 9 +5601565, the offset of the comparator, arithmetic unit, etc. affects the error.

〔the purpose〕

This invention was made in order to solve the above problems, and aims to realize a switched capacitor type A/D converter in which the offset of the comparator etc. does not affect the accuracy. [Summary] In order to achieve the above object, the first gist of the present invention is to provide an input signal terminal to which an input signal is applied, first and fifth switches whose ends are connected to the input signal terminal, and a reference voltage. a reference voltage terminal to which is applied, a second switch whose one end is connected to the non-quasi-voltage terminal, a fourth switch whose one end is connected to the common; a first capacitor, the other end of the second switch being connected in relation to one end thereof; a second capacitor, the other end of the fourth switch being connected in relation to one end thereof;
an inverting amplifier, the other end of which is connected to the input terminal of the second capacitor; and a fifth switch, one end of which is connected to the output terminal of the inverting amplifier, and the other end of which is connected in relation to one end of the first capacitor. a sixth switch, one end of which is connected to the output terminal of the inverting amplifier and the other end connected to the input terminal of the inverting amplifier; and a feedback terminal to which a signal related to the residual output from the inverting amplifier is applied. A seventh switch, one end of which is connected to the feedback terminal, and the other end of which is connected to the one end of the second capacitor, and the output signal of the inverting amplifier is connected manually to the opening and closing of each switch. Q! Is it equipped with a control circuit? There is a 1-bit signal with a J characteristic, and an A/D conversion.

A second aspect of the present invention resides in a cascaded A/D converter in which a plurality of 1-bit A/D converters according to the first aspect are connected in cascade.

The sixth aspect of the present invention resides in a cyclic A/D converter constructed by combining the 1-bit A/D converter of the first aspect and the sample bold circuit.

[Explanation of Examples]

The present invention will be explained below with reference to the drawings. Figure 2 is an electrical circuit diagram showing an embodiment of an A/D converter according to the present invention. In the main circuit 2o, 21 is an input signal terminal to which an input signal V is applied, 321 and 323 are switches whose ends are connected to this input signal terminal 21, 22 is a reference voltage terminal to which a reference voltage v11 is applied, and 322 is this terminal. A switch whose one end is connected to the reference voltage terminal 22, S24 is a switch whose one end is connected to the common, and C21 is the switch 821. S to which the other end of S22 connects to one end
Ai capacitor C22 is this first capacitor C2
A second capacitor having substantially the same capacity as 1 and connected to one end of the switch 823 and 824; 23 is an inverting amplifier S25 to which the other ends of the capacitors C21 and C22 are connected to its input terminal; 826 is a switch to which the output terminal of the inverting amplifier 23 is connected to one end and the one end of the capacitor C21 is connected to the other end; and 826 is a switch to which the output terminal of the inverting amplifier 23 is connected to the other end. a switch whose other end is connected to the input terminal; 24 is an output terminal to which the output of the inverting amplifier 23 is applied;
25 is a feedback input terminal for inputting a feedback signal FB related to the residual output from this output terminal 24; 827 is a switch whose one end is connected to this feedback input terminal 25 and whose other end is connected to the one end of the capacitor C22; 26 is a circulation input terminal (necessary only when a circulation type is used) connected to the one end of the capacitor C21. Reference numeral 27 inputs the comparison output VC from the main circuit 20 and an external clock, and connects each switch 321 to 327- of the main circuit 20.
This is a control circuit that generates a control signal.

FIG. 5 is an operational explanatory diagram for explaining the operation of the one-piece A/D converter configured as described above.

The operation will be explained below according to each step in FIGS. 5(A) to 5(D).

(A) First, only switch 821.323.326 is turned on and input voltage VT is applied to capacitors C21 and C22.
hold it.

The input terminal of the inverting amplifier 23 becomes virtual ground, but the potential becomes vT due to an off-hit (threshold voltage) VT.

(B) Next, switch S24. Only S25 is turned on, and the capacitor C22's load is transferred to 021-\.

Since the voltage between the terminals of the capacitor C22 changes from v-■ to -VT, the electric charge C22VT is transferred to the capacitor C21. As a result, the voltage v1 between the terminals of the capacitor C21 becomes 22 (1+7,7.-)V, -VT.

(C) When only the switch 322 is turned on, the inverting amplifier 23 operates as a comparator with a threshold value V, and its input potential (2) becomes V=V-(1+sub)V+V RC21,IT . As a result, the input voltage can be compared with .

When 21 vT<C21±C22vR, the comparison output from the inverting amplifier 23 becomes L (corresponding to the data output of logic 0), and the next D1 step occurs.

Proceed to Puhe.

When 21v ≧C21+C22vR, the comparison output from the inverting amplifier 23 becomes H (corresponding to data output of logic 1), and the process proceeds to the next step D2.

■) Only switch S25 is turned ON, and the inverting amplifier 23
As the residual output from C22 (3) Vo=V (:t+-mento) ''-2V is obtained.

(D2) Switch 822. Turn ON only S27, transfer the charge of the capacitor C21 to the capacitor C22, and output the residual output C21C21 Vo=(1"-, 5th)V knee!2"R(4) both 2
Get V Knee VR.

FIG. 4 shows a characteristic curve diagram showing the human output characteristics of the above circuit.

In an A/D converter with such a configuration, the offset (or threshold voltage) of the inverting amplifier is, in principle,
Since it does not affect the accuracy of the output, something as simple as an inverter can be used.

Since there are only 1 operation step and 4 steps, which is relatively small, the conversion speed is also relatively fast. Since it is a switched capantor type, no current flows in the balanced state, so there is no error caused by the on-resistance of the switch.

FIG. 5 is a block diagram showing a second embodiment of the present invention.
A plurality of A/D converters are constructed by connecting a plurality of 1-bit A/D converters in cascade as shown in the figure. The input signal vIN applied to the input terminal 51 is applied to each reference voltage terminal 22 of the main circuit 20 (FIG. 2) of the A/D conversion circuit. 21 (Fig. 2).The output from the first stage main circuit 2o is the remainder output Voo, which is added to the feedback input terminal 2.
The comparison output Vcm -Vc from each main circuit 20 connected to the number of main circuits 20 that are fed back to
n, and the clock input through the clock input terminal 53 are applied to a control circuit 54 to generate control signals for each switch. The comparison output Vco −Vcrl,
are each delayed by the shift register array 55 (D is a delay circuit) and output the parallel A/D conversion output data do-
It becomes dn-0.

The A/D converter with such a configuration has the features of the first embodiment, and also has high precision and ``6I several bits of A/D converter.
/D converter can be obtained at the same sample rate as the A/D converter (the sample rate is about n times higher than that of the cyclic type described later).

FIG. 6 is a block diagram showing a fifth embodiment of the present invention, in which a multi-bit A/D converter is constructed by cyclically and repeatedly operating the 1-bit A/D converter circuit of FIG. This is what I did. In the figure, the main circuit 20 (FIG. 2) -\ receives the input signal V□ through the input terminal 61, but the -quasi-voltage terminal 6
A reference voltage is applied via 2. The surplus output Vo from the main circuit 2o is connected to the switch S64. Gapanta c64. Consisting of buffer 641 / full hold circuit 64
The output from the sample and hold circuit 64 is applied to the feedback input terminal of the main circuit 2o and the switch 3.
61 to the circulating input terminal. Control circuit 65
is input via the clock input terminal 63. The comparison output Vc from the main circuit 2o is inputted, and the switch control signal and the A/D conversion data output terminal dn-1 (
generate an n-bit field n).

The operation of the A/D converter with such a configuration is as follows:
Perform D conversion and switch 3 at step Φ in Figure 6.
64 is turned ON and its residual output v00 is held in the sample/hold circuit 64 (H in the step of FIG. 5(D)).
A sample/hold circuit is inserted at the point) 3
, In the next step (step in FIG. 5(A)), the switch 861 is turned on and the previous surplus output Voo is transferred to the capacitor/
It is held by C21. At this time, since the previous residual output Voo is also held in the gap capacitor C22, the fifth
By performing the steps shown in FIGS. (B) to (D), the following conversion can be performed. A series of comparison outputs Vc=Vc obtained for each conversion by repeating this operation once
o-Van-0 corresponds to the data output do-dn output from the control circuit 65. .

The A/D converter with such a configuration has the features of the first embodiment, and also has high-precision, multi-bit A/D converter.
/D converter has the advantage that it can be realized with a simple configuration. Also, the number of bits can be easily increased by 1 simply by increasing the number of repetitions of the procedure.

Also, since the sample/hold circuit used in Figure 6 is included in a closed loop, it does not matter what offset, gage, or characteristic it is, and can be simple. can be used.

FIG. 7 is an electrical circuit diagram showing a fourth embodiment of the present invention, in which the A/D converter circuit shown in the first embodiment (FIG. 2) is combined with the A/D conversion circuit shown in FIG. This circuit is made to operate as a D/A conversion circuit by adding a circuit S78.879 (the first digit of each code in Fig. 7 and Fig. 2 corresponds. The diagram of the control circuit is omitted.) ,,
The operation of the circuit shown in FIG. 7 as an A/D converter is the same as that shown in FIG. 2.

Figure 8 is an operation explanatory diagram showing the operation when the circuit in Figure 7 is operated as a D/A converter.
Each operation step will be explained based on FIGS.

(A) Turn on the manual data sample switch 876 and input terminal 1 of the inverting amplifier.
Inverting the voltage offset (or threshold voltage) of the amplifier
Keep at vT1. lbi trying to convert.

If the data of the th eye is 1, @ is the switch 872.
, when pi=o, turn on the switch 378 and set the voltage v1 between the terminals of the capantor C71 to a constant voltage v1 - VRPi
-Charge to VT 3, if the input data is LSB (+ = +)
turns on the switch S74 and charges the voltage v2 between the terminals of the cable C72 to T. If the input data is not LSB (il'l
') is switch S74 Vi, d--B7-Ill'
The key, par C72 is one year old holding the conversion result v2=Voi-1-VT of the AiJ times (circular style) or the previous stage (vertical style).

(B) Charge redistribution then switch S79. S76 is turned on to redistribute the charges held in the gap capacitors C71 and C72 at (A,).

The terminal voltage of the capantors C71 and C72 after redistribution, that is, the converted voltage Voi, is as follows. Since the values of capantors C71 and C72 are almost equal, equation (5) is as follows: 1 Voi'', 7- (VRPi+Voi-1)
(6) becomes. Equation (6) represents a general equation for charge redistribution type D/A conversion. In the case of the cyclic type, the value v = Voi -VT at this time is held in the capacitor C72 and used for the next conversion.

(C) Conversion output This is the case of the cascade type, and when the switch S77 is turned on, the above conversion voltage Voi (il-) is output as the output voltage V via the inverting amplifier 73 as a buffer, and becomes the input v1 of the second stage.

The D/A converter configured as described above is used as the 1-bit converter.

) Similarly to one station of an A/D converter, by using a cascade type or a circular type, D for several bits of data input is
/A converter can be configured 6゜Such a configuration ODA converter is such that the offset (1 or threshold voltage) of the inverting amplifier does not affect the accuracy of the output, and the switch is ON.
It has advantages such as resistance does not cause errors and it is suitable for IC implementation.

With the configuration shown in Figure 7, human/D conversion and D/A conversion can be performed in the same circuit, which greatly simplifies the input/output interface of, for example, a process computer system. can be converted into

In the circuits of FIGS. 2 and 7, by inserting buffers 91 and 92 in front of capacitors C21 and C22 or C71 and C72 as shown in FIG. You can increase the speed of charging. The formula representing the remainder output in this case is (
When a buffer is added to the circuit in Figure 2) the comparison output is L.
When , Vo=(1+-Handan)V (7
)βIC21I, and when the comparison output is H, Vo-(10~浬麩-)v-浬庩■(8)βIC22I
Becomes β2C22R. However, β1. β2 is the gain of the buffer 91.92. That is, it does not affect the accuracy of the offset d output of the buffers 91 and 92, and it is sufficient that the gains are the same for β1 and β2.

[Efficacy of invention Song Dynasty]

As described above, according to the present invention, the offset of the comparator etc. does not affect the accuracy.
A D converter can be realized.

[Brief explanation of drawings]

Fig. 1 is a principle circuit diagram of a conventional charge redistribution type A/D converter, Fig. 2 is a circuit diagram showing an embodiment of an A/D converter according to the present invention, and Fig. 5 is a circuit diagram showing the principle of an A/D converter according to the present invention. FIG. 4 is a characteristic curve diagram showing the input/output characteristics of the circuit in FIG. 2, and FIG. 35 is a diagram showing the second embodiment of the present invention. , FIG. 6 is a diagram showing the third embodiment of the present invention, FIG. 7 is an electric circuit diagram showing the fourth embodiment of the present invention, and FIG. 8 is a diagram showing the circuit of FIG. 7. FIG. 9 is a partial circuit diagram showing a modification of the circuits in FIGS. 2 and 7. 20, 70... Main circuit, 21.71... Human power signal terminal,
22゜72...Reference 1 pressure terminal, 23.73...Inverting amplifier, 25.75 Return terminal, 27.54.65...Control circuit, 64...Sample/hold circuit, vvv-
v ・Input signal IN'I' Io In-1

Claims (3)

[Claims] (1) An input signal terminal to which an input signal is applied, first and fifth switches whose ends are connected to this input signal terminal, a reference voltage terminal to which a reference voltage is applied, and one end of which is connected to this reference voltage terminal. a second switch, a fourth switch having one end connected to the common, a m 1 capacitor having the other end connected in relation to the other end of the 1.82 switch; a second capacitor, the other end of the fourth switch being connected in relation to one end thereof;
an inverting amplifier, the other end of which is connected to the input terminal of the second capacitor, and a -5 switch whose one end is connected to the output terminal of the inverting amplifier and whose other end is connected in relation to one end of the first capacitor; a sixth switch, one end of which is connected to the output terminal of the inverting amplifier and the other end connected to the input terminal of the inverting amplifier; and a feedback terminal to which a signal related to the residual output from the inverting amplifier is applied. a seventh switch whose one end is connected to the feedback terminal and whose other end is connected to the one end of the second capacitor; and at least each switch to which the output signal of the inverting amplifier is input. 1. A 1-bit h/D converter, characterized in that it is equipped with a control circuit for controlling opening and closing of a channel. (2) 1 piece composed as shown in (a) below) A
/ l) Adjust the conversion circuit according to the number of bits of data output /
A plurality of bits are connected in cascade, and the remainder output of each stage is used as an input signal of the next stage, and a plurality of bits of data output is obtained from the comparison output of each of the 1-bit and digital/digital conversion circuits. A/D converter. (b) A human power signal terminal to which an input signal is applied, and first and sixth switches whose ends are connected to this human power signal terminal;
A reference voltage terminal to which a reference voltage is applied, a second switch whose one end can be connected to the reference voltage terminal, a fourth switch whose one end can be connected to the common, and the 8g1. a first capacitor to which the other end of the second switch is connected relative to one end thereof; and said 8g3. a second capacitor to which the other end of the fourth switch is connected in relation to one end thereof; and ^1.
an inverting amplifier, the other end of which is connected to the input terminal of the second capacitor, one end of which is connected to the output terminal of the inverting amplifier, and the other end of which is connected in relation to one end of the first capacitor; a fifth switch; a sixth switch having one end connected to the output terminal of the inverting amplifier and the other end connected to the input terminal of the inverting amplifier; and a sixth switch connected to the remainder output from the inverting amplifier; a feedback terminal to which a signal is applied;
A seventh switch whose one end is connected to this feedback terminal and whose other end is connected to the one end of the capacitor #1.2, and an output signal of the inverting amplifier is inputted to control opening and closing of at least each of the switches. 1.) A/D converter characterized by comprising a control circuit. (3) Constructed as shown in (a) below, the fC1/D conversion circuit and its remainder output signal are used as inputs, and its output No. 16 is the same as the above-mentioned No. 1. It consists of a sample and hold circuit applied in connection with the one end of the second capacitor, and by repeating conversion a number of times corresponding to the number of bits of the data output, a multi-bit data output is obtained from the comparison output. An A/D converter characterized by: (b) An input to which an input signal is applied (terminal i, the first and fifth switches whose ends are connected to this input signal terminal, a reference voltage terminal to which a reference voltage is applied, and one end of which is connected to this reference voltage terminal) A fourth switch, one end of which is connected to Como 7, and a first switch, the other end of which is connected in relation to its one end.
capacitor, and the third capacitor. a second capacitor, the other end of the fourth switch being connected in relation to one end thereof; an inverting amplifier, the other end of which is connected to the input terminal of the second cabling; one end of which is connected to the output terminal of the inverting amplifier, and the other end of which is connected in relation to one end of the first cabling; a fifth switch; a sixth switch having one end connected to the output terminal of the inverting amplifier and the other end connected to the input terminal of the inverting amplifier; and a signal related to the residual output from the inverting amplifier. Ni feedback terminal, one end of which is connected to this feedback terminal [7] A seventh switch, the one end of which is connected to the one end of the second capacitor; 1.) A/D converter, characterized in that it comprises a control circuit that controls opening and closing of each of the switches.