JPH04249427A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To obtain desired converted data in the conversion using a successive comparison type A/D converter by terminating the A/D converting operation when the conversion of a necessary number of bits is terminated. CONSTITUTION:Initial data '00H' is set in shift register 21, and initial data '80H' is set in a successive comparison type register 11. Analog voltage 15 to be outputted from resistor ladder 14 is compared with analog input voltage 17 by comparator 16 to change the content of the successive comparison type register 11. Repeating this operation carries out A/D conversion of the content successively from the uppermost bit, and converted data is inputted to both a shift register 21 and an A/D conversion stop circuit 22. The A/D conversion stop circuit 22 calculates the number of bits from the successive comparison type register 11, and when the number of bits calculated reaches a value set in register 23 in advance, the A/D conversion is stopped. At this point of time, the number of bits of data stored in shift register 21 is obtained as a result of the A/D conversion.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuits, and more particularly to an analog-to-digital converter for converting analog data into digital data.

0002

[Prior Art] Data measured by various measuring instruments is an analog quantity, so in order to perform data processing on this data, it is converted into a digital quantity using a so-called analog-to-digital converter (hereinafter referred to as an A/D converter). There is a need. Various types of A/D converters are currently available, one of which is a successive approximation type A/D converter. FIG. 3 shows the main part of a conventional successive approximation type A/D converter. This A/D converter is equipped with an 8-bit successive approximation register (11), and each bit corresponds to each stage of the resistance ladder (14) to which the power supply voltage (12) and ground voltage (13) are applied. It is connected to the. This resistance ladder (14) is a so-called ladder type A/D converter, and corresponds to the 8-bit digital data given from the successive approximation type register (11).
12) and the ground voltage (13) by 256
It outputs an analog voltage (15) divided into (=28) stages.

[0003] The analog voltage (15) is input to one of the input terminals of a comparator (16) and is compared with an analog input voltage (17) to be subjected to A/D conversion. Comparator (16)
is adapted to control changing the digital data in the successive approximation type register (11) by giving the comparison signal (18) according to the comparison result to the successive approximation type register (11).

[0004] Also, this A/D converter has an 8-bit A/D converter.
A /D register (19) is provided, and each bit is connected to correspond to each bit of the successive approximation type register (11). This A/D register (19) contains the A/D register (19).
When the conversion is completed, the A/D conversion result is stored.

[0005] Note that an A/D converter with such a configuration is
In reality, it is incorporated into a microcomputer system or the like, and a CPU (central processing unit) within the system controls initial settings and uses conversion results, but these controls are generally performed by software.

Conventional successive approximation type A/
The operation of the D converter will be explained.

[0007] The CPU (not shown) receives “
80H" is applied to the successive approximation type register (11). Here, the code "H" indicates hexadecimal data (the same applies hereinafter). If this is expressed in binary, it is "100000.
00”.

An analog voltage (15) corresponding to this digital data "80H" is output from the resistor ladder (14) and input to the comparator (16). Comparator (16
), if the analog input voltage (17) is larger than the analog voltage (15), the comparison signal (
18), "1" is given to the successive approximation type register (11). In this case, the most significant bit (seventh bit) of the successive approximation register (11) is held as "1" and the next sixth bit "0" is changed to "1". As a result, the value of the successive approximation type register (11) is “11000000”,
In other words, it becomes "C0H".

On the other hand, when the analog input voltage (17) is smaller than the analog voltage (15), the comparison signal (1
8), "0" is given to the successive approximation type register (11). In this case, the most significant bit “1” of the successive approximation register (11) becomes “0” and the sixth bit “0” becomes “1”.
will be changed to This allows the successive approximation register (11
) is "01000000", that is, "40H".

This comparison operation has the following meaning. That is, digital data “80H” as initial data
is the value VREF of the power supply voltage (12) and the ground voltage (
13) half the difference between the values AVSS (VREF - AV
This is data corresponding to SS)/2. Therefore, at this time, the analog voltage (15) output from the resistance ladder (14)
) and the analog input voltage (17),
Analog input voltage (17) is (VREF - AVSS)
It is possible to determine whether the value is larger than /2.

[0011] Then, the analog input voltage (17) is (V
REF −AVSS)/2, that is, when the comparison signal (18) is “1”, the successive approximation register (
11) is “C0H”, and correspondingly, the value of the analog voltage (15) output from the resistance ladder (14) is 3×(VREF-AVSS)/4 and the analog input voltage (17). Make a comparison.

On the other hand, the analog input voltage (17) is (VR
EF −AVSS)/2, that is, when the comparison signal (18) is “0”, the successive approximation register (1
1) is "40H", and correspondingly, the value of the analog voltage (15) output from the resistance ladder (14) is (VREF - AVSS)/4 and the analog input voltage (
17).

[0013] Similarly, the voltage value (VREF -A
VSS) is divided into 2n (where n is a positive integer) voltage range to which the analog input voltage (17) belongs is checked by successive comparisons using the comparator (16).

In this way, the successive approximation register (1
When the 8-bit data of 1) is determined, this bit data is transferred to the A/D register (19) and stored as the A/D conversion result. This A/D conversion result is then read out from the A/D register (19) by software and used within the microcomputer system.

[0015]

[Problem to be Solved by the Invention] However, in such a successive approximation type A/D converter, the lower several bits of the A/D conversion result may contain errors, so only the upper few bits are processed. Often used.

However, in the conventional A/D converter,
The A/D conversion result is obtained only after all bits have been converted, and it is not possible to use the intermediate conversion result. Therefore, even if only the upper few bits are used, it is necessary to wait until the conversion of all bits is completed, resulting in a problem of wasted time.

[0017]Therefore, there is a problem that the above problems must be solved.

The present invention has been made to solve this problem, and is an analog system that can obtain desired conversion data by ending the A/D conversion operation when the required number of bits have been converted. The purpose is to obtain a digital converter.

[0019]

[Means for Solving the Problems] The analog-to-digital converter according to the present invention has (i) a successive approximation register that outputs digital data of a predetermined number of set bits, and (ii) an output from the successive approximation register. (iii) a comparator that compares the analog voltage output from the digital-to-analog converter with an analog input voltage to be converted;
iv) data setting means for setting new digital data in the successive approximation type register based on the comparison result by this comparator; When the number of bits of the digital data determined as the result of analog-to-digital conversion reaches a predetermined value in the (vi) successive approximation type register, the analog-to-digital conversion operation is performed. and a stopping means for stopping.

[0020]

According to the present invention, each time A/D conversion is performed in the successive approximation register starting from the most significant bit, the bits resulting from the conversion are sequentially stored in the shift register and sequentially shifted. Then, when the number of A/D converted bits reaches a predetermined value, the digital data for which A/D conversion has been completed up to that point is taken out as the A/D conversion result.

[0021]

EXAMPLES The present invention will be explained in detail with reference to Examples below.

FIG. 1 shows an analog-to-digital converter in one embodiment of the present invention. In this figure, parts that are the same as those in the conventional example (FIG. 3) are given the same reference numerals and explanations will be omitted as appropriate.

This A/D converter is provided with an 8-bit shift register (21), and a successive approximation register (11).
), each bit data is transferred from the most significant bit side. The transferred bit data is sequentially shifted in the direction of arrow (24).

The bit data transferred from the successive approximation register (11) is also input to the A/D conversion stop circuit (22), and the number of bits is counted. A 3-bit register is provided in this A/D conversion stop circuit (22), and the stop bit instruction data 0 to 8 set in advance in this register is successively compared with the counted number of bits.

Note that the A/D converter in this embodiment is actually incorporated into a microcomputer system, etc., as in the conventional example, and the CPU (Central Processing Unit) in the system controls initial settings and performs conversion results. The use of

The operation of the A/D converter configured as above will be explained.

First, the CPU (not shown) stores initial data "0" in the shift register (21) before starting A/D conversion.
0H" to perform initialization.

After that, when digital data "80H" is set in the successive approximation type register (11) and the analog voltage (15) corresponding to this is output from the resistance ladder (14), this analog voltage (15) is a comparator (16)
is compared with the analog input voltage (17), and new digital data is set in the successive approximation register (11) according to the comparison result. The details of this operation are the same as those of the conventional example, so the explanation will be omitted here.

In this way, each bit data as a result of A/D conversion is determined in order from the most significant bit of the successive approximation type register (11), but each time these bit data are transferred to the shift register (21) and It is also input to the A/D conversion stop circuit (22). Therefore, the shift register (
21) stores the conversion results up to each point of A/D conversion in real time.

The A/D conversion stop circuit (22) stops the A/D conversion for the CPU when the number of A/D converted bits reaches the stop bit instruction data set in advance in the register (23). A stop signal (25) is output to end the A/D conversion.

By the way, in a successive approximation type A/D converter, the conversion result is determined from the most significant bit, as described above, so the A/D conversion starts when a predetermined number of bits have been converted. Even if the process is terminated, the analog voltage range corresponding to the digital data determined as the A/D conversion result only becomes wider, and there is no practical problem at all. For example, the register (23) of the A/D conversion stop circuit (22)
) is set to "011" (=3) as stop bit instruction data, the conversion will be stopped when 3 bits of 8-bit A/D conversion have been converted. At this time, for example, as shown in FIG. 2, if 3 bits of "101" are stored in order from the most significant bit of the shift register (21), the conversion result is "05H".
becomes. And this value is the voltage difference (VREF −AV
SS) corresponds to one of the voltage ranges divided into 8 (=23) steps.

In this embodiment, the number of bits at which A/D conversion is to be stopped is set in the register (23) of the A/D conversion stop circuit (22). It may also be stopped by a stop signal given from outside. In this case, data of the number of bits completed at the time of input of the stop signal will be obtained as the A/D conversion result.

[0033]

[Effects of the Invention] As explained above, according to the present invention,
Each time A/D conversion is performed starting from the most significant bit, the bits resulting from the conversion are sequentially stored in the shift register, so when the required number of bits have been converted, the A/D By completing the conversion operation, desired conversion data can be obtained.

Therefore, when only the upper few bits are used, the conversion result can be obtained without waiting until conversion of all bits is completed as in the conventional case, and A/D conversion can be performed efficiently and quickly. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an analog-to-digital converter in one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of the contents of a shift register in an A/D conversion stop circuit when A/D conversion is stopped at the time of completion of conversion of 3 bits by this analog-to-digital converter.

FIG. 3 is a block diagram showing a conventional analog-to-digital converter.

[Explanation of symbols]

(11) Successive approximation type register (12) Power supply voltage (13) Ground voltage (14) Resistance ladder (15) Analog voltage (16) Comparator (17) Analog input voltage (21) Shift register (22) A/D conversion stop circuit (23) Register

Claims (1)

[Claims] 1. A successive approximation register that outputs digital data of a predetermined number of set bits, a digital-to-analog converter that outputs an analog voltage corresponding to the digital data output from the successive approximation register, and A comparator that compares the analog voltage output from the analog converter with the analog input voltage as a conversion target, and a data setting that sets new digital data in the successive approximation register based on the comparison result by this comparator. means, a shift register for sequentially storing digital data as an analog-to-digital conversion result in the successive approximation register, each time the digital data is determined in order from the most significant bit thereof in the successive approximation register; An analog-to-digital converter comprising: a stop means for stopping an analog-to-digital conversion operation when the determined number of bits of digital data reaches a predetermined value.