JPH04129332A - Successive approximation a/d converter - Google Patents

Abstract

PURPOSE:To reduce the A/D conversion time by providing a successive approximation timing control circuit to the A/D converter and controlling a successive approximation timing for each bit of binary data conversion. CONSTITUTION:When a register value of SCR, B7R-B4R in a timing control circuit 7 is set to '00' in binary notation, a register value of B3R-B0R is set to '01' in binary notation, and a register value of DR is set similarly to '10' in binary notation, a timing generating circuit 6 generates an A/D conversion timing signal in the mode 1. Thus, in this case, clocks required for 8-bit A/D conversion are 29 clocks and the conversion time is 75% in comparison with 40 clocks in a conventional A/D converter. The D/A conversion time, the D/A output and the comparison time of an input data vary with the quantity of a change in an analog quantity of the D/A conversion output and the time is reduced when a change in the analog quantity is small.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a successive approximation type A/D conversion device, and particularly to a successive approximation type A/D conversion device configured on a semiconductor substrate. [Prior art] Such a conventional successive approximation type A/D conversion device
It consists of a hold circuit, a D/A converter equipped with a resistance ladder, various registers, and the like. FIG. 8 is a block diagram of a successive approximation type A/D conversion device showing an example of such a conventional device. As shown in FIG. 8, a conventional A/D converter, e.g.
Bit successive approximation type A/D converter (hereinafter simply referred to as A/D converter)
(referred to as a converter) includes a sample-and-hold circuit l connected to an external analog input terminal AvrN, and a resistor ladder l.
0 and a resistor ladder selection decoder circuit 9, and is supplied with a reference power supply AV*gp and a substrate power supply A V ss, and an output A of this D/A converter 2.
A comparator 3 that compares the outputs of the NC and sample/hold circuits 1, and a D/A conversion input register 4 that is controlled by the comparison result output of this comparator 3. An external clock input terminal C.
A frequency divider 5 that is connected to the LK and divides the frequency of the external clock, an A/D conversion result storage register 8 that stores the A/D conversion result, and an analog data input from the outside to the sample and hold circuit 1. The storage timing S, the successive comparison timing signals 37 to BO for successively comparing the analog data with analog values obtained by D/A converting each bit of digital data in binary representation, and the A/D conversion results are A/D.
The conversion result is stored in the storage register 8.
) are timing generation circuit diagrams of the A/D converter shown in FIG. 8, respectively. As shown in FIG. 9(a), this timing generation circuit 6
uses a switching counter composed of a NOR gate 12 and 10 shift registers 13, and after an A/D conversion start signal (start pulse) is input,
Each signal S, B7 to BO, and D is generated under the control of a frequency dividing clock via frequency dividing circuits 5A and 5B. Further, as shown in FIG. 9(b), this timing generation circuit 6 uses a 4-bit binary counter 20, and a decoder 21 generates S, B7 to BO as the truth values in Table 1. , D are decoded and output. 10 is a timing chart for explaining the operation of the A/D converter shown in FIG. 8. As shown in FIG. 10, in the above-mentioned A/D conversion device, when an A/D conversion start signal is input from the outside, the successive approximation timing generation circuit 6 and the D/A conversion input register 4 are initialized. After that, S, B7 to BO are input by external clock. D various timing signals are generated sequentially. First, A/
After the D conversion start signal is input, the analog voltage applied to the external terminal ANIN is input to the sample-and-hold circuit l and stored in the timing signal S generated first. Next, the successive approximation timing signal B7 sets the fourth bit of the D/A conversion input register to 1. Further, the D/A conversion input register 4 converts analog data corresponding to binary data [10000000] with the 7th bit set to 1 into a D/A converter 2 configured by a resistor ladder 10 and a resistor ladder selection decoder circuit 9. Get from. The output ANC is then input to the comparator 3 and compared with the analog voltage previously stored in the sample-and-hold circuit 1. As a result of the comparison in the comparator 3, if the analog value stored in the sample/hold circuit 1 is thicker than the analog value of the pressure ANC of the D/A converter 2, the data in bit 7 of the D/A converter input register 4 "1" is held, and conversely, the analog value stored in the sample and hold circuit l is
If it is smaller than the analog value of the A converter 2, the data in the D/A conversion input register 4-7 is set to "0". next,
The successive approximation timing generation circuit 6 activates B66 times, and uses the comparator 3 to D/A convert the analog value stored in the sample/hold circuit 1 and the value set to 1 in the 4th bit of the D/A conversion input register. A comparison is made with the analog value obtained by inputting it to the device 2. For bit 6, the comparison result is stored in the fourth bit of the D/A conversion input register in the same procedure as for bit 7 described above. Thereafter, when such comparison and storage operations are performed in sequence based on the successive approximation timing up to B)O, the A/D conversion is completed. Ru. FIG. 11 is a configuration diagram of the resistance ladder and selection decoder circuit of the D/A converter shown in FIG. 8. As shown in FIG. 11, this D/A converter 2 inputs the 40-bit outputs XBO to XB7 and the bit inverted outputs XBO to XB7 of the DA conversion register, and outputs the outputs of the connection points X r + to Xrzs* of the resistance ladder 10. When any one connection point k is selected, an analog voltage expressed by the following equation is output from the output terminal ANC of the resistance ladder selection decoder circuit 9 from the analog reference potential AVR. Therefore, by inputting the digital data in binary representation stored in the D/A conversion input register 4 to this D/A converter 2, it is possible to obtain an analog value corresponding to the digital value from the pressure ANC. can. FIG. 12 is a characteristic diagram of each bit and D/A conversion output for explaining the operation of the A/D converter shown in FIG. 8. As shown in FIG. 12, the series of operations explained in FIG. 10 is shown here. In other words, the solid line is external terminal A
This shows the A/D conversion operation when the maximum analog input (same potential as A V agy) is input from Nry. , indicates that the value of IFFJ is stored in hexadecimal notation. Moreover, the dotted line represents the A/D conversion operation when the minimum analog input is input from the external terminal, and when the A/D conversion is completed, the D/A conversion input register 4 contains all 0.1
This indicates that a value of "00" is stored in hexadecimal notation. When the 8-bit A/D conversion is completed with the above operation, the D/A conversion input register 4 stores the stored data in the A/D conversion result storage register 8 with a signal at timing D, and a series of A/D conversion operation ends. [Problems to be Solved by the Invention] In the conventional successive approximation type A/D converter described above, since the output signal of the successive approximation timing generation circuit is constant as shown in FIG. The conversion time of N bits when M[μS] is MX (N+2)CμS]
need. Therefore, the conventional successive approximation type A/D converter has a drawback that when the externally input tack rate is constant, the A/D conversion accuracy and A/D conversion time are fixed. In addition, recent A/D converters formed on semiconductor substrates have improved in semiconductor technology (10 bits, 12 bits),
High precision devices such as 16 bits have been developed, but with conventional successive approximation type A/D converters, as well as improving A/D conversion accuracy (increasing the number of bits), the A/D conversion time also increases. The disadvantage is that it occurs. In other words, the A/D conversion time of an 8-bit A/D converter with a conversion speed of 10 μs per bit is 100 μs, but the conversion time of a 12-bit A/D converter is 140 μs, which is 1.4 times faster. Even if this A/D conversion device is used with 8-bit A/D conversion accuracy, the A/D conversion time will be 1.4 times longer. An object of the present invention is to provide a successive approximation type A/D conversion device that can shorten the A/D conversion time and achieve high accuracy. [Means for Solving the Problems] A successive approximation type A/D conversion device of the present invention includes a sample/hold circuit that temporarily stores analog values input from the outside, and a D/A conversion input register. A D/A converter connected to the input register and equipped with a resistor ladder and its selection decoder circuit; analog data stored in the sample and hold circuit; Digital data = D/A
A comparator that compares analog values obtained by inputting to the converter using a successive approximation method and controls the D/A conversion input register based on the result, and a successive approximation timing signal to the D/A conversion input register. The apparatus is configured to include a successive approximation timing generation circuit that outputs data, and means for changing the successive approximation timing time generated by the successive approximation timing generation circuit bit by bit. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a successive approximation type A/D conversion device showing an outline of the present invention. As shown in FIG. 1, this embodiment includes a sample/hold circuit 1, a D/A converter 2 consisting of a resistance ladder 10 and a resistance ladder selection decoder circuit 9, a comparator 3, and a D/A conversion input register. 4, a clock frequency divider 5, a successive approximation timing generation circuit 6, and an A/D conversion result storage register 8
This is the same configuration as the prior art example shown in FIG. The details will be explained below with reference to FIGS. 2 to 6. FIG. 2 is a configuration diagram of a timing generation circuit and a timing control circuit included in a successive approximation type A/D converter for explaining the first embodiment of the present invention. As shown in FIG. 2, in this embodiment, a successive approximation timing generation circuit 6 including a ring counter consisting of a shift register 13 and a NOR circuit 12 is connected to a timing control circuit 7.
When three types of clocks with different periods obtained by changing the frequency division ratio of the clock source circuit 11 are input, and when activated by the A/D conversion start signal, the external analog input sampling timing signal S and successive approximation timing signals B7 to B are input.
O and A/D conversion result storage timings D are sequentially generated at timings controlled by the timing control circuit 7. First, a timing generation circuit 6 consisting of a ring counter
is constructed by cascading ten shift registers (SL) 13, and shifts out data stored in the shift register (SL) 13 bit by bit using a shift clock SCL. This timing generation circuit 6 clears all of the internal shift register 13 by the A/D conversion start signal, and then outputs the output from the NOR logic circuit 12 to the first shift register SL1 by inputting the first shift clock SCL. Take in "1". In this way, by sequentially shifting 1 with the input of the shift clock SCL, successive approximation timings S, B7 . B6. B5
．． B4. B3. B2°Bl, BO, and D are output in sequence. On the other hand, the timing control circuit 7 includes a timing control register 14 that sets a timing mode, and a decoder circuit 15 that decodes the register value bit by bit. In this example, the control register 14 controls each timing using 2-bit registers SCR, B7R, B6R,
B5R, B4R, B3R, B2R, BIR, BOR, D
It is composed of R. Each of these 2-bit control registers 14
By changing the value of , the timing of each successive approximation described above can be changed. That is, the decoder circuit 15
The timing signals S, B7 to BO, D can be changed by configuring them using the logic of the truth table shown in Table 2. In Table 2, a is the 4-frequency division pressure, b is the 2-frequency division pressure, C is the original clock output, and d is the control output for selecting the conversion stop clock. The following is a margin. Table 2 Also, FIG. 3 is a timing diagram for explaining the operation of the successive approximation type A/D converter shown in FIG. 1. For example, the SCR in the timing control circuit 7 described above
, B7R-B4R register value in binary value

[00], B
The register values from 3R to FOR are binary values [01], and D
Similarly, if the register value of B is set to [10], the timing generation circuit 6 generates the A/D in mode 1 as shown in FIG.
Generates a conversion timing signal. Therefore, in this case, 8
The clock required for A/D conversion of bits is 29 clocks, which is a conversion time of 5% compared to the conventional 40 clocks. However, as shown in the timing of the conventional example shown in FIG.
The time required for D conversion was fixed. This means that the time required for one A/D conversion is the data setting time to the D/A conversion input register 4, the D/A conversion time, and the D/A conversion time.
This is because it is the sum of the time for comparing the output and input data and the time for storing the comparison result in the D/A conversion input register 4. However, the D/A conversion time and the comparison time between the D/A output and input data vary depending on the magnitude of change in the analog amount of the D/A conversion output, and when the change in the analog amount is small, the time is reduced. be able to. That is, in this embodiment, the time required for A/D conversion of the lower bits among the digital bits to be successively compared is small. Therefore, by changing the value of the timing control register 14 shown in FIG. 2, various successive approximation timings can be generated. 4 to 6 are timing charts for explaining the operation of the successive approximation type A/D converter shown in FIG. 1, respectively, similarly to FIG. 3. As shown in FIGS. 4 to 6, the various successive approximation timings that occur are 23 clocks each. Examples of 25 clocks and 16 clocks. In this way, by changing the value of the timing control register 14, various successive approximation timings can be generated.
An example of controlling successive approximation timing when precision is required is shown. That is, in FIGS. 5 and 6, the lower two bits of A/
The D conversion timing is omitted, and the timing at which the 6-bit A/D conversion result is stored in the A/D conversion result storage register 8 is shown. In short, if the control is performed at the timing shown in Figure 3,
A/D conversion can be completed in about 72% of the A/D conversion time of the conventional example, and when control is similarly performed at the timing shown in FIG. 4, about 57%, Fifth
The A/D conversion can be completed in approximately 62% of the A/D conversion time when controlled using the timing shown in the figure, and 40% when controlled using the timing shown in FIG. Next, FIG. 7 is a configuration diagram of a timing generation circuit and a control circuit built in a successive approximation type A/D converter for explaining a second embodiment of the present invention. As shown in FIG. 7, this embodiment includes a binary counter 16 that is reset by a start pulse and counts by inputting a clock, and a NAND circuit 17. NOR
The timing generating circuit 6 includes a circuit 18 and an encoder circuit 19 for encoding the decoded code. That is, the binary counter 16 is used as a timing generation circuit, and its feature is that the binary code sequentially output from the binary counter 16 is decoded by an external control signal (mode 1 to mode 4), and the The encoded output is generated as successive approximation timing. Mode 1, mode 2 in this FIG. Mode 3. The truth values of the successive approximation timing generation circuit 6 in mode 4 are as shown in Tables 3 to 6, respectively, and the generation timings are shown in FIGS. 3 to 6, respectively, as in the first embodiment described above. It is shown. Blank spaces below indicate a logical 0 (mode 1) Blank spaces indicate a logical 0 (mode 2) Blank spaces indicate a logical 0 (mode 3) Blank spaces indicate a logical O (mode 4) [Effects of the Invention] As explained above, the successive approximation type A/D converter of the present invention is provided with a successive approximation timing control circuit and controls the successive approximation timing for each bit converted into binary data. When used with the Hiro A/D conversion time function, the A/D conversion timing of the lower bits can be deleted, so
A/D conversion time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a successive approximation type A/D conversion device showing an outline of the present invention, and FIG. 2 is a block diagram of a successive approximation type A/D conversion device for explaining the first embodiment of the present invention. 3 to 6 are timing diagrams for explaining the operation of the successive approximation type A/D converter shown in FIG. 1, and FIG. Successive approximation type A/D for explaining the second embodiment of
FIG. 8 is a block diagram of a successive approximation type A/D conversion device showing an example of a conventional conversion device, and FIG. 9(a) is a block diagram of a timing generation circuit and a control circuit built into the conversion device. (b) is a timing generation circuit diagram of the successive approximation type A/D converter shown in FIG. 8, and FIG. 10 is a timing diagram for explaining the operation of the successive approximation type A/D converter shown in FIG. , FIG. 11 is a configuration diagram of the resistance ladder and selection decoder circuit of the D/A converter shown in FIG. 8, and FIG.
FIG. 2 is a characteristic diagram of each bit and a D/A conversion output for explaining the operation of the successive approximation type A/D conversion device shown in the figure. 1...Sample/hold circuit, 2...
・D/A converter, 3... Comparator, 4...
・D/A conversion input register, 5A, 5B...Clock frequency divider, 6...Successive approximation timing generation circuit (timing generation circuit), 7...Successive approximation timing Control circuit (timing control circuit), 8...
...A/D conversion result storage register, 9...Selection decoder circuit, 10...Resistance ladder 11.
...Clock source circuit, 12...NO
R circuit, 13...Shift register (SLI~5
LIO), 14...timing control register,
15...Encoder times! , 16... Binary counter, 17... NAND circuit, 1
8...NOR circuit, 19...Decoder circuit, ANrN...External analog input terminal, CLK
...External clock input terminal, AY O, ...
・・D/A converter reference power supply, A Vss・・・・・
...D/A converter board power supply, ANC...analog output, S...sample/hold timing signal, BO to B7...A/D conversion of each bit Successive approximation timing signal, D...timing signal for storing A/D conversion results in register, SCL...
・Ring counter shift keys, a to d...
...Selection signal. Agent Patent Attorney Susumu Uchiharac/)Tomo-Sunto-00 0ko 0ko Oko Oko 0ko COOko
ako (of) Figure q ＼ 11th ward 12th ward

Claims (1)

[Claims] A sample that temporarily stores analog values input from the outside.
A hold circuit, a D/A conversion input register, and the D/A conversion input register.
A D/A converter connected to the A conversion input register and equipped with a resistance ladder and its selection decoder circuit; analog data stored in the sample and hold circuit; and binary data set in the D/A conversion input register. a comparator for inputting digital data into the D/A converter and comparing obtained analog values using a successive approximation method, and controlling the D/A conversion input register according to the result;
A successive approximation timing generating circuit that sends out a successive approximation timing signal to the /A conversion input register, and means for changing the successive approximation timing time generated by the successive approximation timing generation circuit bit by bit. Comparison type A/D conversion device.