JPS62133821A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To reduce the required time of A/D conversion and to improve the quantized accuracy by quickening a conversion clock at low-order bit decision more than that at a high-order bit decision. CONSTITUTION:A data selector 13 of a conversion clock generating circuit 1 selects a frequency division output having a low frequency at the decision of the high-order bit in an output of a frequency divider 12 and selects a frequency division output having a high frequency at the decision of a low-order bit and applies the result to a sequential comparison register 2 as a conversion clock 121. Thus, a converted analog input 502 and a reference sequential comparison analog output 401 are compared to form a comparison data 501, which is fetched in a register 2 synchronously with the clock 121 to obtain an A/D conversion output 202.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a successive approximation type analog-to-digital converter (hereinafter referred to as an A/D converter) that converts an analog signal into a digital signal. FIG. 3 shows the configuration of a conventional A/D converter. The analog value to be converted is applied to one terminal 602 of comparator 5. The output of a digital-to-analog converter (hereinafter referred to as a D/A converter) 4 is applied to the other input of the comparator 5. The comparator 6 outputs “1” and “○” depending on the magnitude of the two inputs.
''.However, comparator 5
Isn't the output constant at 1" or "○'" (, D
Since it takes time for the output value of the /A converter 4 to stabilize, the unstable output value causes the comparator 5 to output 1", ○"" unstablely. When the output is sufficiently stable, the reference Conversion clock 121 output by conversion clock generation circuit 1& configured by clock signal source 11 and frequency divider 12
The output of either 111 or ff□I+ of comparator 5 is taken into successive approximation register 2 in synchronization with .

The successive approximation register 2 sequentially stores the digital values of 1" and ○" output by the comparator 6 in order from the MSB to the upper bit, and transmits the digital values to the determined peer).

In order to determine all the lower bits, a digital signal 201 for successive approximation analog value generation is output, and the final converted value -iA/D output 202 is output.

The D/A converter 4 converts the input digital signal 201 and the D/A converter 4 into
A successive approximation analog value 401'i is output using the reference voltage 301 of the A reference reference voltage generation circuit 3. FIG. 4 shows a timing chart of the above-mentioned Mu/D conversion. When the conversion start command becomes “1”, a digital signal 201 of “01111111” is sent to the D/A converter 3.
is input. The D/A converter 3 receives the fifth signal according to the input signal.
Outputs zero [v] as shown in the figure. (However, although the voltage value comparison type is described, the same applies to the current comparison type.

In addition, digital signals are complementary, offset,
It is written in binary code. ) Since comparator 5 has a smaller successive approximation analog value than the analog value to be converted,
After a certain time Δt has elapsed after outputting o”1, the successive approximation register 2
"o" is taken in and the MSB is determined. MSB′f
After determining BiT2i, the successive approximation register 2 changes the determined MSBO value 1o'' to the next determined BiT2 as O'', and further sets the lower binoto value to ``1'' and outputs the digital signal 201' to determine BiT2i. iD/A converter 4
Output to. In the same way that the MSB is determined, BiT
2 is determined as "○", and the following steps are determined by the same procedure up to the LSB.

Problems to be Solved by the Invention According to such a conventional configuration, the conversion time is determined by the frequency of the conversion clock 121 generated by the conversion clock generation circuit 1& and the number of conversion bits. In order to increase the conversion speed or increase the total number of conversion points, it is necessary to increase the frequency of the conversion clock 121, but as mentioned above, it takes a certain amount of time for the output of the D/A converter 4 to become stable. If the frequency is accelerated, conversion errors are likely to occur.

The present invention has been made in view of the above points, and an object of the present invention is to provide an A/D converter that has a simple configuration, reduces the occurrence of conversion errors, and is capable of shortening conversion time or increasing the number of conversion bits. .

Means for Solving the Problems In order to achieve the above object, the present invention sets the conversion clock generated by the conversion clock generation circuit at a high frequency when determining the upper bits, and sets its frequency high when determining the lower bits. The clocks in this exponentiation relationship obtained by passing the reference clock through all the dividers are switched by a data selector, or a conversion clock that changes directly is created by a programmable counter, and the comparator output is sequentially synchronized with this. The present invention has the above-described configuration, so that the output of the successive approximation analog value output from the digital-to-analog converter has a wider fluctuation range when determining the lower focus than when determining the upper bit. It is small and therefore requires a short stabilization time. Therefore, since the output of the comparator becomes stable quickly, data can be taken into the successive approximation register quickly. Therefore, by controlling the frequency of the conversion clock, which is the acquisition timing, the conversion time can be shortened or the number of conversion bits can be increased without reducing the conversion accuracy. FIG. 2 is a block diagram showing an example of a /D converter. In FIG. 1, the same parts as those of the conventional example shown in FIG. 3 are given the same numbers.

In FIG. 1, numeral 13 is a data selector to which the output of the frequency divider 12 is connected, and as the converted bits move from higher to lower, the frequency is switched to a higher frequency division output, and outputted as a converted clock 121.

In this embodiment, since the clock frequency is controlled by the frequency divider 12, the change in the conversion clock 121 is only a multiple of 2, but by using a program counter instead of the frequency divider 12 and data selector 13, It is possible to set the relative change ratio of the conversion clock.

Figure 2 shows A when the conversion clock 121 changes in three stages.
3 is a timing chart showing a /D conversion process. M
SB~BiT4. Regarding the determination of BiTs~Bi7°BiT8, the conversion clock 121 changes. MSB-B
If the clock for determining up to iT4 is the same as the clock in the conventional example shown in Figure 4, the A/D conversion time is 5.75/
It is shortened to 8.

Effects of the Invention As has been described above, according to the present invention, the time required for A/D conversion is shortened, and faster analog signal sampling processing is possible, while the quantization accuracy is higher for the same conversion time. can be improved and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an A/D converter in an embodiment of the present invention, FIG. 2 is a timing chart of A/D conversion of the present invention, and FIG. 3 is a block diagram of a conventional A/D converter. ,
Figure 4 is a timing chart of conventional A/D conversion, Figure 5 is a timing chart of conventional A/D conversion.
The figure is a characteristic diagram showing changes in successive approximation analog values output from a D/A converter built into the A/D converter in correspondence with a timing chart. 1--Conversion clock generation circuit, 2--Successive approximation register, 4--D/A converter, 5--
... Comparator, 12... Frequency divider, 13... Data selector. Name of agent: Patent attorney Toshio Nakao (1 person)
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Claims (1)

[Claims] a comparator having two inputs, an analog value input to be converted and an analog value input for successive approximation; and a successive approximation register that stores output data of the converter in synchronization with a conversion clock;
An analog-to-digital converter comprising a digital-to-analog converter that outputs the analog value for successive approximation, and characterized in that a conversion clock when determining the lower bits is faster than a conversion clock when determining the upper bits.