JP3106771B2 - Successive approximation A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation A / D converter, and more particularly to a successive approximation A / D converter built in a microcomputer formed on a semiconductor substrate.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings. FIG. 8 is a configuration diagram of the successive approximation A / D converter. The successive approximation type A / D converter is a D / A converter 83 (hereinafter DAC83).
A sample and hold circuit 81 for sampling and holding the analog input voltage, a comparator 4 for comparing the output voltage of the sample and hold circuit 81 with the output voltage of the DAC 83, a successive approximation register 80,
It comprises a control circuit 8 for controlling the operation of the successive approximation type A / D converter, and a clock signal generation circuit 7.

[0003] These are the minimum necessary components for realizing a successive approximation A / D converter.

In operation, the output voltage of the DAC 83 corresponding to the bit weight and the analog input voltage V _AN are compared in order from the most significant bit (hereinafter abbreviated as MSB) of the successive approximation register 80 having a plurality of bits, and this is compared with the least significant bit. Bit (hereinafter L
A digital value is obtained by repeating this process up to SB). The principle of operation of the successive approximation type A / D converter is DA
Essentially, when the reference voltage of C83 is V _REF ,

[0005]

[0006] This corresponds to the development. Here, α is an error voltage which is directly caused by the resolution of the successive approximation A / D converter. The conversion result is represented by a bit string of a part bi of the expansion coefficient, and corresponds to the data string of each bit stored in the successive approximation register 80.

FIG. 9 is a timing chart showing the operation of the N-bit successive approximation type A / D converter shown in FIG. In FIG. 9, the periods T _S , T _N ,..., T ₁ are switched in synchronization with the output of the clock generation circuit 7 in FIG.

After the analog input voltage V _AN is sampled in the period T _S , the value of each bit of the successive approximation register 80 is defined as b _N , b _N−1 ,..., B _{1 in} order from the MSB in the period T _N. , B _N are set to “1” and the other bits are set to “0” to set a comparison voltage corresponding to this bit string {bi}.

[0009]

Is output from the DAC 83. Further comparator 4
The analog input voltage V _AN and the comparison voltage V _DAC are compared, and if V _AN > V _DAC , the value of “1” is set, and V _AN <V _DAC
Then, reset the value of “0” to b _N to obtain the MSB
Is determined. Next, in the period T _N−1 , b _{N−1 is set} to “1” and b _N−2 ,..., B ₁ are set to “0”, and the above operation is repeated. Conversion of N bits is finished by repeating N times the operation until period T _1. Development of analog input voltage obtained in this way

[0011]

The bit sequence {bi} of a part bi of the expansion coefficient
Are stored in the successive approximation register 80 as conversion results.

Next, the DAC 83 will be described.

Many types of DACs are known for use in N-bit successive approximation type A / D converters. In particular, in a consumer microcomputer successive approximation type A / D converter formed on a semiconductor substrate. Is a voltage output type so-called resistor ladder type DAC configured by connecting 2 ^N resistors having the same resistance in series, or 1 /
DAC called resistor array ladder or so-called capacitor array system in which capacitors having a weighted capacitance value of 2 ⁱ C (i = 0, 1,..., N-2) are connected in series and parallel by a control line to obtain a desired analog voltage. A DAC in which the system and the capacitor array system are mixed, that is, a system in which the upper i bits of the N bits are D / A converted by the capacitor array system and the remaining (Ni) bits are D / A converted by the resistance ladder system. Types of methods are widely and generally used.

In each of the above methods, the successive approximation register 8
The N-bit data stored in 0 is directly or decoded and used as a DAC control signal.

FIG. 10 shows an example of a DAC using the resistance ladder method.

In FIG. 10, 2 ^N resistors having the same resistance value are connected in series, taps are drawn out from each resistance end, and a switch circuit 101 controlled by an output signal of the decoder 100 is provided at the tip of the tap.

At the i-th (i = 1 to N) -th tap, a divided voltage value 2 ⁱ / ^2N · V _REF of the reference voltage V _REF appears.

N stored in the successive approximation register 80
A desired analog voltage can be obtained by decoding using bit data as an input signal to the decoder 100, selecting only one output signal line, and closing the corresponding switch.

FIG. 11 shows D using the capacitor array method.
It is an example of AC. In FIG. 11, the DAC of the capacitor array type is ^{i i} · C (i = 0, 1,..., N−2).
(N-1) capacitors having a weighted capacitance value, one capacitor having a capacitance value of 1/2 ^N- 2.C, and ^N- bit data stored in the successive approximation register 80. And N switches.

For example, when the data of the i-th bit of the successive approximation register 80 is "1", the contact of the switch corresponding to this bit is connected to the reference voltage _VREF , and the data becomes "0".
In such a case, if control is performed such that the contact of the corresponding switch is connected to the ground potential side, the equivalent circuit is as shown in FIG. 12, for example. Therefore, the potential of the contact 120 outputs a voltage determined by the voltage division ratio of each capacitor.

[0022]

When the conventional N-bit successive approximation A / D converter described above is constructed on a semiconductor substrate, it is difficult to maintain the accuracy of the DAC 83 for N> 10. Therefore, it is difficult to perform A / D with stable accuracy. The ladder resistance method, the capacitor array method, and the mixed type of the resistance ladder method and the capacitor array method described above are widely used as the method of realizing the DAC unit of the successive approximation type A / D converter formed on the semiconductor substrate. This is because the relative error of the resistance value of each resistance element and the relative error of the capacitance ratio of each capacitor can be made relatively small in the manufacturing process.

However, in the resistance ladder method, the required number of resistance elements increases exponentially with the increase of N, so that the layout area increases, and the relative error also increases. It is no longer realistic. Also in the capacitor array system, the required capacitors increase with the increase of N, and it becomes difficult to keep the relative error of the capacitance ratio small. A similar problem occurs in a system in which the resistance ladder system and the capacitor array system are mixed.

An object of the present invention is to minimize the layout area of the A / D converter without lowering the conversion accuracy even when the value of N increases.

[0025]

SUMMARY OF THE INVENTION The successive approximation type A /
The D converters are initialized to predetermined voltage values, respectively, and
First and second hold circuits for holding the first and second hold circuits;
The average voltage of the voltage held in the second hold circuit is
A first means for obtaining the average voltage;
A comparator for comparing the input voltage with the input voltage;
A register for latching the result, and a second register for holding the average voltage.
3 and the second circuit according to the output of the comparator.
The voltage held in the hold circuit of the third
Is the second signal transmitted to one of the second hold circuits.
And the new means obtained by the first means.
Analog input voltage for a predetermined number of times
In the successive approximation type A / D converter that performs successive approximation with
The first, second and third hold circuits are respectively
And a voltage follower.
Held on the capacitor on the input side of the Tage Follower
When transmitting the voltage to the capacitor on the output side,
The bias voltage is applied to the common end of the input and output side capacitors.
And pressurizes the held voltage to a predetermined value for transmission.
And a bias voltage generating circuit. Also before
Whether the boost operation is performed depends on the conversion result of the most significant bit.
Is determined according to.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram showing one embodiment of the present invention. FIG. 2 is a flowchart showing the operation of the successive approximation A / D converter shown in FIG. FIG. 3 shows D in FIG.
This is an example in which AC12 is more specifically configured using MOSFETs.

FIG. 4 is a timing chart showing the operation of the successive approximation type A / D converter configured as shown in FIG.

In FIG. 1, an ANI terminal 10 is an analog voltage input terminal, and an AV _REF terminal 9 is a reference power supply voltage terminal. C1 to C4 are capacitors, and particularly, the capacitors C1 and C2 have the same capacitance value. Power supply 11
Has a voltage value of the half value 1 / 2V _REF with respect to the reference supply voltage V _REF as described below is a bias power source for applying a voltage to one end of a capacitor C1 -C4. The clock generation circuit 7 operates the A / D converter.

The DAC 12 has an output signal line 13. The comparator 4 has the input of the output of the hold circuit 6 and the output of the _{DAC 12} and compares the magnitude of the analog input voltage V _AN with the voltage value of the output voltage V _DAC of the _{DAC 12} . The conversion result is stored in the result register 5, and the output 15 of the comparator 12 is latched in synchronization with the signal 14 output from the control circuit 8.

S0 to S9 are switches, and switches S
0, switch S1, and switch S4 are controlled by a control signal 16, switches S2 and S6, switch S7 are controlled by a control signal 17, and switches S3, S5, and S8 are controlled by a control signal 18 to open and close. Further, the switch S9 is turned to the ground potential or 1 /
Selection is made between 2 V _REF potential. The control signal 17 and the control signal 18 are output according to the output of the comparator 4, and the analog voltage V _AN held by the hold circuit 6 and the DAC
12 comparison results V _AN> V _DAC the output voltage V _DAC of
If so, the control signal 18 becomes active and the switch S
3, switch S5 and switch S8 are closed, and V _AN <V _DAC
, The control signal 17 becomes active and the switch S
2, switch S6 and switch S7 are closed.

The actual operation will be described with reference to FIGS.

First, the switch S9 is set to the ground potential side in the initial state, and the potential of the capacitor C1 is charged and discharged to the _VREF potential and the potential of the capacitor C2 is charged and discharged to the ground potential with all other switches opened. (The circuit for charging / discharging is not shown in the figure.) Next, the switches S0, S1, and S4 are closed. The analog input voltage is sampled by closing the switch S0, and the switches S1 and S4
, The potential of the capacitor C3 is fixed to V _REF and the potential of the capacitor C4 is fixed to the ground potential. After opening the switches S0, S1, S4, the switches S7, S8
Close. At this time, since the capacitors C1 and C2 have the same capacitance value, the potential at the common end of each capacitor is the potential V _C1 of the capacitor _C1 and the potential V _C of the capacitor C2.
Average potential of _C2 1/2 · (C _C1 + V _C2 ) = 1/2 · V _REF
Becomes This potential is used as a comparison voltage V _DAC , the comparator 4 compares the V _DAC with the analog voltage V _AN held in the hold circuit 6, and stores the obtained digital output b _N in the result register 5. (If V _AN > V _DAC, b _N =
1, if V _AN <V _DAC , define b _N = 0) The operation up to this point determines the most significant bit b _N of the digital value.

Next, the voltage transmitting means including the voltage follower will be described. In FIG. 1, the voltage followers 1, 2, and 3 are always used in combination with two capacitors. Capacitors C1,
There are four types, C3 and voltage follower 1, capacitors C1 and C4 and voltage follower 2, capacitors C2 and C3 and voltage follower 2, and capacitors C2 and C4 and voltage follower 3, all of which have the configuration shown in FIG. FIG. 6 shows an example in which the voltage follower is constituted by a MOSFET. Here, the switch circuits 64 and 66 correspond to any one of the switches S2, S3, S5, S6, S7 and S8.
And a P-chMO as shown in FIG.
It is configured by combining an SFET and an N-ch MOSFET. By the way, when the differential input stage of the voltage follower is constituted by an N-ch MOSFET as shown in FIG. 6, if the gate voltage on the positive-phase input side becomes close to the threshold voltage, the impedance between the source and the drain of the MOSFET becomes high impedance. It will not work. The bias voltage generation source 60 provided to solve this problem includes resistors 31 and 3 having the same resistance value.
2 and a P-ch MOSFET 30, and corresponds to the switch S9 in FIG. P-chMOSFET30
, The common terminal 61 of the capacitor 62 and the capacitor 63 is connected to the ground potential or 1 /
Any voltage value of 2V _REF is biased. First P
Switch 6 with the ch-channel MOSFET 30 turned off and the common end 61 of the two capacitors biased to ground potential.
4 is closed and the input voltage V _IN is sampled by the capacitor 62. At this time, the switch 66 is also closed. Thereafter, the switch 64 is opened, the P-ch MOSFET 30 is turned on, and the common terminal 61 of the two capacitors 62 and 63 is connected to the common terminal 61.
Bias the voltage at V _REF . With this operation, the contact 65
Is V _IN + ／ V _REF . Since the reference voltage V _REF is usually used at about 5 V, the potential of the contact 64 is 2.5 V even when V _IN = 0 V, and this value is a voltage value at which the voltage follower can function sufficiently. Therefore, the contact 69
, A voltage value of V _IN + 1 / 2V _REF appears. here,
By opening the switch 66, turning off the P-ch MOSFET 30 and returning the potential of the common terminal 61 to the ground potential, the potential of the contact 67 becomes V _IN , indicating that the voltage has been transmitted. If the input voltage V _IN is equal to or more than Ｖ V _{REF, the} voltage follower functions sufficiently without performing the above operation. Whether the input voltage V _IN is 1 / 2V _REF or the conversion of the first 1 bit, i.e. to find at the time of determining the most significant bit of the result registers 5, if the most significant bit b _N = 1 P- The chMOSFET 30 is not turned on.

Now, to determine the next bit b _N−1 ,
If b _N = 0, switches S2, S6 and S7 are turned on,
If b _N = 1, switches S3, S5 and S8 are turned on.
By operating according further the bias voltage of the common terminal of the capacitor as previously described to the value of b _N, b _N = voltage V _C1 = 1 / 2V stored in the capacitor C1 when the 0
_REF is transmitted to the capacitor C3 via the voltage follower 2, and the voltage V _C4 =
0V is transmitted to the capacitor C2 via the voltage follower 3. On the other hand, when b _N = 1, the voltage V _C2 = １ ／ V _REF stored in the capacitor C2 is transmitted to the capacitor C4 via the voltage follower 2, and
The voltage V _C3 = V _REF stored in 3 is transmitted to the capacitor C 1 via the voltage follower 1. Then, after all switches are opened, the switches S7 and S8 are opened.
Close the value of V _{DAC is, V DAC = 1/2 (} 1 / 2V
_REF + 0) = 1/4 V _REF (when b _N = 0) V _DAC = 1
/ 2 (V _REF + ／ V _REF ) = ３V _REF (b _N =
1). By comparing the obtained comparison voltage V _DAC with the analog input voltage V _AN , b _N−1 is determined.
Thereafter, if this operation is sequentially repeated, the bit strings b _N , b _N−1 ,
.., B ₁ are determined, and the A / D conversion is completed. After N operations, the comparison voltage V _DAC is

[0035]

Thus, it is clear that the same development as that of the related art is performed.

1/2 ^{N + 1} · V _REF is an error voltage, and if N is increased, the error voltage can be reduced.

FIG. 3 is a more specific example of the configuration shown in FIG.

Here, the clock generation circuit 7 in FIG.
Hold circuit 6, switch S0, analog input terminal 10
Has been omitted. The switches S1 to S8 are composed of MOSFETs as shown in FIG. FIG. 4 is a timing chart showing the operation of FIG. 3 and shows a period Ti (i = N,.
In 1), 1-bit conversion is performed. The period Ti is composed of three layers of clocks φ0, φ1, φ2. FIG. 4 particularly shows a case where the conversion result is 01101...

FIG. 7 is a diagram showing a second embodiment of the present invention. FIG. 7 is a modification of the bias voltage generation source 60 in FIG. Other configurations are the same as those in FIG.
Elements other than the result register 5 are omitted. The power supply of the NOR gate 70 uses the reference voltage V _REF and b
_{When N} = 0, the voltage biased on the signal line 23 depends on the value of the signal line 28. When the value of the signal line 28 is "1", the ground potential is set, and when the value of the signal line 28 is "0". NO when
The R gate 70 has a so-called self-bias structure in which an input signal and an output signal are short-circuited, and outputs 1/2 V _REF to the signal line 23, respectively. However, the logical threshold value of the NOR gate 70 is set to 1/2 V _REF .

Since a resistor is used in the bias voltage generating source 60 in FIG. 6, if the resistance value is reduced, current consumption becomes a problem. Therefore, the resistance value is set to a value of about 10 KΩ. When a resistor is to be formed on a semiconductor substrate, an ion implantation resistor or the like is widely and generally used. However, as shown in this embodiment, the ion implantation is performed with a low current consumption by forming a NOR gate and setting a low mutual conductance of the MOSFET. The bias voltage generation source can be configured with an area about 1/10 of the resistance. Therefore, the total area is advantageous.

[0042]

As described above, according to the present invention, the DAC is essentially replaced with the capacitor C1 shown in FIG. 1 without using the conventional resistor array or capacitor array.
And only two capacitors C2, the capacitor C2 is used.
The area can be reduced by 0%. Also, when performing N-bit A / D conversion, even if N is increased to increase the conversion accuracy, D
Since the circuit configuration of AC does not depend on N, there is an effect that the circuit can be easily changed only by increasing the number of bits of the result register 5 without any change.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation shown in FIG. 1;

FIG. 3 is a detailed view of the embodiment in FIG. 1;

FIG. 4 is a timing chart for explaining the embodiment of the present invention.

FIG. 5 is a switch circuit diagram.

FIG. 6 is a voltage follower circuit diagram.

FIG. 7 is a diagram for explaining a second embodiment of the present invention.

FIG. 8 is a block diagram of a conventional successive approximation type A / D converter.

FIG. 9 is a diagram illustrating a successive approximation A / D converter.

FIG. 10 is a diagram illustrating a resistor ladder type DAC.

FIG. 11 illustrates a capacitor array type DAC.

FIG. 12 is an equivalent circuit diagram of a capacitor array type DAC.

[Explanation of symbols]

1, 2, 3 Voltage follower 4 Comparator 5 Result register 6 Hold circuit 7 Clock generation circuit 8 Control circuit 9 Reference power supply voltage terminal 10 Analog input terminal 11 Bias voltage power supply 12, 83 D / A converter 13 DAC output signal 14 , 16,17,18,20,21,22,27,2
8 Output signal line of control circuit 15 Output of comparator C1, C2, C3, C4, 62, 63 Capacitors S0, S1, S2, S3, S4, S5, S6, S7, S
8, S9, 52, 64, 66 Switch 50, 67, 68 N-ch MOSFET 30, 51 P-ch MOSFET 31, 32 Resistance 53 Inverter 70 NOR gate 23, 61 Output of bias voltage generation circuit 65, 69 Contact

Claims (2)

(57) [Claims] 1. A first and a second hold circuit, each initialized to a predetermined voltage value and holding a voltage, and obtaining an average voltage of the voltages held in the first and the second hold circuits. A comparator for comparing the average voltage with an analog input voltage using the average voltage as a reference voltage, a register for latching a comparison result of the comparator, a third hold circuit for holding the average voltage, A second means for transmitting a voltage held in the third hold circuit to one of the first and second hold circuits in accordance with an output of a comparator, wherein the first means A successive approximation type A / D converter that performs successive approximation with an analog input voltage a predetermined number of times using the obtained new average voltage as a reference voltage.
The first, second and third hold circuits respectively
A capacitor and a voltage follower.
The voltage is held by the capacitor on the input side of the voltage follower.
Transfer the output voltage to the capacitor on the output side.
To the common end of the input side and output side capacitors.
Giving a bias voltage to boost the held voltage by a predetermined value.
A successive approximation type A / D converter comprising a bias voltage generating circuit for transmitting . 2. The highest priority is whether to perform the boosting operation.
It is determined according to the result of bit conversion.
The successive approximation type A / D converter according to claim 1 .