JPH1117541A - Test circuit for d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit with a small scale that checks monotonousity of the D/A converter. SOLUTION: A digital signal is given to a D/A converter 1 and the converted analog signal is given to a comparator circuit 2 provided with a sample-and-hold circuit, a digital signal whose bits is increased by 1-LSB with respect to the digital signal above is given to the D/A converter and the converted analog signal is given to the comparator circuit 2. The monotonousity of the D/A converter is tested by selecting a switch circuit of the comparator circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit for testing the monotonicity of a D / A converter.

[0002]

2. Description of the Related Art In general, monotonicity is used to express the accuracy of a D / A converter. Japanese Patent Application Laid-Open No. 5-335950 discloses a test circuit for testing the monotonicity. FIG. 5 is a block diagram of a test circuit of a D / A converter described in Japanese Patent Application Laid-Open No. 5-335950.

In FIG. 1, a digital output of an A / D converter 32 for converting an analog signal output of a D / A converter 31 into a digital quantity, whose monotonicity is guaranteed, is stored in a latch 33. The increment circuit 35 adds 1 to the output value of the XOR circuit 34 for all bits of the data stored in the previous clock. This increment circuit 3
5 is stored in a latch 36, and the adder 37 is configured to add the incremented result to the value stored in the first latch 33 at the next clock.

[0004] The operation of the circuit of FIG. 5 configured as described above will be described below. The test circuit of the D / A converter converts an analog value of the D / A converter 31 to be tested into a digital value by the A / D converter 32 which is guaranteed monotonic. If the digital value of the A / D converter 32 is a two's complement code, the digital value of the A / D converter 32 is stored in the latch 33. By inputting the output of the latch 33 to an XOR circuit 34 having one of two inputs connected to a power supply (VDD), all bits are inverted.

Next, 1 is added to the output value of the XOR circuit 34 by the increment circuit 35. The output of the increment circuit 35 is stored in the latch 36. The above operation converts the value stored in the latch 33 into the opposite polarity of the two's complement code. The input to the adder 37 is A /
Latch 36 with inverted polarity of digital value of D converter 32
And the value stored in the latch 33 at the next clock of the digital value of the A / D converter 32. When the digital signal input to the D / A converter 31 is changed from the minimum value to the maximum value, if the result calculated by the adder 37 becomes 0 or a positive value, monotonicity is maintained. .

[0006]

The problem with the above method is that the circuit scale becomes large. The reason is that the analog output of the D / A converter is converted into a digital value by an A / D converter whose monotonicity is guaranteed, and the digital value is guaranteed monotonicity by using an increment circuit, an adder circuit or the like. This is because it has been determined whether or not it has been performed.
The present invention has been made under such a background, and an object of the present invention is to provide a D / A converter test circuit having a small circuit scale.

[0007]

According to a first aspect of the present invention, in a test circuit of a D / A converter, an analog output of a D / A converter under test to which a digital signal is input has a sample hold circuit. A comparator circuit that is input to the + input side and the − input side of the comparator circuit and includes the sample and hold circuit, compares a value input to the + input side with a value input to the − input side,
Provided is a test circuit for a D / A converter, which outputs a comparison result.

According to a second aspect of the present invention, in the comparator circuit including the sample and hold circuit,
An input side is connected to a first terminal of a first switch circuit, the + input side is connected to a first terminal of a second switch circuit, and a second terminal of the first switch circuit is connected to a first terminal of a first capacitor. One electrode is connected to a first terminal of a third switch circuit, and a second terminal of the second switch circuit is connected to a first electrode of a second capacitor and a second terminal of the third switch circuit. , The second of the first capacitor
The electrode is connected to a first terminal of a fourth switch circuit, a first terminal of a sixth switch circuit, and an input terminal of a first inverter circuit, and a second electrode of the second capacitor is connected to a fifth switch. A first terminal of the circuit, a first terminal of a seventh switch circuit, and an input terminal of a second inverter circuit, and an output terminal of the first inverter circuit is connected to the fourth terminal.
The second terminal of the switch circuit, the second terminal of the seventh switch circuit, and the input terminal of the third inverter circuit, and the output terminal of the second inverter circuit is connected to the third terminal of the fifth switch circuit. Two terminals, a second terminal of the sixth switch circuit, and an input terminal of a fourth inverter circuit; an output terminal of the third inverter circuit is connected to a first input terminal of a first NAND circuit; The output terminal of the fourth inverter circuit is connected to the first terminal of the second NAND circuit.
An output terminal of the second NAND circuit is connected to an input terminal, an output terminal of the second NAND circuit is connected to a second input side of the first NAND circuit, and an output terminal of the first NAND circuit is connected to the second NAND circuit. A first input terminal connected to a second input terminal;
2. The test circuit for a D / A converter according to claim 1, wherein the comparison result is output from an output terminal of an AND circuit.

According to a third aspect of the present invention, the threshold voltage of the first inverter circuit is equal to the threshold voltage of the second inverter circuit, and the threshold voltage of the third inverter circuit is equal to the threshold voltage of the third inverter circuit. The threshold voltage of the fourth inverter circuit is equal to the threshold voltage of the fourth inverter circuit, and the threshold voltage of the first inverter circuit and the threshold voltage of the second inverter circuit are equal to the threshold voltages of the third inverter circuit and the fourth inverter circuit. 3. A test circuit for a D / A converter according to claim 2, wherein the test circuit has a voltage lower than the hold voltage.

According to a fourth aspect of the present invention, in the comparator circuit including the sample and hold circuit,
An input side is connected to a first terminal of the first switch circuit,
The + input side is connected to a first terminal of a second switch circuit, and the second terminal of the first switch circuit is connected to a first electrode of a first capacitor and a first terminal of a third switch circuit. And the second terminal of the second switch circuit is
A second terminal connected to a first electrode of the second capacitor and a first terminal of the fourth switch circuit;
A terminal connected to a negative input terminal of the comparator circuit, a second terminal of the fourth switch circuit connected to a positive input terminal of the comparator circuit, and outputting the comparison result from an output terminal of the comparator circuit. A test circuit for a D / A converter according to claim 1, wherein:

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS D / A according to one embodiment of the present invention
The test circuit of the converter will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In this figure, reference numeral 1 denotes a D / A converter under test, which outputs an analog signal by inputting a digital signal. Reference numeral 2 denotes a comparator circuit having a sample-and-hold circuit.
The value input to the input side, the value input to the + input side is compared with the value input to the-input side, and a comparison result is output.

FIG. 2 is an internal circuit diagram of the comparator circuit 2 including the sample and hold circuit of FIG. In this figure, the − input side is connected to the first terminal of the switch circuit 3, and the second terminal of the switch circuit 3 is connected to the first electrode of the capacitor 10 and the first terminal of the switch circuit 5. The + input side is connected to a first terminal of the switch circuit 4, and a second terminal of the switch circuit 4 is connected to a first electrode of the capacitor 11 and a second terminal of the switch circuit 5.

The second electrode of the capacitor 10 is connected to a first terminal of the switch circuit 6, a first terminal of the switch circuit 8, and an input terminal of the inverter circuit 12. The second electrode of the capacitor 11 is connected to the switch circuit 7.
, The first terminal of the switch circuit 9, and the input terminal of the inverter circuit 13. An output terminal of the inverter circuit 12 is connected to a second terminal of the switch circuit 4, a second terminal of the switch circuit 9, and an input terminal of the inverter circuit 14. The output terminal of the inverter circuit 13 is connected to the second terminal of the switch circuit 7.
Terminal, a second terminal of the switch circuit 8 and an input terminal of the inverter circuit 15.

The output terminal of the inverter circuit 14 is N
An output terminal of the inverter circuit 15 is connected to a first input terminal of a NAND circuit 17, and an output terminal of the NAND circuit 17 is connected to a second input terminal of the NAND circuit 16. Connected to the terminal,
The output terminal of the NAND circuit 16 is connected to the second input terminal of the NAND circuit 17, and the comparison result is output to the output terminal O.
The output is from the UT.

Next, the circuit operation of FIGS. 1 and 2 will be described with reference to the timing chart of FIG. D / A for test
The digital input value applied to the converter 1 increases by 1 LSB from the minimum value in a predetermined cycle. In a period T1 in FIG. 3, a digital signal is input to the D / A converter 1 under test, and a voltage (V1) converted into an analog voltage value is supplied to the + input side and-of the comparator circuit 2 including the sample and hold circuit. Input to the input side.

At this time, the switching circuit 3 and the switching circuit 6
The switch circuit 7 is turned on, the switch circuits 4, 5, 8, and 9 are turned off. The D / A converter 1 under test converts the first electrode of the capacitor 10 to the D / A converter 1. Analog voltage (V
1) is applied and feedback is applied to the inverter circuit 12, so that the threshold voltage (VTH1) of the inverter circuit 12 is provided on the second electrode side of the capacitor 10.
Is added.

Next, in a period T2, a digital input signal increased by 1 LSB is input to the D / A converter 1 under test, and the converted analog voltage (V2) is supplied to the comparator circuit 2 having a sample and hold circuit. + Input side and-
Input to the input side. At this time, the switch circuits 4, 6, and 7 are turned on, the switch circuits 3, 5, 8, and 9 are turned off, the capacitor 10 keeps its previous state, Since the analog voltage (V2) is charged on the first electrode side and the feedback is applied to the inverter circuit 13, the threshold voltage (V2) of the inverter circuit 13 is provided on the second electrode side of the capacitor 11.
TH2) is added.

In this case, the threshold voltage (VTH1) of the inverter circuit 12 is equal to the threshold voltage (VTH2) of the inverter circuit 13, and the threshold voltages (VTH1, VTH2) of the inverter circuits 12 and 13 are equal. ) Indicates the inverter circuit 14
And a threshold voltage lower than the threshold voltage of the inverter circuit 15 and the threshold voltage of the inverter circuit 14;
The threshold voltages of the inverter circuits 15 are set to be equal.

Next, in the period T3, the switch circuits 5, 8, and 9 are turned on, the switch circuits 3, 4, 6, and 7 are turned off, and the first electrode of the capacitor 10 is turned off. And the first electrode of the capacitor 11 is short-circuited, and the voltage becomes (V1 + V2) / 2. The voltage of the second electrode of the capacitor 10 is (VTH1−V1) + (V1 + V2) / 2 = V
TH1 + V2 / 2−V1 / 2, and the voltage of the second electrode of the capacitor 11 is (VTH2−V2) + (V1 + V2) / 2 =
VTH2 + V1 / 2−V2 / 2.

The voltage applied to the input side of the inverter circuit 12 is VTH1 + V2 / 2−V1 / 2, which is higher than the threshold voltage VTH1 of the inverter circuit 12, so that the inverter circuit 12 outputs Low. The voltage applied to the input side of the inverter circuit 13 is VTH
2 + V1 / 2−V2 / 2, which is lower than the threshold voltage VTH2 of the inverter circuit 13, so that the inverter circuit 13 outputs high. Therefore, the output of the comparator circuit 2 including the sample and hold circuit is Low.
Becomes Further, in the period T4, all the switch circuits are turned off.
FF state.

The above operations of the periods T1 to T4 are sequentially repeated, and if the output of the comparator circuit 2 including the sample-and-hold circuit is always low, the D / A converter is guaranteed monotonic. When High is output even once, monotonicity is not guaranteed.

Next, a second embodiment of the comparator circuit having the sample and hold circuit of the present invention will be described with reference to the circuit diagram of FIG. In FIG. 4, the capacitors 26 and 27 are charged to the output voltage of the D / A converter when the switch circuits 22 and 23 are ON. The comparator circuit 28 includes the switch circuit 2
4. When the switch circuit 25 is ON, the capacitor 2
6. The charge of the capacitor 27 is input, and the comparison result is output.

Next, the operation of the circuit of FIG. 4 will be described. The digital input value applied to the D / A converter under test 1 is increased by 1 LSB from the minimum value. A digital signal is input to the D / A converter 1 under test, and the voltage (V1) converted into an analog voltage value is input to the + input side and the − input side of the sample and hold circuit. At this time, the switch circuit 22
Are turned on, the switch circuits 23, 24 and 25 are turned off, and the capacitor 26
Is charged with the analog voltage (Vl) converted by the D / A converter under test 1.

Next, 1 LSB is applied to the D / A converter 1 under test.
A digital input signal increased by an amount is input, and the converted analog voltage (V2) is input to the + input side and the − input side. At this time, the switch circuit 23 is turned on, the switch circuits 22, 24 and 25 are turned off, the capacitor C3 keeps the previous state, and the capacitor C4 is charged with the analog voltage (V2). .

Next, since the switch circuits 24 and 25 are in the ON state and the switch circuits 22 and 23 are in the OFF state, the charge stored in the capacitor 26 is supplied to the input side of the comparator circuit 28 and stored in the capacitor 27. The stored electric charge is +
Applied to the input side and compared by a comparator circuit 28,
Output the comparison result. If the output result is always Low, the monotonicity is guaranteed, and the periods T1, T2,
The operation of T3 is sequentially repeated, and if the output of the comparator circuit 2 including the sample and hold circuit is always Low, it means that the D / A converter has guaranteed monotonicity.

The operation of one embodiment of the present invention has been described above in detail with reference to the drawings. However, the present invention is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention.

[0027]

As described above, according to the present invention, D / A can be performed by a test circuit having a small circuit scale.
The converter can be tested for monotonicity. The reason is that in the prior art, an A / D converter, an XOR circuit, an increment circuit, an adder circuit, and a latch circuit were required. However, the present invention uses a comparator circuit having a sample and hold circuit, and uses a switch circuit. By switching at the above timing, a monotonicity test equivalent to that of the related art can be performed. For example, when testing the monotonicity of an 8-bit D / A converter, in the prior art, XOR circuit: 10 elements × 8 bits = 80 elements Increment circuit: 36 elements × 8 bits = 360 elements Adder circuit: 34 elements × 8 Bit = 340 elements Latch circuit: 8 elements × 8 bits × 2 = 128 elements Total = 768 elements, and further requires an A / D converter with guaranteed monotonicity.

The number of elements in the first embodiment of the present invention is as follows: switch circuit: 1 element × 7 = 7 elements INV circuit: 2 elements × 4 = 8 elements NAND circuit: 4 elements × 2 = 8 elements Capacitor: 1 element × 2 = 2 elements Total = 25 elements, and the effect that a monotonic test equivalent to the conventional example can be realized with about 1/30 the number of elements can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of a comparator circuit including a sample and hold circuit of a block diagram showing an embodiment of the present invention.

FIG. 3 is an operation timing chart according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the comparator circuit including the sample hold circuit of the block diagram showing the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional technique.

FIG. 6 is a circuit diagram showing a commonly used increment circuit.

FIG. 7 is a circuit diagram showing a commonly used addition circuit (1 bit).

[Explanation of symbols]

1, 31 D / A converter 2 Comparator circuit provided with sample hold circuit 3, 4, 5, 6, 7, 8, 9, 22, 23, 24, 25
Switch circuit 10, 11, 26, 27 Capacitor 12, 13, 14, 15 Inverter circuit 16, 17 NAND circuit 28 Comparator circuit 32 A / D converter 33, 36 Latch 34 XOR circuit 35 Increment circuit 37 Adder

Claims (4)

[Claims] In a test circuit of a D / A converter, an analog output of a DA converter under test to which a digital signal is input is input to a + input side and a − input side of a comparator circuit having a sample and hold circuit. A comparator circuit provided with the sample-and-hold circuit, compares the value input to the + input side with the value input to the-input side, and outputs a comparison result. Transducer test circuit. 2. The comparator circuit including the sample and hold circuit, wherein the-input side is connected to a first terminal of a first switch circuit, the + input side is connected to a first terminal of a second switch circuit, A second terminal of the first switch circuit is connected to a first electrode of a first capacitor and a first terminal of a third switch circuit, and a second terminal of the second switch circuit is connected to a second capacitor Is connected to the first electrode of the third switch circuit and the second terminal of the third switch circuit, and the second electrode of the first capacitor is connected to the first terminal of the fourth switch circuit, the first terminal of the sixth switch circuit, The second electrode of the second capacitor is connected to an input terminal of the first inverter circuit, and the second electrode of the second capacitor is connected to the first terminal of the fifth switch circuit, the first terminal of the seventh switch circuit, and the input of the second inverter circuit. To the terminal The output terminal of the first inverter circuit is connected to the second terminal of the fourth switch circuit and the second terminal of the seventh switch circuit.
An output terminal of the second inverter circuit, a second terminal of the fifth switch circuit, a second terminal of the sixth switch circuit, and a fourth inverter. An output terminal of the third inverter circuit is connected to an input terminal of the third inverter circuit.
The fourth inverter circuit is connected to a first input terminal of a D circuit, and an output terminal of the fourth inverter circuit is connected to a second NAN.
A first input terminal of the D circuit; an output terminal of the second NAND circuit;
An output terminal of the first NAND circuit is connected to a second input side of the ND circuit.
2. The test circuit for a D / A converter according to claim 1, wherein the test circuit is connected to a second input terminal of the ND circuit, and outputs the comparison result from an output terminal of the first NAND circuit. 3. The threshold voltage of the first inverter circuit is equal to the threshold voltage of the second inverter circuit, and the threshold voltage of the third inverter circuit is equal to the threshold voltage of the fourth inverter circuit. The threshold voltage of the first inverter circuit and the threshold voltage of the second inverter circuit are lower than the threshold voltage of the third inverter circuit and the threshold voltage of the fourth inverter circuit. 3. The test circuit for a D / A converter according to claim 2, wherein: 4. The comparator circuit including the sample and hold circuit, wherein the-input side is connected to a first terminal of a first switch circuit, and the + input side is connected to a first terminal of a second switch circuit. A second terminal of the first switch circuit is connected to a first electrode of a first capacitor and a first terminal of a third switch circuit; and a second terminal of the second switch circuit is connected to a second terminal of the second switch circuit. The first terminal of the capacitor and the first terminal of the fourth switch circuit, the second terminal of the third switch circuit is connected to the-input terminal of the comparator circuit, the fourth terminal of the fourth switch circuit 2. The test circuit for a D / A converter according to claim 1, wherein two terminals are connected to a + input terminal of the comparator circuit, and the comparison result is output from an output terminal of the comparator circuit.