JPH0681048B2 - A / D converter - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an A / D converter, and more particularly to a parallel A / D converter suitable for integration into an integrated circuit.

[Background of the Invention]

The parallel A / D converter that achieves high-speed A / D conversion has an exponentially increasing circuit scale with respect to the number of bits. The circuit can be simplified and is suitable for integration into an integrated circuit (JP-A-57-131123).

This A / D converter uses the input voltage V _in for three comparators 10
Compared with each divided voltage of the reference voltage V _REF
The upper 2 bits D _U are determined via the encoder 18, and one of the four switch groups 12 to 15 is selected and turned on based on this result to turn on the reference divided voltage selected by the three comparators 11. V _in is compared and the lower 2 bits D _L are determined via the encoder 19. 4 The converter as an example the bit is 15 compares the input voltage V _in and the reference divided voltage of 15
Complete parallel A / D for simultaneous comparison with each of the comparators
Unlike the converter, the upper two bits are determined by the three comparators, and then the lower two bits are determined by the other three comparators. In general the A / D conversion of 2n bits determine the lower n bits in the upper n bits, the other 2 ⁿ -1 pieces of comparators 2 ⁿ -1 pieces of comparators. Therefore, the required number of comparators is 2 ^{n + 1} -2, which is significantly smaller than 2 ^{2n in} the case of the fully parallel type. For example, in the case of 10 (n = 5) bits, 62 comparators are required as opposed to 1024 in the case of the complete parallel type.

By the way, the A / D converter shown in FIG. 1 uses different comparator groups to determine the upper bits and the lower bits to perform the comparison operations at different timings. Mismatch may occur. For example, when V _in approaches the reference divided voltage V _R1 ,
The output of the comparator 10 (a), which should be originally constant, fluctuates, and the switches selected during conversion of the lower bits (for example,
12) may switch to an adjacent switch group (for example, 13) and an error may occur. Further, due to the difference in the arrangement of the upper comparator 10 and the lower comparator 11 on the integrated circuit and the difference in the comparison time, the switch group (for example, 12) selected by the comparison result of the upper bits is not appropriate, and the adjacent switch group (for example, 13). ) Should be used for comparison of lower bits. These are conventional A / Ds that belong to series-parallel type
This is a problem peculiar to the converter and often causes the converter to malfunction or deteriorates the conversion accuracy.

[Object of the Invention]

An object of the present invention is to solve the above problems and prevent mismatches in circuit operation in upper bit conversion and lower bit conversion,
It is to provide a series-parallel type integrated circuit A / D converter that is highly accurate and does not cause malfunctions.

[Outline of Invention]

To achieve the above object, in the present invention, a charge-balanced comparator having a sample-hold function is used as the comparator, and a latch for holding the conversion result of the upper bit is provided to stably select the switch group in the lower bit conversion. At the same time, a circuit configuration for covering the mismatch is provided by slightly increasing the comparator used for the lower bit conversion and expanding the range of the reference divided voltage to be compared up and down. It was made clear that a highly accurate and stable series-parallel type integrated circuit A / D converter could be realized.

Example of Invention

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 2, in particular, the portion (a) is a diagram showing a circuit configuration of the A / D converter of the present invention. For simplicity, a resolution of 4 bits is taken as an example. The charge-balanced MOS comparators 16 and 17 essentially having a sample-hold function are used for conversion of upper and lower bits, respectively, and a reference voltage V _REF consisting of ₁₆ resistors R _{1 to} R _{16 is} used.
Compare divided terminal voltages of pressure circuit and the input voltage V _in the. The comparison results of the high-order comparator group 16 and the low-order comparator group 17 are converted into the high-order bit D _U and the low-order bit D _L by the encoder 18 and the encoder 19, respectively. The latch 20 holds the comparison result of the upper bits, and one of the four switch groups 12 to 15 is selected by this held data, and the lower bit is compared and converted.

The operation of this A / D converter is as shown in Figs. 2 (a) and 2 (b). Controlled by. First, the input / output of the inverter 21 of the charge balance type comparator 16 is short-circuited by φ (High level), and the reference divided voltage is input to each capacitor C. Next After the input / output of the inverter 21 of the charge balance type comparator 16 is opened by (High level), the input switch SW1 is switched to input the input voltage V _in to each capacitor C.
As a result, the comparator 16 receives the reference divided voltage and the input voltage V _in
And the comparison output is converted into a digital value D _U of the upper 2 bits via the encoder 18. Further, the comparison output is simultaneously converted into predetermined data D _SEL via the decoder 18 and stored in the latch 20 by the next clock φ. On the other hand, the charge balance comparator 17 To enter the input voltage V _in to each Kiyapashita C with short-circuiting the input and output of'll go-between inverter 22 (High level).
Next, after the input / output of the inverter 22 of the comparator 17 is opened by φ (High level), the input switch SW2 is switched to input the reference divided voltage to each capacitor. At this time, one of the four switch groups 12 to 15 is driven by the stored data D _SEL of the latch 20 and the corresponding reference divided voltage is selected. However, the selected reference divided voltage is a voltage obtained by further dividing the dividing step of the reference divided voltage applied to the comparator group 16. As a result, the comparison output of the comparator 17 is converted via the encoder 19 into the lower 2 bits of the digital value D _L.

Since the charge-balanced comparator essentially has a built-in sample-hold function, the same sample input voltage Vin is compared _in the conversion between the upper bit and the lower bit. Since the conversion result of the upper bits is held by the latch 20, one of the switch groups (12 to 15) is stably selected in the conversion of the lower bits, which is a problem in the conventional A / D converter (Fig. 1). This prevents the malfunction. The operation of the A / D converter of the present invention in the embodiment shown in FIG. 2 (a) will be described in more detail. The comparator group 16 for converting the upper bits is the reference component at the falling edge of the clock φ. Holds the piezo voltage on the capacitor and the clock that follows The input voltage V _in is compared with the held reference divided voltage during the period when is High, the encoder output according to the comparison result is latched at the rising edge of the next clock φ, and the lower bit is converted. The comparator group 17 for Holds the input voltage V _in at the falling edge of and compares the input voltage V _in held during the period when the clock φ is High with the fine reference divided voltage selected by the latched encoder output The point is the characteristic of the circuit of the embodiment. Thus, in the comparator groups 16 and 17, the comparison periods (amplification period when the comparator is regarded as a charge-balanced amplifier) are shifted from each other by a half cycle, but the former is the reference divided voltage and the latter is the input voltage. Hold on. Latch operation of latch 20 (rising edge of clock φ) and comparator group 17
Sample operation of (clock Since the input voltage related to the selection of a fine reference divided voltage based on the conversion result of the upper bit and the input voltage determining the conversion result of the lower bit are almost the same time point, the input voltage at the same time. By such an operation, the A / D converter of the present embodiment can perform the A / D conversion at the frequency of the clock φ without causing the malfunction which has been a problem in the past. Therefore, the conversion speed is the same as that of a 4-bit fully parallel type A / D converter which compares the input voltage V _in with 15 charge balance type comparators at the same time. realizable. Since the number of comparators is remarkably reduced and the circuit configuration is simple, it is suitable for an integrated circuit.

FIG. 3 is a diagram showing another embodiment of the A / D converter of the present invention. As in the case of FIG. 2, the charge-balance type comparators 16 and 17, the resistance voltage dividing circuit (R _{1 to} R ₁₆ ) of the reference voltage V _REF , the encoder 18,
19, switch groups 23 to 26, a latch 20 and a logic circuit 27. Of these, each of the switch groups 23 to 26 is composed of seven switches by adding four switches, and four comparators 17 used for conversion of the lower bits are also added to form seven comparators. The encoder 19 inputs the comparison result of these comparators 17 and outputs the 3-bit lower data D' _L . Converted data of upper 2 bits
The D _U and the lower data D _L ′ are input to the logic circuit 27 and processed, and a 4-bit digital conversion value D is obtained.

The operation of this A / D converter is a clock with opposite phases. Thus, the same control as in FIG. 2 is performed, the conversion of the upper bits and the conversion of the lower bits are alternately performed, and the digital conversion value D of the input voltage V _in is obtained. Since the range of the reference divided voltage to be compared is expanded up and down in the conversion of the lower bit, some mismatches of the conversion circuit of the upper bit and the conversion circuit of the lower bit are relieved, and the correct conversion result can be obtained. . For example, because the accuracy of the upper comparator 16 is rough, the switch group 23 should be selected correctly from the switch group 23.
Is selected. Even in this case, the input voltage V
_{If in} is equal to or lower than the terminal voltage at the P ₁ point, the comparison between the reference divided voltage selected by the switch group 23 and the input voltage V _in is validated, and a correct digital conversion value can be obtained.
In this case, since the lower order data D _L ′, which should originally be 2 bits, becomes 3 bits due to the overflow, one bit of the overflow should be carried to the upper order bit D _U. This processing can be easily realized by the logic circuit 27. On the contrary, it is assumed that the upper comparator 16 correctly selects the switch group 24 where the switch group 23 should be selected. Even in this case, if the input voltage V _in is equal to or higher than the terminal voltage at the P ₂ point, the comparison with the reference divided voltage is made effective and the correct digital conversion value can be obtained. In this case, since the lower data D' _L is displayed by 3 bits by the underflow (negative number), the upper 2 bits data by the logic circuit 27.
A digital conversion value D can be obtained by simply adding or subtracting D _U and the lower 3 bits data D ′ _L.

〔The invention's effect〕

As described above, according to the present invention, in the serial-parallel type A / D converter, it is possible to prevent mismatches in the circuit operation between the high-order bit conversion and the low-order bit conversion. A / D converter can be integrated into an integrated circuit. In addition, the circuit configuration is complete, the circuit size is small, and high-resolution high-speed A / D converters can be realized in a small area, and the power consumption is small, which is a great effect in terms of performance and economy.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a conventional serial-parallel type A / D converter, and FIGS. 2 (a) and 2 (b) are a circuit configuration example and a time chart of the A / D converter of the present invention, respectively. It is a figure. FIG. 3 shows another circuit configuration example of the A / D converter of the present invention. 10,11 …… Comparator, 12 to 15 …… Switch group, 21,22
...... Inverter, 23 to 26 …… Switch group.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eigame Imaizumi 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Mycro Computer Engineering Co., Ltd. (56) Reference JP-A-57-131123 (JP, A) JP 56-164628 (JP, A)

Claims (1)

[Claims] 1. A plurality of first divided voltages are generated by resistance-dividing a reference voltage, and each of the plurality of first divided voltages is further divided by resistance to generate a plurality of second divided voltages. A plurality of first comparators that output a comparison result by comparing the generated divided voltage generation circuit with the plurality of first divided voltages generated from the divided voltage generation circuit and a common input voltage. A first encoding circuit for encoding comparison outputs of the plurality of first comparators; and a plurality of the plurality of divided voltage generation circuits of the divided voltage generation circuit based on a comparison result of the plurality of first comparators. A selection circuit for selecting a group of second divided voltages selected from among the two divided voltages, the selected group of second divided voltages selected by the selection circuit, and the common input voltage. And a plurality of second comparators for comparing and a ratio of the plurality of second comparators. An A / D converter including a second encoding circuit for encoding an output, wherein each of the plurality of first comparators is connected to a first signal amplifier and an input terminal of the first signal amplifier. A first switch and a first capacitor, and a first input selection switch for selecting a common input voltage or a selected first divided voltage, and the first switch is turned on at a first timing. By setting the above, the potential of the input terminal of the first signal amplifier is set to a predetermined potential, and one corresponding first divided voltage of the plurality of first divided voltages is set to the first divided voltage.
The first input selection switch is connected to the capacitance side of, the first capacitance is charged, the first switch is turned off at the second timing, and the first input selection switch is switched. Is connected to the common input voltage via the first capacitor to change the potential of the input terminal of the first signal amplifier, and each of the plurality of second comparators has a second Second amplifier and second switch connected to the input terminals of the second signal amplifier, and a second input selection switch for selecting a common input voltage or a selected second divided voltage. And setting the potential of the input terminal of the second signal amplifier to a predetermined potential by turning on the second switch at the second timing.
The input selection switch is connected to the common input voltage to charge the second capacitor, the second switch is made non-conductive at the first timing, and the group of second divided voltage Of the corresponding second divided voltage is connected to the second capacitor by switching the second input selection switch to change the potential of the input terminal of the second signal amplifier. A / D converter characterized in that