JPH075704Y2 - Multi-channel A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a multi-channel A / D converter capable of simultaneously converting a plurality of analog signals into digital signals in parallel.

(Prior Art and its Problems) Conventionally, there has been a multi-channel A / D converter as shown in FIG.

This multi-channel A / D converter is available from page 112 of "Practical Electronic Circuit Handbook (3)" published by CQ Publishing Co., Ltd.
It is described on page 14.

Briefly, the counter CTR ₃ counts up with the clock signal CK ₃ so that the D / A converter DAC
_The staircase waveform is output from ₃ and input terminals V ₃₁ ... V ₃₄
The analog signals input from are compared by each comparator CO ₃₁ ... CO ₃₄ . RS flip-flop FF when it becomes equal
₃₁ ... FF ₃₄ is set, and the digital signal output by the counter CTR ₃ at that time is latched by the latch circuit LA ₃₁ ... LA ₃₄ , and converted into analog signals input to the input terminals V ₃₁ ... V ₃₄ , respectively. The corresponding digital signal is output from the output terminal D _31.
‥ output from the D _34.

However, the A / D converters described above have drawbacks such as "the counter takes a long time to count and the conversion time is slow" and "the conversion time varies depending on the input voltage and is not constant".

(Object of the Invention) The present invention has been made to eliminate the above drawbacks and to provide a multi-channel A / D converter having a fast conversion time and a constant conversion time.

(Structure of the Invention) The present invention is a reference voltage generating circuit commonly provided for each channel for sequentially outputting an analog signal corresponding to the weight of each bit of a binary digital signal, and a capacitor for holding an input analog signal. A comparator that compares the terminal voltage of the capacitor provided for each channel with the output voltage of the reference voltage generation circuit; a register consisting of multiple bits that sets each bit according to the output signal of the comparator; and the charging of the capacitor Alternatively, the multi-channel A / D converter includes a charge / discharge control circuit that controls discharge by the output voltage of the reference voltage generation circuit and the output signal of the comparator.

(Embodiment) FIG. 1 is a circuit diagram of a multi-channel A / D converter which is an embodiment of the present invention.

The operation of the multi-channel A / D converter will be described with reference to the waveform diagram of FIG. In this embodiment, the digital signal will be described as 4 bits.

In the shift register SR _11, only the first MSB is [1] (however,
[] Indicates a binary number, and [1] is sequentially shifted to the LSB side by the clock signal CK ₁ such as (2-1). When [1] is shifted to LSB, [1] is set to MSB again at an appropriate timing, and the LSB is sequentially shifted.

By inputting the output signal of SR ₁₁ as described above to the D / A converter DAC ₁ , the reference voltages V _A , V _B , V _C corresponding to each bit of the binary code signal as shown in (2-5). , V _D in sequence to form a reference voltage generation circuit VG ₁ .

The reference voltage is input to each channel CH ₁₁ , CH ₁₂ , CH ₁₃ , CH ₁₄ , and each channel CH ₁₁ ... CH ₁₄ is an input terminal.
The analog signals input to V ₁₁ , V ₁₂ , V ₁₃ , and V ₁₄ are converted to digital signals and output terminals D ₁₁ , D ₁₂ , D ₁₃ , and D
Output from _{14 as} a 4-bit digital signal.

Since the circuits of the channels CH _{11 to} CH ₁₄ perform the same operation with the same circuit configuration, only the channel CH ₁₁ will be described.

As shown in the figure (2-6), the reference voltage V _{A is} applied to the input terminal V _11.
If a lower voltage V _i is input, the analog gate G ₁₁ is temporarily turned on by the sampling pulse signal of (2-2), and the voltage V _i is _held in the capacitor C ₁₁ .

The voltage V _i is input to the amplifier A ₁ and the input terminal of the comparator CO ₁ via the buffer amplifier BA ₁₂ .

In the next clock signal, the reference voltage V _A to the input terminal of the comparator CO ₁ and amplifier A ₁ is input, for magnitude of voltage input to the comparator CO ₁ is V _A> V _i , The output signal becomes [0], and [0] is written in the LSB of the shift register SR ₁₂ at the rising edge of the pulse signal φ ₁₂ .

Is output voltage of V _i -V _A from amplifier A ₁ at the same time, passes through the analog gate G ₁₃ by a pulse signal phi _12, although the voltage V _i -V _A is held in the capacitor C _12, the shift register SR _Since the LSB of ₁₂ is [0], the output signal of the AND circuit AN ₁ becomes [0] and the analog gate G ₁₂ does not become conductive.

In (2-6), the voltage across the terminals of capacitor C ₁₁ is indicated by the solid line,
The reference voltage output from the reference voltage generation circuit VG ₁ is shown by the broken line.

Reference voltage V from the reference voltage generating circuit VG ₁ at the next clock signal
_{When B} is output, the output signal of the comparator CO ₁ becomes [1] because V _B <V _i , and the shift register SR ₁₂ outputs the pulse signal φ ₁₂
At the same time, the previously stored [0] shifts to the next higher bit, and at the same time, 1 is stored in the LSB. And circuit AN ₁
Becomes a state in which the pulse signal φ ₁₁ can pass. At the same time, the voltage V _i −V _B is output from the output terminal of the amplifier A ₁ and is held in the capacitor C ₁₂ via the analog gate G ₁₃ .

Therefore, the pulse signal φ ₁₁ is generated by keeping the analog gate G ₁₂ conductive for a certain time through the AND circuit AN ₁ .
The voltage charged in the capacitor C ₁₂ is the buffer amplifier B
A ₁₁ to the capacitor C ₁₁ via analog gate G ₁₂ V _i −V
The voltage of _B value is held.

In this embodiment, the amplifier A ₁ , the analog gate G ₁₃ ,
Capacitor C ₁₂ , buffer amplifier BA ₁₁ , analog gate G
₁₂ and the LSB portion of the shift register SR ₁₂ , and the AND circuit AN ₁ are the charge / discharge control circuit described in the scope of claims for utility model registration.

Reference voltage V from the reference voltage generating circuit VG ₁ at the next clock signal
_{When C} is output, since V _C <V _i −V _B , the output signal of the comparator CO ₁ becomes [1], and the LSB of the shift register SR ₁₂ and the bit above it are previously stored [01]. Is shifted up by 1 bit and [1] is further stored in LSB.

At the same time, the voltage of (V _i −V _B ) −V _C is output from the output terminal of the amplifier A ₁ , and the capacitor C ₁₂ is charged via the analog gate G ₁₃ .

Pulse signal phi ₁₁ is in a conductive state analog gate G ₁₁ through the AND circuit AN _1, the charging voltage of the capacitor C ₁₂ (V _i
−V _B ) −V _C is charged to capacitor C ₁₁ .

Reference voltage V from the reference voltage generating circuit VG ₁ at the next clock signal
_{When D} is output, V _D <(V _i −V _B ) −V _C , so the comparator
The output signal of CO ₁ becomes 1, and the 3 bits from the LSB of the shift register SR ₁₂ shifts the previously stored [011] to the upper position by 1 bit and at the same time further stores [1] in the LSB.

As described above, 4 stored in the shift register SR ₁₂
The bit digital signal becomes [0111] and the input terminal V
_The analog signal input to ₁₁ is converted to a digital signal and output from output terminal D ₁₁ .

The above conversion operation is repeated.

Next, another embodiment with one holding capacitor is shown in FIG. 4, and its operation will be described with reference to the waveform diagram of FIG. Similar to the description of FIG. 1, only the operation of the channel CH _{41 of} FIG. 4 will be described.

The shift register SR ₄₂ and the reference voltage generation circuit VG ₄ operate exactly the same as the shift register SR ₁₂ and the reference voltage generation circuit VG _{1 in} FIG. _1, and are respectively the pulse signal φ ₄₂ of (5-4) and ( 5-1) Clock signal CK ₄ works.

As in the case of the description of FIG. 1 above, when the voltage V _i lower than the reference voltage V _A is input to the input terminal V ₄₁ , the voltage −V _i is output from the output terminal of the inverting buffer amplifier BA _41. Is output.

By the reset pulse RE ₄ as shown in (5-3), the analog gate G ₄₃ is turned on to discharge the charge stored in the capacitor C ₄ . When a sampling pulse signal with a specific time width such as (5-2) is input in this state, the current of V _i / R ₄ flows from the resistor R ₄ to the inverting buffer amplifier BA during that time width.
Flowing in the direction of ₄₁ , the capacitor C ₄ is charged to the voltage V _i .
The resistor R ₄ , the capacitor C ₄ , and the amplifier A _{41 form} an integrating circuit.

For ease of explanation, the capacitor C ₄ is charged and discharged so that the same voltage as the absolute value of the voltage applied to the resistor R ₄ via the analog gates G ₄₁ and G ₄₂ changes due to charging and discharging. The capacitance of C ₄ , the value of resistor R ₄ , the time width of the sampling pulse, and the time width of the output pulse of the monostable multivibrator MMV ₄ are set.

The comparator CO ₄ is similar to the comparator CO ₁ in the embodiment shown in FIG.
When the input signal to the input terminal is greater than the input signal to the input terminal, the output signal is [1], and vice versa. When the LSB of the shift register SR ₄₂ set according to the comparator CO ₄ is [1], the AND circuit A
The N ₄ pulse signal phi ₄₁ passes as shown in (5-5), the sampling pulse signal SH ₄ from monostable multivibrator MMV ₄
Output the signal shown in (5-6) with the same time width as
Reference voltage generation circuit VG ₄ with analog gate G ₄₂ conducting
Is applied to the resistor R ₄ via the buffer amplifier BA ₄₂ to discharge the electric charge stored in the capacitor C ₄ corresponding to the reference voltage.

By the above operation, the voltage between the terminals of the capacitor C ₄ changes as shown by the solid line in (5-7), and a digital signal corresponding to the analog signal input to the input terminal V ₄₁ is formed in the shift register SR ₄₂ . The digital signal is output from the output terminal D ₄₁ .

And each channel CH ₄₂ , CH ₄₃ , CH ₄₄ also has input terminals V ₄₂ , V ₄₃ ,
The digital signal corresponding to the analog signal input to V ₄₄ is output from each output terminal D ₄₂ , D ₄₃ , D ₄₄ .

(Effect of the invention) As described above, according to the multi-channel A / D converter of the present invention, the conversion time is shorter and the conversion time is shorter than that of the conventional multi-channel A / D converter of the counting method. Unprecedented multi-channel A / D with the characteristic that
It is a converter.

[Brief description of drawings]

 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit diagram of FIG. 1, FIG. 3 is a circuit diagram showing a conventional example, and FIG. FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a waveform diagram showing the operation of the circuit diagram of FIG.

Claims (1)

[Scope of utility model registration request] 1. An analog signal comprising a plurality of channels capable of inputting different analog signals to respective input terminals and corresponding to the weight of each bit by the number of steps equal to the number of bits of the binary digital signal to be converted. A reference voltage generation circuit that is commonly provided for each channel that sequentially outputs, a capacitor that holds an input analog signal for each channel, and a comparison that compares the terminal voltage of the capacitor with the output voltage of the reference voltage generation circuit. And a register consisting of a plurality of bits for setting each bit in accordance with the output signal of the comparator, charging or discharging the capacitor, when the output signal of the comparator is high or low level, the data in the register While writing, to the voltage difference between the terminal voltage of the capacitor and the output voltage of the reference voltage generating circuit immediately before,
The terminal voltage of the capacitor is changed by charging or discharging, and the charging of the capacitor is performed by sequentially comparing the changed terminal voltage of the new capacitor with the next output voltage of the reference voltage generating circuit by the comparator. A multi-channel A / D converter characterized by being provided with a discharge control circuit and capable of converting an input analog signal into a digital signal for each channel.