JPS5922440A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To reduce the number of comparators and to decrease the number of times of conversion, by providing 2n sets of resistor groups connected in series between reference voltages and a comparator, etc. comparing a divided potential with an analog input signal via (2<n>-1) sets of switches. CONSTITUTION:A terminal is led out of parts dividing equally 16 set of series resistor groups into four, and three terminals are connected to the switches A1-A3. Further, a switch group F comprising three switches F1-F3 is provided and the input side of the F is connected selectively to switch groups A-E. This output is connected to input terminals 1-3 of comparators X1-X3 and other terminals 4-6 are connected to an input terminal 7 of an analog signal to be compared. Output terminals 8-10 of the comparator are connected to the input terminals (a)-(c) of an encoder 11. The output of the encoder 11 is connected to memory circuits 12, 14. A control sequence circuit 18 receives a conversion start signal STC and supplies a conversion end signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-speed A/1) converter that converts an analog signal into a digital signal.

[Technical background of the invention]

In general, there are various types of A/D converters, and examples of A/D converters that have relatively high conversion speeds include successive approximation type and parallel comparison type A/D converters.

[Problems with background technology]

When converting an analog signal to, for example, an 8-bit digital signal using a parallel comparison type A/D converter, 28-
Since 1=255 comparators are required, the chip size of this semiconductor device becomes large and the manufacturing cost increases, which is a drawback.

Furthermore, when this is performed using a successive approximation type A/D converter, eight conversions are required, resulting in a long conversion time and a disadvantage that it is not suitable for high-speed conversion.

[Purpose of the invention]

This invention was made in view of the above-mentioned drawbacks, and its purpose is to reduce the number of comparators to a large extent, reduce the number of conversions, and maintain a relatively high conversion speed.
[) provides a converter.

[Summary of Yorikiri]

The A/D converter of this invention has a group of 2n resistors connected in series between reference voltages, and a divided potential between each resistor is selected via a 2"-1 switch. 2n-A-1 comparators that compare multiple potentials and analog input signals six times, and the output content of the comparators required to repeat t comparisons until the final result is obtained. As mentioned above/
a control circuit for selecting a switch group, and a memory circuit for sequentially retaining the output contents of the comparator, n > t).
It is characterized by satisfying the condition i.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 71 is a block diagram showing the basic configuration of a 4-pittle converter. Connect 16 resistors in series and label them with the number RO"R15. Next, take out the terminals from the points where this series resistor group is divided into four equal parts, and connect these three terminals to each of the switch inputs. Connect to the switch Al-A3.Also, divide each of the four resistors into four equal parts and replace them.Take out the terminal from the common connection point of each resistor Re"Rlg, and connect each of these three One set of terminals is connected to the corresponding switch group B.
, C, I) and E switches B1 ""R3+
c,~c,l Di'D! and connects to E1 to E3. Furthermore, a switch group F consisting of three switches F1%F3 is provided, and the input side of this switch group F is selectively connected to switch groups A to E as will be described later.

This output side is connected to one input terminal 1 to 3 of three comparators X and %X3. The other input terminals 4-6 of these comparators X1-X3 are connected to the input terminal 7 of the analog signal to be compared. Next, output terminals 8 to 10f of comparators X1 to X3
: Connected to each of the input terminals (,) to (c) of the encoder 11.

The two sets of output terminals 5lS2 of this encoder 11 are connected to the input terminal 13 of the switch control circuit J2 and the memory circuit 140.
Connected to input terminal 15 in parallel. This memory circuit 14
are two sets of registers 15, 16 and an ``f-circuit 17''.
The upper 2 bits are stored in register 15.
.

The information of the lower two bits Y2+Y3 is sequentially stored in Yl and the register 16.

Further, the latch circuit 17 temporarily stores information output from these registers 15 and 16.

An output signal converted into a 4-pit digital signal is simultaneously obtained from the output terminal 1'9 of the memory circuit 14.

Finally, a control sequence circuit 18 is provided, which receives a conversion start signal STC at its input terminal 20 and supplies a control signal from one output terminal 21 to the switch control circuit 12 and the registers 15 and 16. circuit 17
is connected to supply the conversion end signal EOC.

Next, while referring to the timing chart in Figure 2,
The operation of the /D converter will be explained.

First, the series resistor group RO to R15116V is connected to a reference power source (not shown). It is assumed that a 7V analog input signal is supplied to the analog input signal terminal 7.

Sequence circuit 1 that controls conversion start signal STC
8, a control signal is supplied to registers 1s and i6, and the previously stored information content is erased. At the same time, a control signal is also supplied to switch control circuit 12, so that switch group F and switch Group A is connected. In this case, the voltage of the 16V reference voltage divided into four equal parts by the 16 resistors R6 to R1g of the same value is applied to the switch group A, so the voltage of each switch is A1 = 12V.
, A2=8V, and A3=4V.

First, in the first step (duration TI), the analog input signal and each switch A1 to A of the switch group A are input.
3 using comparators X1 to X3. That is,
The reference input terminal 1 of the comparator X1 has the potential of AI, 12V,
is applied, and A! is applied to the reference input terminal 2 of the comparator X2. The potential of 8V is further applied to the reference input terminal 3 of the comparator X3.

' potential of 4V is applied to each. At the same time,
An analog signal is applied to the other input terminal 4, 5.6 of each comparator. Here, these comparators X1 to X3 have an output level of 1# when an analog input signal higher than the reference potential is applied, and an output level of 1# when a lower analog input signal is applied. is designed to be “0#”.

As a result of the first step comparison operation with
The output signal level of each is o''.

'O#,''1#. These values are supplied to the input terminals n, b, and c of encoder 1. By performing this first step operation, the level of the analog input signal becomes equal to the reference voltage program. It is possible to make a rough judgment as to which potential level block the block corresponds to.In this example, it is judged that it corresponds to the block of resistors R7 to R4. Based on the result of this judgment, the switch is set in the next step. A switch group connected to group F is selected.

On the other hand, the encoder 11 to which the comparison output levels of the comparators X1 to X3 are supplied operates according to the truth table of Table 1.

Table 1 In this example, the ttol pp output signal from the encoder 11 is transmitted to the switch control circuit 12 and the memory circuit 14.
The data is supplied to the register 15, where it is stored as the upper two bits of the four bits of the final data. The timing of this storage is stored in the register 15 during the duration TI of the first step, and in synchronization with the falling edge instant at the end of this duration T1, the upper two Bit information data is sent to latch circuit 17 and latched. The duration of the step is here predetermined by a clock signal from a clock signal generator (not shown).

When the first step period T1 ends, the switch control circuit 12 switches and connects the switch group F to the switch group as described above.

After this instant, a second step of duration T2 begins.

The analog signal input terminals 4, 5.6 of the comparators X1 to X3 are still supplied with analog input signals at the previous signal 1 level, but the other reference potential input terminals 1, 2 and 3 are supplied with 7V each. , 6V and 5V are applied separately.

Here, if a comparison operation is performed in the same manner as in steps above, the output signals of these comparators X1 to Xs are 1" and '1", respectively.
, 1''. When these encoder input signals are processed according to the truth table shown in Table 1, a digital output signal of '11' level is obtained at the output terminal of this encoder 11. This digital signal is input to the memory circuit. The lower two bits are stored in the remaining register 16 of 14 as a signal.
Here, the switch group is not switched, but this signal is detected and the conversion end signal EOC is supplied from the control sequence circuit 18 to the latch circuit 17. This ends the second step period, which has a duration T
From the falling edge of 2, the lower 2 bits) information is sent from the output terminal Y2*Y3 of the register 16 to the latch circuit 17 and latched. Then, if necessary,
As explained above, a 7V analog input signal can be extracted as a 4-bit data signal from the circuit 17.
When A/D conversion is performed under the reference potential of '0111', 4
It can be extracted as a digital signal.

The A/D converter according to the present invention is not limited to the example described above, and various modifications can be made.

For example, in the above embodiment, three comparators were used and conversion was performed twice, but as the number of bits increases, many combinations of the number of comparators and the number of steps can be considered.

〔Effect of the invention〕

According to the A/D converter of the present invention, since the number of comparators can be reduced compared to a parallel comparison type, there is an advantage that the buffer circuit from the analog human power sensor can be saved.

Furthermore, since the number of comparators can be saved, the size of the semiconductor chip of the A/D converter can be reduced, which has the advantage of improving the integration rate. Therefore, it is possible to improve the yield of H and F, and also to reduce costs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the A/D converter according to the present invention, and FIG. 2 is a timing chart showing the operation of the converter shown in FIG. 1-3... Reference potential input terminal, 4-7... Analog signal input terminal, 11... Encoder, 12... Switching control circuit, 14... Memory circuit, 1rI5.
control sequence circuit %RO~R1g...resistance,
A-F... Switch group, STC,... Conversion start signal, EOC... Conversion end signal, X, %X,... Comparator, Y (1 to Y3... Register output terminal. Application Personal agent Patent attorney Suzue Takehiko 224- Figure 2 STC

Claims (1)

[Claims] A group of 2n resistors connected in series between the reference voltages, and the divided reference voltages between these resistors are connected to multiple potentials selected via 2n-1 switches and the analog signal to be converted. 2n -1-1 comparators that compare the signals six times, an encoder that forms part of the final converted digital signal every t conversions by the output signal trap of the comparators; A switch control circuit that selects a switch group necessary for the next conversion from the switch group according to an output signal, and a memory circuit that sequentially stores the output contents of the encoder every t conversions, n ) A) ~Φ converter characterized by satisfying the conditions of l.