JPH0724381B2 - Analog / digital converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type analog / digital converter (hereinafter abbreviated as A / D converter), and in particular, the same digital amount is converted into a plurality of analog amounts. The present invention relates to a corresponding multi-value conversion type A / D converter.

[Prior art]

Examples of conventional successive approximation type A / D converters include those described in "A / D, D / A conversion technology of microcomputer age", page 75, published by Nikkan Kogyo Shimbun.

FIG. 7 is a block diagram showing the above prior art,
(A) is a voltage comparison type, (b) is a current comparison type, (c) is a pulse waveform diagram, (d) is a detailed diagram of a voltage comparison type.

In FIG. 7, a decoder for inputting the reference power source 37
By controlling the analog converter (hereinafter abbreviated as D / A converter) 30 with the output of the successive approximation register 33, and comparing the output with the analog input 40 to be converted into a digital signal by the comparator 31, Perform A / D conversion. The basic operation of the voltage comparison type and the current comparison type is the same.

The basic operation will be described in detail below.

As shown in FIG. 7D, the successive approximation register 33 is composed of a shift register 34 and a holding register 35. Note that this example illustrates a case where an analog input is converted into a 3-bit (8-step) digital signal.

First, when the start signal is input, the MSB of the shift register 34
(Most Significant Bit, ie P _{03 in} the figure, P ₀₄
The dummy bit on the timing becomes 1 and then the holding register 35 is set by the above data of the shift register 34. Therefore, the holding register 35 is set to [100]. Note that [100] is a notation in which the left end is the MSB, and the right end is the MSB in FIG. 7 (d).
This value [100] is 4/8 of full scale range (FSR)
Corresponds to (= 1/2).

Then, the above output is given to the D / A converter 30, and the D / A converter 30
30 outputs an analog amount corresponding to the above digital input (4/8) FSR as an output V _OUT .

Next, the D / A converter 30 is connected to one input terminal of the comparator 31.
Is supplied to the other input terminal, and the other input terminal is supplied with the analog input 40 to be converted into a digital signal.

The comparator 31 compares the magnitudes of the above two inputs, and outputs a "0" signal when the analog input 40 is larger than (4/8) FSR, and outputs a "1" signal when the analog input 40 is small. This "1" signal is a holding register
It becomes the reset signal 36 of 35 and resets the MSB of the holding register 35 to “0”. That is, analog input 40 is (4 /
8) When it is larger than FSR, the content of the holding register 35 is kept as it is, and when the analog input 40 is smaller than 1/2 FSR, the MSB of the holding register 35 is reset to "0".

First, considering that the reset signal 36 is “0”, that is, the analog input 40 is larger and the content of the holding register is kept as it is, then the content of the shift register 34 is shifted. It becomes [010]. As a result, the holding register 35 is set to [110]. This value is 6 / FSR
Corresponds to 8 (= 3/4). Therefore, the analog amount corresponding to (6/8) FSR is output to the output of the D / A converter 30. Then, in the comparator 31, the analog input 40 and the above (6/8) FSR
Are compared with each other, and the “0” signal or the “1” signal is output as described above. As a result, if the analog input 40 is larger (in the case of “0” signal), then the holding register 35 [11
1) Set (corresponding to 7/8 of FSR) and compare the output of the D / A converter 30 corresponding to it with the analog input 40.

As a result, when the analog input 40 is larger (in the case of the “0” signal), the above [111] becomes a converted digital output. On the contrary, when the analog input 40 is smaller ("1" signal), the holding register 35 is reset and [110] becomes a converted digital output.

As a result of comparing the analog input 40 with the (6/8) FSR, when the analog input 40 is smaller (in the case of "1" signal), the holding register 35 is set to [101].
This value corresponds to 5/8 of FSR. And like above,
(5/8) FSR and analog 40 are compared, and as a result, when the analog input is larger (in the case of “0” signal), the above [101] becomes the converted digital output and the analog input Is smaller (in case of “1” signal), [10
0] is the converted digital output.

On the other hand, in the case of “1” signal in comparison with the first (4/8) FSR, that is, when the analog input 40 is smaller,
The holding register 35 is set to [010]. This value is the FSR
Equivalent to 2/8 (= 1/4).

Thereafter, in the same manner as described above, the value of the holding register 35 is changed to [011] according to the result of comparison between the set value and the analog input 40.
(Equivalent to 3/8 of FSR) or [011] (equivalent to 1/8 of FSR)
And outputs a digital value according to the result.

Therefore, the input analog quantity is converted into the following digital quantity.

As described above, in the successive approximation A / D converter, set the initial value of the reference voltage to the intermediate value (1 / 2FSR), and depending on the comparison result, if the analog input is higher, the reference voltage A / D conversion can be performed efficiently by shifting to the higher side and shifting the reference voltage to the lower side when the analog input is lower. In the above example, the 3-bit A /
Although it is D conversion, the same applies to conversion with a larger number of bits.

The successive approximation type as described above is suitable for high integration because it has a medium speed (conversion speed of several hundreds of μs) and a small number of comparators, and is suitable for microcomputers with a built-in A / D converter. Is also used.

By the way, in normal A / D conversion, one digital amount corresponds to one analog input amount regardless of linear conversion or non-linear conversion (logarithmic compression code, etc.). An A / D converter with multiplication function (for example, Proceedings of IEICE Spring Conference 1988, C-300, 2-2
61), one analog quantity may correspond to a plurality of digital quantities, but this is only the multiplication function incorporated in the decoding switch circuit.

However, when the A / D converter itself has characteristics corresponding to a predetermined membership function, such as an A / D converter used in a fuzzy controller, a plurality of analog quantities are combined into one digital quantity. May correspond to.

For example, as shown in FIG. 5, when it is desired to perform conversion such that the digital amount includes a convex function or a concave function with respect to the analog amount, one digital amount is converted into two analog amounts as described above. Will correspond.

As an A / D converter in the case where a plurality of analog amounts correspond to one digital amount as described above, there is, for example, an all parallel comparison type converter (flash A / D) as shown in FIG.

In the fully parallel comparison type as described above, since the magnitude of the analog amount can be immediately known, it is only necessary to make the correspondence as shown in FIG. 5 by the decoding circuit. However, the fully parallel comparison type requires 2n comparators for n-bit conversion, which requires an enormous chip area and consumes a large amount of power (for example, 100 mA or more). However, it is difficult to embed it in a microcomputer or the like.

[Problems to be Solved by the Invention]

As described above, in the normal successive approximation type, depending on the comparison result, the reference voltage is shifted to the higher side when the analog input is higher, and the lower reference voltage is used when the analog input is lower. A / D conversion can be performed efficiently by shifting to, but in the case of a polyvalent function as shown in FIG. 5, the direction of comparison, that is, the direction of changing the reference voltage is A ₁ . There is a problem that it cannot be judged because it is different from A ₂ .

Further, in the all parallel comparison type, as described above, since 2n comparators are required for n-bit conversion, there is a problem that a huge chip area is required and power consumption becomes large.

The present invention has been made in order to solve the problems of the prior art as described above, and efficiently performs conversion such that a plurality of analog amounts correspond to one digital amount, and a small size,
It is an object to provide an A / D converter that can be operated with low power consumption.

[Means for Solving the Problems]

In order to achieve the above object, the present invention is configured as described in the claims.

That is, in the present invention, when the n-valent function, that is, the n analog amounts correspond to one digital amount, n n-values corresponding to the respective parts of the n-valent function that are monovalent functions are output. Decode switch circuit of
An n number of comparators for respectively comparing the output of each decode switch circuit and the analog input are provided, and a priority comparator of the n number of comparators is determined and the signal of the priority comparator is determined. Is output, or if the judgment cannot be made, a selection / judgment logic circuit that detects the judgment of the comparator and outputs a signal that gives priority to it is provided, and the direction in which the reference value should be changed is detected and the direction is changed. It is configured to make the successive comparisons.

Example of Invention

 FIG. 1 is a diagram showing an embodiment of the present invention.

In FIG. 1, the reference voltage generating circuit 1 generates a plurality of different reference voltages 1a _{1 to} 1an. The reference voltage generation circuit 1
For example, as shown in FIG. 3, the power supply voltage V _DD
It is possible to use a circuit that divides the resistance of the resistor with a series circuit of a large number of resistors.

The first decode switch circuit 2a (details will be described later with reference to FIG. 2) and the second decode switch circuit 2b have a one-to-one relationship between the analog amount and the digital amount (one analog amount corresponds to one However, the same digital amount exists between both decoding switch circuits, and therefore one digital amount is added to two analog amounts at the outputs of the two decoding switch circuits. It has a corresponding configuration.

Reference voltage generation circuit 1 and decode switch circuit 2 described above
The a and 2b form the D / A converter 10.

The pair of comparators 3a and 3b inputs the outputs 2a 'and 2b' of the decoding switch circuits 2a and 2b, and outputs the analog input 4 to be converted into a digital signal and the outputs 2a 'and 2b'. Compare each.

Further, the selection / judgment logic circuit 11 includes the comparators 3a and 3b described above.
Of the comparator is input to determine which comparator output should be prioritized (details will be described later), and the output 12 controls the holding register 9.

Further, the holding register 9 inputs data by the shift register 8 and a control circuit (microcomputer or the like) not shown.

The output 13 of the holding register 9 becomes the digital signal of the conversion result.

A circuit that controls the timing of each unit is provided, but is not shown.

Next, the operation will be described.

First, the decode switch circuits 2a and 2b receive a plurality of reference voltages supplied from the reference voltage generation circuit 1 and select an analog amount to be a reference value for comparison.

The decode switch circuit 2a, 2b, for example, has a configuration such shown in FIG. 2, the decoding circuit 23 decodes the digital signal 13, the switch 21a ₁ through 21 in accordance with the result
By controlling ai, the reference voltage designated by the digital signal 13 is selected and output as the output 2a 'or 2b'.

The decode switch circuit 2a corresponds to the A ₁ side in FIG. 5 and the decode switch circuit 2b corresponds to the A ₂ side in FIG. It is a decoding switch circuit that is a valence function.

The reference voltages 2a 'and 2b' selected as described above are applied to the comparators 3a and 3b.

Hereinafter, the 3-bit A / D conversion will be described as an example.

First, at the beginning of the comparison, the MSB of the shift register 8 is set to "1", and the data is transferred to the holding register 9, as in the normal successive comparison. In this case, the content of the holding register 9 is [100]. Therefore, the data of the digital signal 13 becomes [100], and the decoding switch circuits 2a and 2b
Selects an analog quantity corresponding to the data [100] from the plurality of reference voltages 1a _{1 to} 1an and outputs it as 2a ′, 2b ′.
Note that [100] is (1/2) as described in the prior art.
Equivalent to FSR.

Next, the operations of the comparators 3a and 3b and the selection / judgment logic circuit 11 will be described with reference to FIG.

The left diagram of FIG. 4 (the part shown in the left half) is a diagram showing the functional relationship between the analog amount (vertical axis) and the digital amount (horizontal axis). It shows similar characteristics to. The upper half of each figure (from D-00 to the top) corresponds to the decode switch circuit 2a, and the lower half surface (from D-00 to the bottom) corresponds to the decode switch circuit 2b.

As described above, the contents of the holding register 9 are initially [10
0], the analog quantity (indicated by white circles) corresponding to the digital quantity of (1/2) FSR appears at the outputs 2a 'and 2b'. In this case, since the analog quantity is a divalent function of the digital quantity, the output is
Two of 2a 'and 2b' are output.

First, as shown in FIG. 4 (a), when the value of the analog input 4 indicated by the black circle is above the upper half white circle,
When the comparators 3a and 3b compare with 2a 'and 2b', "1" is output to the output 3a 'and "0" is output to the output 3b'.

In this case, since the comparator to be successively compared is 3a, its output 3a 'becomes "1", so that the RS flip-flop 5 is set and Q = "1", = "0". , 3
"1" of a'is output as the control signal 12. By applying the signal to the holding register 9, the normal successive approximation is thereafter performed using the comparator 3a in the direction of S _{1 in} the left diagram of FIG. 4 (a).

Next, as shown in FIG. 4 (b), when the analog input 4 indicated by a black circle is below the white circle in the lower half, the output 3a 'of the comparator 3a is "0", and the output of the comparator 3a is "0". The output 3b 'becomes "1", and the "1" of the output 3b' of the comparator 3b is output as the control signal 12.

By applying the signal to the holding register 9, the normal successive approximation is performed thereafter by using the comparator 3b in the direction of S _{2 in} the left diagram of FIG. 4 (b).

Next, as shown in FIG. 4 (c), when the analog input 4 is located between the upper half white circle and the lower half white circle,
The outputs of the comparators 3a and 3b are both "0", and neither is given priority.

However, the direction of successive approximation is the same, and the output of either comparator is output as the control signal 12. Then, when the successive approximation is advanced, there is a step in which the output of the comparator is inverted (in this case, the comparator 3b), the comparator is prioritized at that step, and the successive approximation is further advanced.

In this way, A / D conversion by successive approximation can be executed even when the analog amount is a divalent function of the digital amount.

Next, FIG. 6 is a diagram of another embodiment of the present invention, showing a configuration in the case where the analog amount is a trivalent function of the digital amount.
Although the shift register 8 and the holding register 9 are not shown in FIG. 6, this part is the same as that in FIG.

Decode switch circuits 2a, 2b, 2c and comparators 3a, 3b, 3c
Correspond to the part of the monovalent function which is a part of the trivalent function, respectively.

As in the case of FIG. 1, the selection / judgment logic circuit 11 'selects the comparator in the portion where the input analog value exists, or when the selection cannot be made as in the case of FIG. 4 (c). In that case, the successive comparison can be similarly performed by detecting the inversion.

Similarly, successive comparison can be performed in the case of an arbitrary multivalent function having three or more valences.

〔The invention's effect〕

As described above, according to the present invention, when the analog quantity is a multi-valued function of the digital quantity, the same number of independent decoding switch circuits and comparators as the valences are provided, and the outputs of the comparators are provided. Accordingly, by providing a logic circuit for selecting a comparator or detecting inversion, successive comparison can be performed even in A / D conversion in which the analog amount is a multivalued function of the digital amount. Therefore, it is possible to obtain an effect that a constrained A / D converter with a relatively small number of elements and power consumption can be realized.

[Brief description of drawings]

1 is an embodiment of the present invention, FIG. 2 is an embodiment of a decoding switch circuit, FIG. 3 is an embodiment of a reference voltage generating circuit, and FIG. 4 is a circuit operation of the present invention. FIG. 5 is a characteristic diagram and a block diagram for explaining, FIG. 5 is a characteristic example diagram of a polyvalent function, FIG. 6 is another embodiment diagram of the present invention, and FIG. 7 is a conventional successive approximation type A / D converter. FIG. 8 and FIG. 8 are examples of a conventional fully parallel comparison type A / D converter. <Description of symbols> 1 ... Reference voltage generation circuit 1a _{1 to} 1an ... Reference voltage 2a, 2b, 2c ... Decode switch circuit 3a, 3b, 3c ... Comparator 4 ... Analog to be converted into digital quantity Input 5a, 5b, 5c …… RS flip-flops 6a, 6b, 6c …… AND circuit 7 …… OR circuit 8 …… Shift register 9 …… Holding register 10 …… D / A converter 11,11 ′ …… Selection・ Judgment logic circuit 12 …… Selection / judgment output 13 …… Converted digital output

Claims (1)

[Claims] 1. A means for outputting a plurality of reference voltages, and a plurality of decode switch circuits for inputting the reference voltage and outputting an analog quantity corresponding to a part of a polyvalent function which is a monovalent function, respectively. , A plurality of comparators that respectively compare the outputs of the plurality of decoding switch circuits with the analog inputs to be converted into digital quantities, and among the plurality of comparators based on the outputs of the plurality of comparators, A selection / judgment logic circuit that judges a priority comparator and outputs the signal of the comparator, or detects an inversion of the comparator and outputs a signal that gives priority thereto, and an output of the selection / judgment logic circuit. , And one or a plurality of register circuits for outputting the digital amount of the conversion result and the signal for controlling the plurality of decode / switch circuits based on the above. Analog / digital converter and performing successive approximation type analog / digital converter corresponding to the multivalued function of the amount.