JP2880953B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to an A / D converter using a resistor string system.

[0002]

2. Description of the Related Art A / D by a conventional resistor string system
The configuration of the converter is shown in FIG. This conventional example, as shown in FIG. 4, and inputs a predetermined reference voltage V _ref from the reference voltage terminal 20, the analog voltage V _in A / D conversion inputted from the input terminal 21, output terminal 22 8-bit A / D output as 8-bit digital voltage _Vout
This is a configuration example of a converter, in which a resistor string 16 including a plurality of resistors connected in series between a reference voltage terminal 20 and a ground point, and connection of each resistor of the resistor string 16 selectively output by a control signal 106. the voltage level of the point, the analog switch 17 for outputting a comparison signal 105, the comparison result signal 107 by comparing the voltage level of the analog voltage V _in of the comparison signal 105 output from analog switch 17 In response to the input of the comparator 18 to be output and the comparison result signal 107 output from the comparator 18, the comparator 18 outputs a control signal 106 for performing switching control of the analog switch 17, and outputs an A / D converted digital voltage V and a control unit 19 that outputs _out to the outside via an output terminal 22.

[0003] In FIG. 4, in this conventional example, an analog voltage V _in input to the input terminal 21, an analog
Comparison signal 105 output from switch 17 and comparator 1
8, the levels are compared, and the comparison result signal 107 is input to the control unit 19. In response to the input of the comparison result signal 107, the analog switch 17 is switched and controlled by the control signal 106 output from the control unit 19, whereby the voltage divided by the resistor string 16 is appropriately selected and selected. This is output as a comparison signal 105 of the voltage level. Immediately after the start of the D / A conversion, the voltage level of the comparison signal 105 selectively output by the analog switch 17 by the control signal 106 output from the control unit 19 is the voltage level of _基準 of the reference voltage _Vref. It is controlled so that At this time, the control unit 19 refers to the comparison result signal 107 outputted from the comparator 18, the analog voltage V _in is input from the input terminal 21, half of the voltage of the reference voltage V _ref It is determined whether the level is higher or lower than the level, and the digital voltage V output from the output terminal 22 is determined.
The value of the most significant bit of _out is determined. That is, the value of the most significant bit, V _in> the case of V _ref / 2 is "1", in the case of V _in ≦ V _ref / 2 is "0".

[0004] Next, in the voltage level determination described above, the analog voltage V _in, in the case of higher level than half the voltage level of the reference voltage V _ref (the value of the most significant bit is "1") , The control signal 10 output from the control unit 19
6, the voltage level of the comparison signal 105 selectively output by the analog switch 17 is 3 V _ref /
4 and input to the comparator 18. Further, the voltage level determined above, the analog voltage V _in, than half the voltage level of the reference voltage V _ref in the case of low-level (the value of the most significant bit is "0") by the control signal 106 Under control, the voltage level of the comparison signal 105 selected and output by the analog switch 17 is set to V _ref / 4 and input to the comparator 18. The control unit 19 receives an input of the comparison result signal 107 in the comparator 18, when the value of the most significant bit is "1", 3/4 the voltage level of the analog voltage V _in is the reference voltage V _ref is determined whether a high level, or at low levels than, also in the case of the value of the most significant bit is "0", the 1/4 of the voltage level of the analog voltage V _in the reference voltage V _ref It is determined whether the level is higher or lower. That is, in the control unit 19, the analog voltage V
_in level is 0 to V _ref / 4, V _ref / 4 to V _ref /
_{2, V ref / 2~3V ref /} 4,3V ref / 4~V ref
Is determined, and the value of the bit next to the most significant bit of the digital voltage _Vout is determined. In this way, the values of the output of the digital voltage _Vout up to the least significant bit are sequentially determined.

[0005] FIG. 5 shows A / A in the conventional example.
From point D conversion start until the time of the end of conversion, the analog voltage V _in and the comparison signal at the input terminal 21 1
FIG. 5 is a diagram showing how the voltage level changes in FIG. 5, and the target voltage shows an ideal voltage waveform of the comparison signal 105.
FIG. 5 shows a transition of a voltage level change in an A / D converter having a 4-bit length in order to simplify the description and make it easy to understand. Immediately after the start of A / D conversion,
Analog switch 1 to determine the most significant bit
7, the voltage level of the comparison signal 105 selectively output is set to the target voltage of V _ref / 2. Then after a predetermined time has passed from the conversion starting, the voltage of the comparison signal 105 rises to a voltage level within the range of required accuracy of A / D conversion, in this state, compared to the analog voltage V _in signals 1
05 is compared in the comparator 18 to determine the value of the most significant bit (timing T _{1 in} FIG. 5). Fig In 5, compares the level of the analog voltage V _in signal 105
, The value of the most significant bit is “1”. At this timing, the target voltage is changed and the voltage of the comparison signal 105 is rapidly increased again to determine the value of the next bit. Then, after a lapse of a certain time, the voltage of the comparison signal 105 rises to a voltage level within the required accuracy range.
Voltage of the comparison signal 105 with the analog voltage V _in the comparator 18
And the second bit value is determined (timing T ₂ ). In FIG. 5, the analog voltage V
_Since the level of in is lower than the comparison voltage level of the comparison signal 105, the bit value of the second bit is “0”. Then, at this timing, the target voltage is changed to determine the value of the next bit. After a certain time, the comparison signal 105 is output from the comparison circuit 6.
Is compared comparison voltage and the voltage of the analog voltage V _in of the bit values of the third bit of the following is determined. In the example of FIG. 5, for the level of the analog voltage V _in is high than the comparison voltage level of the comparison signal 105, the bit value of the third bit is "1" (timing T _3). And
At timing T _3, 4 bit of the following, that is, the target voltage in order to determine the value of the least significant bit is changed. Then, after a certain time, the voltage of the comparison voltage and the analog voltage V _in of the comparison signal 105 in the comparison circuit 18 are compared, the bit value of the least significant bit is determined. In the example of FIG. 5, the level comparison of the analog voltage V _in signal 10
Since the level is lower than the comparison voltage level of No. 5, the bit value of the least significant bit becomes “0” (timing T ₄ ).

In the D / A converter proposed in Japanese Patent Application Laid-Open No. 62-31224, two resistor strings are used, and when performing one D / A conversion process, In the first half of the conversion, high-speed D / A is achieved by using the two resistor strings connected in parallel.
In the latter half of the conversion, only one of the resistor strings is used, and the other resistor string is separated from the power supply to realize low power consumption. Have been. When this type of D / A converter configuration is applied to an A / D converter, the A / D converter
To determine the value of one bit in the conversion, one D
/ A conversion operation is performed, whereby A /
The configuration is such that D / A conversion is performed a number of times corresponding to the number of bits in the D conversion process, and all bits are determined.

[0007]

The above-described conventional A / D
In the converter, in order to shorten the time required for the A / D conversion and increase the conversion speed, the voltage of the comparison signal which is switched and selected by the analog switch and input to the comparator is set to the specified voltage ± 1 / It is necessary to reduce the time required until the voltage falls within the voltage level corresponding to the conversion accuracy corresponding to 2 bits. Since this required time is affected by the resistance value of the resistor string and the value of the wiring capacitance, in order to reduce the time, the resistance value of the resistor constituting the resistor string is set to a lower value, and the wiring capacitance is reduced. Although reduction is required, lowering the resistance value of the resistor string has a disadvantage in that more current flows into the resistor string, resulting in an increase in power consumption.

On the other hand, in order to suppress an increase in power consumption,
When the resistance value of the resistor string is increased, the voltage level of the comparison result signal input to the comparator becomes the specified voltage ±
There is a drawback that the time required to reach within a voltage level corresponding to 1/2 bit is extended and the conversion speed of A / D conversion is reduced.

Regarding the application of the D / A converter proposed in the above-mentioned JP-A-62-31224,
If the change in the target voltage is large in the first half of the / D conversion, it is necessary to set the timing of switching the analog switch during the determination of one bit. There is a disadvantage that the configuration of the control circuit is complicated and is not suitable for practical use. In the latter half of the A / D conversion, if the change in the target voltage is small, there is a margin for the voltage of the comparison signal to rise to a voltage level within the required accuracy range. -There is a disadvantage that power consumption increases by switching the switch, and the effect of reducing power consumption cannot be obtained.

[0010]

An A / D converter according to the present invention is an A / D converter for converting an analog voltage into a digital signal of a plurality of bits. The A / D converter is formed by a plurality of resistors connected in series. A first resistor string that generates a divided voltage value of a predetermined reference voltage at a connection point of the resistors, and a switching control performed by a predetermined first control signal to change a divided voltage value in the first resistor string. A first analog switch for arbitrarily selecting and outputting a second resistor formed by a plurality of resistors connected in series and generating a divided voltage value of a predetermined reference voltage at a connection point of the plurality of resistors; The second resistor string is connected between a low-potential end of the second resistor string and a ground point, and is controlled to open and close by a predetermined second control signal, so that the second resistor string has a low-potential end. A second analog switch that arbitrarily “connects” or “disconnects” the connection between the second analog switch and the ground, and the second control signal in a state where the second analog switch is “connected”. A third analog switch that is controlled to switch and arbitrarily selects a divided voltage value in the second resistor string and transmits the divided voltage value to a predetermined voltage dividing point in the first resistor string; A comparator for comparing a level with a level of a comparison voltage of a comparison signal selected and output from the first analog switch; and receiving the first and second signals when receiving a comparison result signal output from the comparator. A control unit that generates and outputs a second control signal, and that determines and outputs each bit value of a digital signal corresponding to the analog voltage. Note that the first resistor string is formed by 2 ^x resistors connected in series when the number of A / D conversion bits is x, and the second resistor string has a high speed A / D conversion bit number. In the case of y, it may be formed by 2 ^y resistors connected in series.

The control unit sequentially latches a shift register in which only the bit value of the most significant bit is set at the start of A / D conversion and a bit value sequentially converted and output in the A / D conversion process. A first OR circuit for performing a logical sum of an output value of the shift register and an output value of the result register, and outputting the result as the first control signal; and an output of the result register. A value and a value of a first control signal output from the first OR circuit are input, and one of the values is selected through a selection control action depending on a level value of the comparison result signal, A data selector that outputs the result to the result register, and a second OR circuit that obtains a logical sum of an output value of the shift register and outputs the result as the second control signal,
At the end of the A / D conversion, a digital signal of the A / D conversion result latched in the result register may be output, and the level value of the comparison result signal is “1”.
In the case of the level, the output value of the first OR circuit is selected by the data selector and latched in the result register, and the bit value of the corresponding digital signal is "1".
When the level value of the comparison result signal is “0” level, the output value of the result register is selected by the data selector and latched by the result register, and the corresponding digital signal is output. The bit value may be determined as “0”.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment receives a predetermined reference voltage V _ref from the reference voltage terminal 8, the analog voltage V _in is input from the input terminal 9 converts A / D,
This is an example of a configuration of an 8-bit A / D converter that outputs an 8-bit digital voltage _Vout from an output terminal 10, and includes an auxiliary resistor string 1 connected in series between a reference voltage terminal 8 and a ground point. The analog switch 2 controlled to be opened and closed by the control signal 102, the resistor string 3 connected between the reference voltage terminal 8 and the ground, and the voltage level at the connection point of each resistor of the auxiliary resistor string 1 1
02, the analog switch 4 for selectively outputting the signal to the corresponding resistor connection point of the resistor string 3 and the voltage level of the connection point of each resistor of the resistor string 3 by the control signal 1
03, the analog switch 5 selectively outputting the comparison signal 101 and outputting the comparison signal 101, and the voltage level and analog voltage V of the comparison signal 101 output from the analog switch 5.
_The comparator 6 outputs a comparison result signal 104 output from the comparator 6 by comparing with the voltage level of the control signal 102 and the control signal 102 for the analog switch 4 and the analog switch. And a control unit 7 that outputs a control signal 103 for the A / D converter 5 and outputs an A / D converted digital voltage _Vout .

FIG. 2 is a block diagram showing a configuration of the control unit 7 according to an embodiment. The output value of the result register 12 or the OR circuit 1 corresponds to the input of the comparison result signal 104.
4. Select one of the output signals 103 from
A data selector 11 for outputting to the data register 12, a result register 12, a shift register 13, and OR circuits 14 and 15. FIG. 3 shows, as a specific example of the present embodiment, the analog voltage at the input terminal 9 from the start of A / D conversion to the end of conversion in the case of an 8-bit A / D converter. FIG. 6 is a diagram showing transition of changes in the voltage level of Vin and the comparison signal 101, and the target voltage indicates an ideal voltage waveform of the comparison signal 101, as in the case of FIG. 5 described above. In FIG. 1, the comparison signal 101 is obtained by dividing the reference voltage Vref by a plurality of voltage output levels generated by dividing the reference voltage Vref by the auxiliary resistor string 1 and the resistor string 3,
It is output as a signal of the voltage level selected and output by the analog switch 4 and the analog switch 5.
The number of resistors constituting the resistor string 3 is 2 ^x (x
Is the number of conversion bits), and the number of resistors constituting the auxiliary resistance string 1 is 2 ^y (y is the number of bits for performing high-speed conversion).

Next, referring to FIGS. 1, 2 and 3,
The operation of the present embodiment will be described. Immediately after the start of A / D conversion, the control unit 7 shown in FIG. 2 sets a value in which only the most significant bit is set in the shift register 13 to determine the most significant bit. All the values of 12 are cleared. In such a state setting, the shift register 13 and the result register 12
Is ORed by the OR circuit 14, the output of the OR is output as the control signal 103 and input to the analog switch 5, and at the same time, the value of the shift register 13 Via control signal 102
And input to the analog switches 2 and 4. Through the control action of the control signal 102, the analog switches 2 and 4 are brought into the "contact" state, and the analog switch 5 is controlled to be switched by the control signal 103. In this state, the comparison signal 1 is output via the resistor string 3 and the analog switch 5 with the voltage level set to the level of V _ref / 2.
01 is input to the negative input terminal of the comparator 6. In the comparator 6, the level of V _ref / 2 and the input terminal 9
Level of the analog voltage V _in that is input through the are compared, when the V _in> V _ref / 2 is input to the control unit 7 is outputted by the comparison result signal 104 is "1" level. The control unit 7 shown in FIG. 2 receives the comparison result signal 104 at the “1” level and receives the output of the OR circuit 14 by the data selector 11, that is, the control signal 103.
Is selected and latched by the result register 12, the value of the most significant bit of the A / D converted analog voltage V _in is "1"
Is determined as On the other hand, when V _in <V _ref / 2, the comparison result signal 104 is output at the “0” level and input to the control unit 7. In this case, the output of the result register 12 by the data selector 11 is selected and latched in the result register 12, the analog voltage V _in
The value of the most significant bit after A / D conversion is determined as "0". In this way, the value of the most significant bits after A / D conversion of the analog voltage V _in is determined to be "1" or "0". Next, the shift register 13 is shifted by one bit to the right side. In this state, the voltage level of the comparison signal 101 switched and output from the analog switch 5 is 3V _ref / when the value of the most significant bit is "1". When the value of the most significant bit is "0", it is input to the comparator 6 at the level of _Vref / 4. At this time, the analog switches 2 and 4 are in the “closed” state, and are controlled by the control signal 103 output from the OR circuit 14 included in the control unit 7, so that the circuit switching operation by the analog switch 5 is performed. This is performed at a high speed, whereby the voltage level of the output comparison signal 101 changes at a high speed.

Next, in the comparator 6, the voltage level of the comparison signal 101 is 3V _ref / 4 or V _ref / 4.
When the level of the analog voltage V _in that is input via the input terminal 9 are compared, V _in> 3V _ref / 4 or V _in> V
_{At ref} / 4, the comparison result signal 104 is output at the “1” level and input to the control unit 7. In the control unit 7 shown in FIG. 2, upon receiving the above-mentioned "1" level comparison result signal 104, the control signal 103 output from the OR circuit 14 is selected by the data selector 11, and the result register 12 And the analog voltage V
bit value of the second bit after the A / D conversion _in is determined as "1". In addition, V _in <3V _ref / 4 or V _in <
At the time of V _ref / 4, the comparison result signal 104 is output at “0” level and input to the control unit 7. In this case, the output of the result register 12 is selected by the data selector 11 and latched by the result register 12,
Bit value of the second bit after the A / D conversion of the analog voltage V _in is determined as "0". Thus, the bit value of the second bit after the A / D conversion of the analog voltage V _in is determined to be "1" or "0". In this manner, sequentially, A / D conversion processing is completed is determined until the value of the least significant bit of the A / D converted analog voltage V _in.

The OR circuit 15 in the control section 7 receives a signal output from the shift register 13 and performs a logical OR operation on the signal, A / D converts the data and determines 8-bit data to be output. At this time, the control signal 102 is output at the “1” level while the value of the first five bits of the 8-bit data is determined,
While the bit is determined, the control signal 102 is output at the “0” level. By this control signal 102, the analog switches 2 and 4 are in the "closed" state while the value of the first 5 bits of the 8-bit data is determined, and while the 3 bits of the second half are determined. Is in the "disconnected" state. That is, in the present invention, it is possible to appropriately select and switch the resistor string in the A / D conversion process.
A / D conversion processing can be speeded up,
The current consumed by the resistor string can be suppressed, and the power consumption can be reduced.

Next, with reference to FIG showing changes in the level change of the comparison voltage of the analog voltage V _in and the comparison signal 101 of FIG. 3 will be described with cast sock operation of this embodiment.
FIG. 3 shows a 4-bit A / D as a specific example of the present embodiment for the sake of simplicity of explanation.
The transition of the voltage level change in the converter is shown.
First, immediately after the start of A / D conversion, the target voltage is set to V _ref / 2 to determine the most significant bit. At this time, the analog switches 2 and 4 are set to “contact”,
The level of the comparison signal 101 output from the analog switch 5 is rapidly increased. Then after a predetermined time has passed from the conversion starting, the voltage of the comparison signal 101 rises to a voltage level within the range of required accuracy of A / D conversion, in this state, the voltage of the comparison signal 101 with the analog voltage V _in the comparator 6 and the value of the most significant bit is determined (timing T ₁ ). In Figure 3, for the level of the analog voltage V _in is high than the voltage level of the comparison signal 101, the value of the most significant bit is "1".
At this timing, in order to determine the value of the next bit, the target voltage is changed and the voltage of the comparison signal 101 is rapidly increased again. Then, after a certain period of time,
Voltage of the comparator signal 101 rises to a voltage level within the range of required accuracy, in this state, the bit value of the second bit is compared in voltage comparator 6 of the comparison signal 101 with the analog voltage V _in is determined (Timing T ₂ ). FIG.
, The level of the analog voltage V _in is
Is lower than the comparison voltage level, the bit value of the second bit is “0”. Then, at this timing, the target voltage is changed to determine the value of the next bit. In the example of FIG. 3, since the difference between the current target voltage value and the changed target voltage value is small at this time, the analog voltage is set to fall within the required accuracy range after a certain time. It is not necessary to keep the switches 2 and 4 in the “closed” state, so that the analog switches 2 and 4 are set to the “off” state at this timing. As a result, in the conventional A / D converter, there is no means for changing the resistance value of the resistor string 16 (see FIG. 4), so that the comparison signal 105 (shown by a thin line in FIG. 3) is not provided. In the present embodiment, the comparison voltage drops more gradually than the voltage of the comparison signal 105, in contrast to the comparison voltage that drops sharply. Then, after a certain time, is compared the voltage of the reference voltage and the analog voltage V _in of the comparison signal 101 in the comparison circuit 6, the bit value of the third bit of the following is determined. In the example of FIG. 3, for the level of the analog voltage V _in is high than the comparison voltage level of the comparison signal 101, the bit value of the third bit is "1" (timing T ₃ in FIG. 3) . And this timing T
_{At 3} , the target voltage is changed to determine the value of the next fourth bit, the least significant bit. In this case, since the analog switch 2 and 4 are set to the state of "OFF", the comparison voltage of the comparison signal 101 for the same reason as the case of the timing T ₃ after the foregoing, conventional A / D It rises more slowly than the comparison voltage of the comparison signal 105 (indicated by a thin line in FIG. 3) in the converter. Then, after a certain time, the voltage of the comparison voltage and the analog voltage V _in of the comparison signal 101 in the comparison circuit 6 are compared, the bit value of the least significant bit is determined. In the example of FIG. 3, the level comparison signal of the analog voltage V _in 101
Is lower than the comparison voltage level, the bit value of the least significant bit becomes “0” (at timing T in FIG. 3).
₄ ).

As described above, the first A / D conversion processing is performed. Although FIG. 3 referred to in the above description shows an operation example in the case of an A / D converter having a 4-bit length for simplification of the description as described above, it goes without saying that Also, in the case of an A / D converter having another bit length, the A / D conversion operation is performed in the same manner as in this case.
Although there is a change depending on the circuit configuration, the number of bits y when performing A / D conversion using the resistor string 3 and the auxiliary resistor string 1 and A / D conversion is performed using only the resistor string 3. And the ratio between the resistance value of the resistor string 3 and the resistance value of the auxiliary resistor string is 1: 1 to 1: 2, the power consumption and the conversion. It is advantageous in both aspects of speed.

[0020]

As described above, according to the present invention, by providing an auxiliary resistor string in addition to a main resistor string, the auxiliary resistor string is appropriately switched during the operation of A / D conversion processing. Immediately after the start of the conversion process, the resistance value of the resistor string is reduced in accordance with the internal signal having a large amplitude level, and the resistance value of the resistor string is reduced in accordance with the internal signal in which the amplitude level decreases as the conversion process proceeds. Increasing the resistance value has the effect of reducing unnecessary power consumption and reducing power consumption.

Further, under the same power consumption condition, the operating resistance value of the resistor string can be selected to be a small value, so that there is an effect that the A / D conversion processing speed is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of a control unit in the embodiment.

FIG. 3 is a diagram showing a voltage transition in an A / D conversion process in the embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a diagram showing a voltage transition in an A / D conversion process in the conventional example.

[Explanation of symbols]

1 Auxiliary resistor string 2, 4, 5, 17 Analog switch 3, 16 Resistor string 6, 18 Comparator 7, 19 Control unit 8, 20 Reference voltage terminal 9, 21 Input terminal 10, 22 Output terminal 11, 23 Data / selector 12, 24 result register 13, 25 shift registers 14,15,26 OR circuit 101 and 105 compare the signal 102,103,106 control signal 104 and 107 comparison result signal V _ref reference voltage V _in analog voltage V _out digital voltage

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/38 H03M 1/14

Claims (4)

(57) [Claims] 1. An A / D converter for converting an analog voltage into a digital signal of a plurality of bits, comprising: a plurality of resistors connected in series; a divided voltage of a predetermined reference voltage at a connection point of the plurality of resistors. A first resistor string for generating a value, a first analog switch that is switched and controlled by a predetermined first control signal and arbitrarily selects and outputs a divided voltage value in the first resistor string. A second resistor string formed by a plurality of resistors connected in series and generating a divided voltage value of a predetermined reference voltage at a connection point of the plurality of resistors; a second resistor string on a low potential side of the second resistor string; It is connected between the terminal and the ground point, and is controlled to open and close by a predetermined second control signal to arbitrarily “connect” the connection between the low potential side terminal of the second resistor string and the ground point. Or a second analog switch to be turned off, and a switching control by the second control signal in a state where the second analog switch is in a “closed” state. A third analog switch for arbitrarily selecting a voltage value and transmitting the voltage value to a predetermined voltage dividing point in the first resistor string; a level of the analog voltage; and a selected output from the first analog switch. A comparator for comparing a level of a comparison voltage of a comparison signal to be inputted with a comparison result signal output from the comparator, and receiving a first control signal and a second analyzer at the start of conversion.
Set the log switch to "close" and complete the conversion of the specified bit.
A control unit that generates and outputs a second control signal for controlling to “ turn off ” at the timing set, and that determines and outputs each bit value of a digital signal corresponding to the analog voltage. A / D characterized by being constituted
converter. 2. The method according to claim 1, wherein the first resistor string is formed by 2 ^x resistors connected in series when the number of A / D conversion bits is x, and the second resistor string includes a high-speed A / D converter.
2. The A / D converter according to claim 1, wherein the A / D converter is formed by 2 ^y resistors connected in series when the number of D conversion bits is y. 3. A shift register in which only a bit value of a most significant bit is set at the start of A / D conversion, and a control unit sequentially latches bit values sequentially converted and output in an A / D conversion process. A result register that stores and holds the data; a first OR circuit that calculates a logical sum of an output value of the shift register and an output value of the result register and outputs the result as the first control signal; and an output of the result register. A value and a value of a first control signal output from the first OR circuit are input, and one of the values is selected through a selection control action depending on a level value of the comparison result signal, A / D converter comprising: a data selector that outputs to the result register; and a second OR circuit that performs a logical sum of output values of the shift register and outputs the result as the second control signal. End To the results claim 1 or claim 2 A / D converter, wherein the output digital signal of the A / D conversion result is latched in the register. 4. When the level value of the comparison result signal is “1”, the output value of the first OR circuit is selected by the data selector, latched in a result register, and the corresponding digital signal is output. When the bit value of the signal is determined to be “1” and the level value of the comparison result signal is “0” level, the output value of the result register is selected by the data selector and stored in the result register. 4. The A / D transformer according to claim 3, wherein the bit value of the latched digital signal is determined as "0".