JPS62245722A - Serial/parallel type analog/digital converter - Google Patents

Abstract

PURPOSE:To eliminate the transient fluctuation of a reference voltage attended with the swiching of a switch by controlling the switch for reference voltage selection at low-order bit comparison by the precharge system so as to stabilize the switch operation. CONSTITUTION:When the output of EOR circuits 75-78 is decided by the com parison of high-order 2-bit, a clock phi is changed and an NMOS switch 10 is turned off. Simultaneously, one input clock, the inverse of phi of NAND circuits 31-34 is changed and only the NAND circuit inputting logical '1' of the EOR circuits 75-78 outputs a low level. Thus, only a PMOS switch 20 receiving a low level at its gate is in switch operation by the output of the NAND circuits 31-34 to connect one of the control line 30 and a power supply VDD. Thus, one NMOS switch group is turned on surely by the clock, the inverse of phi. Thus, large fluctuation of the reference voltage due to transient operation of switch groups 121'-124' is prevented and the comparison speed reduction due to the reference voltage fluctuation is avoided.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a series-parallel type AID converter, and particularly to a series-parallel type A/D converter suitable for reducing power consumption. [Prior Art] In order to reduce the power consumption of a parallel type A/1) converter, a series/parallel type A/D converter was devised in Japanese Patent Laid-Open No. 56-23026.
As described in , in the case of an N-bit series-parallel A/D converter, 2N voltage dividing resistors connected in series are divided into m voltage dividing resistor groups to obtain the reference voltage. Obtain the comparison result of the high level bit from the reference voltage and input voltage obtained, and select one of the m voltage dividing resistor groups from the obtained comparison result.

[7] Obtain the J, I, Q" voltages and compare the lower (J-j) bits from the obtained base 1" x q voltage and the input +2 voltage to 1! ) It's a bastard. here. 2~〉m. [Problem to be solved by the invention] Figure 3 is 4 bits (N = 4, m = 4)
This figure shows L known examples of arrays when serial-parallel type A/D converters are integrated into semiconductor circuits in the case of . This series-parallel Δ/D converter converts the reference voltage 1 to 16 (=
21) Reference voltage divider circuit 100 and first voltage comparator 5 which are further divided into 4 (m=1) voltage divider resistance groups
1 to 53, first position detection FOR circuits 75 to 78 which receive the comparison result from the first voltage comparator as input, and first encoding port "1l11 which receives one output of the FOR circuit as input.
．． o, the other output of the FOR circuit is used as a control signal, and a group of switches 12] to 12 are controlled to be turned on or off by the control signal.
4. A second voltage comparator 61-63, which has one reference input as the 1N quasi-voltage selected by one of the switch groups 121-124. Second position detection FOR circuits 81 to 84 that use the comparison result of the second voltage comparator as manual power. and a second encoding circuit 120 whose input is the output of the second FOR circuit. The voltage comparators 51 to 53 of the series/parallel type A/D converter 1 compare the input voltage with the upper 2 bits, and receive the result of the upper 2 bits as the base 1 of the lower 2 bits. ! Select the voltage and compare the lower two bits. FIG. 2 shows the A/r) conversion characteristics of this converter. The solid line is the A/D conversion characteristic of the upper two bits, and the broken line is the A/D conversion characteristic of the lower two bits. For example, if a digital value of 01 is obtained as a comparison result using the upper 2 bits, the comparison using the lower 2 bits is performed within the range indicated by A. Here, when selecting the reference voltage of the lower bit, the switch groups 121 to 124 receive the logic outputs of the FOR circuits 75 to 78, so when the upper comparison changes, that is, the switch group 121
When the control signals 124 to 124 are changed, two or more switch groups are turned on at the same time, and there is a risk that the reference voltage at the time of comparison of the lower two bits may be changed. Therefore, the comparison of the lower 2 bits is performed by 1 of the switch groups 121 to 124.
After the J&'Q voltage of the lower two bits has changed from '7J switching, a comparison must be made, and often the A/D
This was an obstacle to increasing the conversion speed. An object of the present invention is to provide a series-to-parallel ratio A/I converter that is suitable for high-speed operation and has a small circuit scale.
It is an object of the present invention to provide a series-parallel type A/D converter that suppresses reference voltage fluctuations during comparison and improves high-speed performance. [Means for Solving the Problems] In order to achieve the above object, the present invention stabilizes the switch operation by controlling the switch for selecting the basic character when comparing the lower bits using a precharge method. Transient change in reference voltage due to opening/closing! ! ! IJ was removed. [Function] That is, in a series-parallel type AID converter, the control signal line of the reference voltage signal switch for lower bit comparison is charged or discharged in advance, the reference voltage selection switch is set to the OFF state, and the lower bit comparison operation selects the control signal line. Discharge or charge so that only the reference voltage selection switch to be used is in the on state. This makes it possible to suppress reference voltage fluctuations due to short-circuiting of the reference voltage voltage divider circuit through the jA quasi-voltage selection switch during transient operation, and enables high-speed and reliable comparison. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIG. The symbols in the figure that are the same as those in Figure 3 have been unified. In FIG. 2, characteristics are given to the reference voltage selection switch group at the time of lower bit comparison shown in the conventional example of FIG. 3. The switch groups 121' to 124' shown here are an NMOS switch 10 and an NMOS switch 10 controlled by a clock φ.
It consists of NMOS switches 11 to 13 whose drain side is the gate control line 30, and the NMOS switches 11 to 13
The source terminal is connected between each voltage dividing resistor R, and the drain terminal is connected to the reference voltage input side of the second voltage comparators 81 to 84. Further, the control line 30 is also connected to the drain end of the MOS switch 20. )'Mt) The source end of the S switch 20 is connected to the power supply Vno,
The first position detection circuit 75-7 is connected to the gate input.
A N A N 11 circuit using the output of 8 and the clock 7; connected to the outputs of 31 to 34. Now, when the first voltage comparators 51 to 54 compare the upper two bits, the control lines 30 of the switch groups 121' to 124' are connected to the ground power supply through the NMOS switch 10 in advance by the clock φ. The first voltage comparators 51 to 54 are connected to a reference voltage divider circuit 100.
4 voltage dividing resistor groups Roi-Ran, I<(S~R
A comparison is made between the reference pressures v1 to v3 divided by os, Roo-Rtz+Rta to Rte and the input voltage. The outputs of the voltage comparators 51 to 54 show logic "0" if the input voltage is greater than the voltage, and logic "1" if the input voltage is smaller than the voltage.The first position detection EOR circuits 75 to 78 The outputs of the voltage comparators 51 to 54 detect the boundary between logic "0"l and #ljj, and only the circuit corresponding to the boundary outputs "1", and the others output "O". First encoding circuit 110 inputs the outputs of the FOR circuits 75 to 78 and outputs a digital code 3 corresponding to the boundary detected by the EOR circuits 75 to 78.The above is the comparison operation of the upper two bits.On the other hand, the NANO circuits 31 to 78 34
The output of
) level is fixed. Therefore, the PMOS of switch groups 121' to 124'
Switch 20 is off. Now, when the outputs of the FOR circuits 75 to 78 are determined by the above-mentioned comparison operation of the upper two bits, the clock φ changes and the NMOS switch 1
0 is off. At the same time, the input clock φ of one of the NANI) circuits 31 to 34 changes, and the F, OR circuit 75
~78 logic 141 Only the NANOH path that takes tT as an input outputs low. This selects a group of voltage dividing resistors whose input voltage divides the reference voltage. Therefore, the output of NANOH paths 31 to 34 is T,
Only the PMOS switch 20 which uses gate power as ow performs a switching operation, and connects one end of the control line 30 and the power supply VDn. Since the control line 30 is the gate input of the NMOS switches 11 to 13, the control line 30 is connected to the itt source v.
When connected to I)r), the NMOS switches 11 to 13 are turned on, and the reference voltage input terminals of the second voltage comparators 61 to 63 are connected between the voltage dividing resistor R. Voltage comparators 61-6
; 3 compares the input voltage with the reference voltage V a ” V b appearing in the voltage dividing resistor group divided into four, and similarly to the comparison of the upper two bits, the second position detection FOR circuit 8
1 to 84, and the lower two bits 4 are obtained by the second encoding circuit 120. The 6th order comparison operation that yields a 4-bit digital output is performed using the clock φ as described above.
The process starts after the S switch 10 is turned on and the PMOS switch 20 is turned off. In FIG. 1, PMOS switches or CMOS switches may be used instead of the NMOS switches 11 to 1:3. At this time, the NMOS switch 10 is PAO8 or CMO8.
, l) The OS switch 20 is an NHO2 or CMOS switch, and the clock φ may be selected as appropriate. As described above, according to the present invention, when selecting the reference voltage in the lower bit comparison operation, the voltage selection switch NM that is reliably turned off in advance by the clock φ and the voltage selection switch NM
For the OS switch group 121' to 124', the clock T
This allows one NMOS switch group to be reliably turned on. For this reason, switch groups 121' to 12
The base I'F! due to the transient operation of 4'! In addition to preventing large fluctuations in voltage, it is also possible to prevent reduction in comparison speed due to fluctuations in the reference voltage. Figure 4 shows a PMOS switch 20' in place of the NANO circuits 31 to 34 shown in Figure 1.
This is one of the embodiments in which the control of the MOS switch 20' is performed by the clock φ'. As a result, one of the outputs of the FOR circuits 75 to 78 can be connected directly to the NMOS
It can be input to the switch 20 and also controlled by the first
The circuit will be similar to the one shown in the figure, and the circuit will be simple. FIG. 5 shows another embodiment of the serial/parallel type A/D converter of the present invention. The switch group for selecting the reference voltage in the comparison operation of the lower bits is designated as 125 to 128 in the figure, and the reference voltage selection range in the comparison operation of the lower bits is expanded. Assume now that the position detection circuit 77 is selected in the upper bit comparison operation. At this time, the base voltage selection switch selected when clock 7 is High is 1B in switch groups 127, 11 to 13, 14, 18, and 126.
, 17,128 switches have 15 NMOS switches. Therefore, in the Δ/D conversion characteristic shown in Fig. 6, B
The comparison range in the lower bit comparison operation is expanded, and the lower bit comparison becomes more accurate. here,
In FIG. 5, there is no comparison between overflow and underflow, so the position detection FOR logic circuit 8o contains NAN.
I) A FOR circuit with a selection switch controlled by the outputs of circuits 31-34 is required. However, by increasing the number of resistors in the reference voltage divider circuit 100 and widening the reference voltage range, it is possible to reduce the number of 80 selection switches. In addition, as in FIG. 3, the NMOS switches 11 to ]8
It is also possible to use PMO8 or CMOS switch, and in this case, as in FIG. 3, NMOS switch 10 can be PMO5 or CMO3% PMOS switch 20 can be NHO
2 or 0MO8, and clocks φ and 7 may be appropriately selected. [Effects of the Invention] As described above, according to the present invention, in a series/parallel type A/1 converter, the control signal line of the reference voltage selection switch in the lower bit comparison is rearranged and charged or discharged before the reference voltage is set. The voltage selection switch is set to the off state, and discharge or charge is performed so that only the reference voltage selection switch to be selected in the lower bit comparison operation is turned on. This makes it possible to suppress reference voltage fluctuations due to short-circuits in the reference voltage divider circuit through the switch during transient operation of the reference voltage selection switch, and enables high-speed and reliable comparison. /D conversion base can be provided, which is highly effective in greatly improving performance.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a series-parallel type A/D converter of the present invention, Fig.
The figure shows the A/D conversion characteristics of a series-parallel A/D converter.
FIG. 3 is a diagram showing the configuration of a conventional series-parallel type A/D converter,
FIG. 4 is a diagram showing one embodiment in which the lower bit selection of FIG. 3 is changed, and FIG. 5 is a diagram showing one embodiment of the present invention.
FIG. 6 is a diagram showing A/D conversion characteristics of the series/parallel type A/D converter of FIG. 4. 1... Reference voltage input terminal, 2... Input signal input terminal, 3... Upper 2 bits output, 4... Lower 2 bits output, Ro1 to Rts... Voltage dividing resistor, 10 to 18.・・・
NMOS switch, 20.20'...PMOS switch, 30...control signal line, 31-34...NAND
Circuit, 51-53. 61-68...Voltage comparator, 75
~78.81~84...Position detection FOR circuit, 80.
・Position detection FOR logic circuit, 100 ・iA quasi-voltage division! ! path, 110, 120° 120'... encoding circuit, 121-124, 12]'-124', 12f;-1
28...Switch group. As soon as 4 mouths

Claims (1)

[Claims] Voltage dividing means for producing 1, 2^N reference signals are serially divided into M sets, and the first
Determine the magnitude relationship between the reference signal and the input signal (M-1
) first comparators and M whose input is the output of the comparator.
A first A/D converter is made up of a first section detection circuit and a first encoding circuit that receives the output of the section detection circuit as an input. (2^N/M-1) second reference signals generated from M) dividing means are (2^N/M-1)
N/M-1) of the first switches, and the control line that controls the switches becomes one input of the second switch, and the second switch is connected to the first control line. Opening/closing is controlled by a signal, and the other end is connected to the first power source, the control line serves as one input of a third switch, and the other end of the third switch is connected to the second power source. M sets of switch groups consisting of the first, second, and third switches are provided, and the third switch constituting the M switch groups is controlled according to the M whose inputs are the output of the first section detection circuit and the second control signal.
The other input terminal of the (2^N/M-1) first switches constituting the M switch groups is common to each group, and each N/M-1) second reference signals are input to second comparators, and the second comparators determine the magnitude relationship between the second reference signals and the analog input signal, and 2^N/M-1) second section detection circuits, and a second encoding circuit whose input is the output of the second detection circuits, forming a second A/D converter; The first A/
A D converter performs a first A/D conversion, and the M control lines are charged to the first power supply by the first control signal, and the (2^
After closing the N/M-1) first switches and closing the M third switches using the second control signal that is one input of the M logic circuits, The M second switches are closed, and the first A/D conversion determines in which level of the M switch groups the second reference signal is located in the M logic circuits. detecting whether the M
The third switch of the group of switches is opened, and the second reference signal is passed through the corresponding (2^N/M-1) first switches to the second (2^N/M- 1) A series/parallel type A/D converter which is inputted as a reference voltage signal of two comparators and performs a second A/D conversion.