JPH1117545A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the resolution of a D/A converter without largely increasing the circuit scale. SOLUTION: This current summing type D/A converter that is composed of lots of high-order current cells 11 uniformly weighted to generate the same constant current and low-order current cells 12 weighted to generate a current of one over 2's power with respect to the current of the high-order current cells 11 is provided with a constant current means to generate a base current corresponding to a digit number of specific bits so as to configure the low-order current cells 12 and the D/A converter generates a constant current of one over 2's power with respect to the basic current by distributing equally the basic current to a 2's power number of branches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to a D / A converter for adding and outputting a constant current output of a current cell selected according to the data value of a multi-bit digital input signal.
The present invention relates to a technology that is effective when applied to a / A converter, for example, a technology that is effective when used for a D / A converter for video signal processing.

[0002]

2. Description of the Related Art Conventionally, as this type of D / A converter,
A large number of uniformly weighted current cells are used to generate the same constant current, and a number of current cells according to the data value of the multi-bit digital input signal are selected from this current cell group. There is provided a device in which an analog current output corresponding to the digital input signal value is obtained by adding and outputting a constant current output of a selected current cell (for example, “Nikkei Electronics 198” published by Nikkei BP).
May 16, 2008 Issue (No. 447) "pp. 165-1
75).

[0003]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, the above-mentioned D / A converter has a problem that the circuit scale increases rapidly as the bit resolution increases.

For example, a 6-bit D / A converter can be constructed using 63 constant current cells, but an 8-bit D / A converter that is 2 bits larger than this has 255 constant current cells. Required. For this reason, even if a D / A converter having a high bit resolution is to be configured as an LSI (semiconductor integrated circuit device), a significant increase in the chip area is unavoidable, and the cost is significantly increased accordingly. Problems arise.

Therefore, the present inventors use, for example, 63 high-order current cells configured to generate a constant current having a weight of 4 when constructing an 8-bit D / A converter. Two types of lower current cells configured to select the number of current cells according to the upper 6-bit data value of the 8-bit digital input signal from the upper current cells of the above and generate currents of weights 2 and 1, respectively. The present inventors have studied a configuration in which these two types of lower current cells are selected by the lower two bits of the input signal, and the constant current outputs of the upper and lower current cells thus selected are added and output. According to this, a D / A converter with an 8-bit resolution can be constituted by only 63 upper current cells and 2 lower current cells, that is, a total of 65 current cells.

The D / A converter having an 8-bit resolution has a resolution of 2 bits by adding two types of lower-order current cells having weights of 1/2 and 1/4 in addition to the above configuration. It can be increased to 10 bits. In this case, 10-bit D / A conversion is performed by selecting 64 upper current cells by the upper 6-bit data of the input signal and selecting 4 types of lower current cells by the lower 4-bit data. Can be. However, for this purpose, it is necessary to assign five types of weights having a difference of 16 times at the maximum from 4 to 1/4 with high accuracy.
If the accuracy of the weighting is insufficient, the change accuracy of the analog output with respect to the change of the digital input signal, that is, the so-called differential accuracy cannot be secured.

A current cell is formed by using an active element such as a MOS transistor. When a current cell having five weights from 4 to 1/4 is formed by using this MOS transistor, the following is required. (Gate length to width ratio)
.., And (B) two, four MOS transistors of the same size using the basic weight of 最小 of the minimum weight.
・ By connecting in parallel with, 2 times the above basic unit, 4 times
There is a method of forming a current cell having a weight of twice,.

In the former method (A), a small weight 1 /
In the configuration of the current cell of 2/4, the gate length of the MOS transistor must be extremely large with respect to the gate width, which causes an unreasonable structure of the element, and errors such as manufacturing variations are caused by other sizes. , The reproducibility of the accuracy is poor. In the latter method (B), the number of transistors connected in parallel increases as the weight increases, and when the minimum weight is 1/4, as many as 16 transistors are connected in parallel in the upper current cell having a weight of 4 Have to do it.

As described above, in order to increase the bit resolution, the accuracy of the lower current cell must be increased. However, in order to increase the accuracy of the lower current cell, the element in the upper current cell that occupies the majority of the current cells is required. The size or the number of elements had to be greatly increased, and in any case, a remarkable increase in the scale of the circuit was unavoidable.

An object of the present invention is to provide a technique for increasing the resolution of a D / A converter without significantly increasing the circuit scale.

The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

That is, a number of upper current cells (1) uniformly weighted to generate the same constant current (4 × Io)
1) and the lower current cell (1) weighted to generate a current of a power of 2 to the upper current cell (11).
2 to 15) and a multi-bit digital input signal (DO to D)
9) selecting means (21, 24) for selecting the number and / or type of current cells according to the data value of 9), and by adding and outputting the constant current outputs of the selected current cells,
In the D / A converter adapted to obtain an output current according to the digital input signal value, the lower current cell (14, 1
In order to constitute the above 5), a constant current means for generating a basic current corresponding to a digit value of a specific bit, and the basic current is divided equally into several power branches of 2 so that the basic current can be reduced. A branching means for generating a constant current of a power of 1/2 is provided.

According to the above-described means, it is possible to use an element having an extremely deformed size or shape and without greatly increasing the number of elements in an upper current cell corresponding to an upper bit of a digital input signal. Current cells having different weights can be configured with high precision using only elements of the same size that can easily provide relative ratio accuracy. This achieves the object of increasing the resolution of the D / A converter without significantly increasing the circuit scale.

The number of the upper current cells (11) is selected according to the data value of the upper bits (D4 to D9) of the digital input signal.
15) is selected in accordance with the bit values of the lower bits (D0 to D3) of the input signal. Thereby, the bit resolution can be increased by adding the lower current cell.

Further, the lower current cells (14, 15)
The constant current means (P11) for generating a basic current (Io) corresponding to the digit value of the specific bit (D2) and the basic current (Io) are equally divided into several powers of 2 A branching means (P31 to P34) is provided for taking out, as an output current, a current of a power of 2 with respect to the basic current from one branch path. This allows
A high-precision current cell can be obtained with elements of the same size.

Further, there is provided a branch load circuit (16) for supplying a branch current other than the branch current extracted from the branching means under the same load condition as the branch current extracted as the output current. As a result, the current can be equally branched with high accuracy.

Further, a branch current other than that taken out from the branch means as an output current is supplied to a terminal (ou) which is voltage-controlled so as to have the same potential (Va) as the analog output terminal.
A branch load circuit (16) to be received at tB) is provided. Thus, the load conditions on all the branch paths can be made uniform regardless of the load state of the analog output terminal.

Further, the current cell is constituted by a constant current circuit of MOS transistors (P11 to P14, P31 to P34), and the current weight of the constant current circuit is determined by the number of parallel connection of a plurality of MOS transistors having the same characteristic. To do. As a result, high relative accuracy can be obtained without being affected by manufacturing variations or the like.

Further, a plurality of MOS transistors (P31-P34) connected in parallel and operated at a constant current at the same reference voltage have the lower current cell (1).
By forming the branch of (4, 15), a highly accurate current branch can be realized.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a D / A converter to which the technique of the present invention is applied.

The D / A converter shown in FIG. 1 has a resolution of 10 bits, and includes a current cell group 100, a decoder 21,
Data latch circuits 22, 23, buffer / inverter 2
4, a 10-bit digital input signal (D0 to D0)
An analog output current (Aout) having a magnitude corresponding to the data value of D9) is generated.

The current cell group 100 includes 63 upper current cells 11 arranged in an 8 × 8 matrix.
And four types of lower current cells 12 to 15.

The upper current cells 11 are provided with 63 (= 2 ⁶ -1) corresponding to the upper 6-bit data (D4 to D9) values of the digital input signals (D0 to D9). It is uniformly configured to generate a constant current (4 × Io) having the same weight of 4.

The number of the higher-order current cells 11 is selected by the decoder 21 in accordance with the upper 6-bit data value of the digital input signals (D0 to D9). The decoder 21 has an 8 × 8 matrix selection output line, and selects the number of current cells 11 corresponding to the value of the upper 6-bit data (D4 to D9) of the digital input signal (DO to D9). The output current of the selected current cell 11 is added and output to an analog output terminal (Aout).

The lower current cells 12 to 15 are provided in a total of four (four types), one for each of the lower four bits (D0 to D3) of the digital input signal (D0 to D9). Are individually selected in accordance with the logical value ("1" or "0") of the bit corresponding to. In this case, the current cell 12 corresponding to the lower fourth bit D3 has a weight of 2, the current cell 13 corresponding to the lower third bit D2 has a weight of 1, and the current cell 14 corresponding to the lower second bit D1 has a weight of 1. / 2, the current cell 15 corresponding to the least significant bit D0 is given a weight of 1/4. The output currents of the lower current cells (12 to 15) selected by the lower 4 bits (D0 to D3) of the input signal are added and output to the analog output terminal (Aout).

Further, as will be described in detail later, the current cell 14 having a weight of 1/2 applies a current Io having a weight of 1 to two branch paths.
o / 2 equally, and one of the branches
The current (Io / 2) taken out of the circuit is taken out as a 1/2 weight output current (FIG. 5).
Similarly, a current cell 15 having a weight of 1/4 is connected to a current I having a weight of 1
o is equally divided into four branches by Io / 4 at a time, and a current (Io /
4) is extracted as an output current having a weight of 1/4 (FIG. 6). The current of the other branch path not taken out as the output current is supplied to the branch load circuit 16 which forms the same load condition as the branch current taken out as the output current (FIG. 7).

As described above, the constant current of weight 4 (4 ×
Io), the upper current cell 11 configured to generate 64
The number of current cells 11 corresponding to the value of the upper 6-bit data (D4 to D9) of the input signal is selected from among the 64 upper current cells 11 and the weights 2, 1, 1
/ 2, 1/4 current (2 × Io, 1 × Io, Io / 2,
Io / 4) are generated using four types of lower current cells 12 to 15, respectively, and these four types of lower current cells 12 to 15 are connected to the lower four bits (DO to D) of the input signal.
3), and the constant current outputs of the upper and lower current cells 11 to 15 selected in this way are added and output, so that a total of 67 currents of 63 upper current cells and 4 lower current cells are provided. D / A conversion with 10-bit resolution can be performed using only cells. The D / A conversion output is in the form of a current, but the output current (Aout) can be converted to an output in the form of a voltage (Ra × Aout) by passing the output current (Aout) through a predetermined resistance element Ra.

FIG. 2 shows an example of a specific circuit configuration of the upper current cell 11.

The current cell 11 shown in FIG.
It is configured using OS transistors P11 to P14, P2, P3 and n-channel MOS transistors N1, N2. p-channel MOS transistors P11 to P14
Are formed to have the same characteristics with the same gate length and gate width. Four of the p-channel MOS transistors P11 to P14 are connected in parallel with each other, and the common source is connected to the power supply potential Vcc.
And a reference voltage Vref for constant current control is connected to the common gate.
When 1 is applied, a constant current (4 × Io) having a weight of 4 is output from the common drain. The constant current output (4 × Io) is led to an analog output terminal (Aout) via a p-channel MOS transistor P3 connected in series to the common drain of P11 to P14.

The reference voltage Vref1 is supplied between the gate and the source of a MOS transistor (not shown) whose drain and gate are commonly connected and which is connected so that a predetermined reference current flows between the drain and the source. Given. That is, P11 to P14 operate as a transfer output circuit of the current mirror to generate a constant current at a fixed ratio with respect to the reference current.

The p-channel MOS transistor P3 has p
Since it is interposed in series between the channel MOS transistors P11 to P14 and the analog output terminal (out) and given a constant reference voltage Vref2 to its gate, it functions as a kind of buffer for preventing interference between the current cells 11. I do.

The p-channel MOS transistor P2 and the n-channel MOS transistor N2 form a CMOS inverter. This CMOS inverter is a decoder (21)
Logically inverts the selection signal generated in step (1) and outputs the result. The n-channel MOS transistor N1 is diode-connected,
ON / OFF depending on the logic output state of the CMOS inverter
By being turned off, the output of the current cell 11 is turned on / off.

That is, when the selection signal is "1" (high), the output of the CMOS inverter becomes "0" (low), so that N1 is turned on.
The constant current (4 × Io) generated by 11 to P14 is bypassed by N1 and is no longer output. On the other hand, when the selection signal is "0", the output of the CMOS inverter becomes "1", thereby turning off N1.
The constant current (4 × Io) generated by 11 to P14 is output as it is without being bypassed by N3. When N1 is turned on, p-channel MOS transistor P3 prevents reverse flow of current from another current cell.

FIG. 3 shows an example of a specific circuit configuration of the lower current cell 12 having a weight of 2.

The current cell 12 shown in FIG. 3 is a cell selected by the lower fourth bit (D3) of the digital input signal, and has the same characteristics and has two p-channel MOS transistors P11 and P11. By connecting P12 in parallel, a constant current of weight 2 (2 × Io) is output.

FIG. 4 shows a specific circuit configuration example of the lower current cell 13 having a weight of one.

The current cell 13 shown in the figure is a cell selected by the lower third bit (D2) of the digital input signal, and is a single p-channel MOS transistor P1.
It is configured to output a constant current (1 × Io) having a weight of 1 by only 1.

FIG. 5 shows a specific circuit configuration example of the lower current cell 14 having a weight of 1/2.

The current cell 14 shown in the figure is a cell selected by the lower second bit (D1) of the digital input signal, and is a single p-channel MOS transistor P1.
1, a constant current (1 × Io) having a weight of 1 is generated, and the generated current (1 × Io) is
The current is equally distributed to the OS transistors P31 and P32.

P channel MOS transistors P31, P
32 are formed to have the same characteristics by the same gate length and gate width, and are connected in parallel with each other;
In addition, the reference voltage Vref2 is applied to the common gate, thereby forming a branch path for equally dividing the generated current of weight 1 into two. As a result, a current (Io / 2) having a weight of 1/2 flows through each branch path. Therefore, a current (Io / 2) having a weight of 1/2 can be extracted from one of the two branch paths and output. The current (Io / 2) flowing through the other branch path is supplied to the branch load circuit 16 that forms the same load condition as the analog output terminal (Aout).

FIG. 6 shows a specific circuit configuration example of the lower current cell 15 having a weight of 1/4.

The current cell 15 shown in the figure is a cell selected by the lower first bit (D1) of the digital input signal, and has one p-channel MOS transistor P1.
1, a constant current (1 × Io) having a weight of 1 is generated, and the generated current (1 × Io) is generated by four p-characters having the same characteristic.
Channel MOS transistors P31, P32, P33,
The flow is evenly distributed to P34. As a result, a current having a weight of 1/4 (Io /
4) starts to flow. Therefore, a current (Io / 2) having a weight of 1/4 can be extracted from one of the four branch paths and output. The current (3 × Io / 4) flowing through the other branch path is supplied to the branch load circuit 16 that forms the same load condition as the analog output terminal (Aout).

FIG. 7 shows a specific example of the circuit configuration of the branch load circuit 16.

The branch load circuit 16 shown in FIG. 3 is constituted by using n-channel MOS transistors N41, N42, N43 and p-channel MOS transistors P41, P42, P43, and applies a voltage Va appearing at an analog output terminal (Aout) to P41 and The signal is transmitted to the output terminal outB by each source follower of N41. By causing the terminal outB, which is voltage-controlled to the same potential as the analog output terminal (Aout), to receive the branch current from the lower current cells 14 and 15 in this manner, the load conditions on all the branch paths are analog-output. Regardless of the load state of the terminals, they can be made the same. As a result, a basic current (I) of weight 1 generated by only one MOS transistor
o) can be equally branched with high precision.

As described above, without using an element whose size or shape is extremely deformed, and without greatly increasing the number of elements in an upper current cell corresponding to an upper bit of a digital input signal, Current cells having different weights can be configured with high accuracy by using only elements of the same size that can easily provide specific accuracy, thereby increasing the resolution of the D / A converter without significantly increasing the circuit scale. it can.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the configuration may be such that the weight of the upper current cell 11 is 1 and the weight of the lower current cell is 1/2 to 1/16. Further, the current cells 11 to 15 and the branch load circuit 16
Can be partially or entirely configured using bipolar transistors.

In the above description, mainly the case where the invention made by the present inventor is applied to a 10-bit D / A converter for video signal processing, which is the background of the application, is limited. Not something
For example, D for audio or digital communication
It is also applicable to the / A converter.

[0051]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the resolution of the D / A converter can be increased without significantly increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a D / A converter to which the technology of the present invention is applied.

FIG. 2 is a circuit diagram showing a specific configuration example of an upper current cell

FIG. 3 is a circuit diagram showing a specific configuration example of a lower-order current cell having a weight of 2;

FIG. 4 is a circuit diagram showing a specific configuration example of a lower-order current cell having a weight of 1;

FIG. 5 is a circuit diagram showing a specific configuration example of a lower current cell having a weight of 1/2.

FIG. 6 is a circuit diagram showing a specific configuration example of a lower current cell having a weight of 1/4;

FIG. 7 is a circuit diagram showing a specific configuration example of a branch load circuit.

[Explanation of symbols]

Reference Signs List 100 current cell group 11 upper current cell (weight 4) 12 lower current cell (weight 2) 13 lower current cell (weight 1) 14 lower current cell (weight 1/2) 15 lower current cell (weight 1/4) 16 branch Load circuit 21 Decoder 22, 23 Data latch circuit 24 Buffer inverter D0 to D9 Digital input signal (10 bits) Aout Analog output current P11 to P14 P-channel MOS transistor (for generating constant current) P31, P34 P-channel MOS transistor (branch) (For road formation)

Claims (7)

[Claims] 1. A large number of upper current cells which are uniformly weighted to generate the same constant current, and a lower weight which is weighted to generate a current of a power of 2 with respect to the upper current cell. A current cell and selecting means for selecting the number and / or type of current cells according to the data value of the multi-bit digital input signal, and adding the constant current outputs of the selected current cells to output the digital data. A D / A converter adapted to obtain an output current according to an input signal value, wherein said constant current means generates a basic current corresponding to a digit value of a specific bit in order to constitute a lower current cell; Basic current is 2
D / A comprising a branching means for generating a constant current equal to one power of two with respect to the basic current by equally dividing the current into the several powers of the branch path.
converter. 2. An upper current cell is provided such that a number corresponding to a data value of an upper bit of a digital input signal is selected, and a lower current cell is selected according to a bit value of a lower bit of the input signal. The D / A converter according to claim 1, wherein the D / A converter is provided as follows. 3. A constant current means for generating a basic current corresponding to a digit value of a specific bit as a lower current cell, and a single branch path by dividing said basic current equally into several power branches of 2 3. The D / A converter according to claim 1, further comprising a branching unit configured to extract, as an output current, a current that is a power of 2 with respect to the basic current. 4. 4. A branch load circuit for supplying a branch current other than the branch current extracted from the branching unit as an output current under the same load condition as the branch current extracted as the output current. 3. The D / A converter according to any one of 3. 5. A branch load circuit which receives a branch current other than an output current from the branching means at a terminal which is voltage-controlled so as to have the same potential as an analog output terminal. The D / A converter according to claim 1. 6. The method according to claim 1, wherein the current cell is constituted by a MOS transistor constant current circuit, and the current weighting of the constant current circuit is performed by the number of parallelly connected plural MOS transistors having the same characteristic. 6. The D / A converter according to any one of 5. 7. A branch circuit of a lower current cell is formed by a plurality of MOS transistors having the same characteristics and connected in parallel to each other and operated at a constant current at the same reference voltage. 3. The D / A converter according to 1.