JPS6244728B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a D-A converter that converts digital signals into analog signals.

As is well known, the main parameters that determine the accuracy of this D-A converter are linearity (relative accuracy), which represents the deviation between the ideal straight line connecting the full scale and zero point and the actual analog output signal, and the 1-bit digital input code. Ideal 1LSB when changes by 1LSB
These include differential linearity, which represents the deviation of actual analog output changes with respect to voltage changes, and monotonicity, which represents the characteristic that the analog output increases and decreases in the same way as the digital input increases and decreases.

A current source, for example a weighted current source (I, I/2,...I/2 ⁿ
) are connected in parallel and a weighted current source is selected according to the digital input to obtain an analog output (current). In this case, the accuracy of the weighted current source is directly related to the accuracy of this DA converter. Therefore, efforts have been made to improve the accuracy of each weighted current source.

As an example, a method has been proposed in which n minute current sources (1/n·I) are collected as a current source I, and 1/2n are collected as a current source I/2. In this method, assuming that the variation in the minute current source forms a Gaussian distribution, the variation in the current source I also forms a Gaussian distribution, and its standard deviation σ _I becomes σ _I =√σ〓 (1). In equation (1), σ is the standard deviation of the minute current source. This standard deviation σ〓 is There will be variations in

Therefore, let us consider the variation of the minute current source as σ〓/
Assuming that 1/n・I=0.01, in order to input the variation Eσ 〓 in the above equation (2) to the equivalent of 16 bits, it should be within the range of ±1/2 LSB. becomes. Therefore, the number of minute current sources required to maintain high accuracy of the D-A converter using this method is 1.8 million, which is extremely difficult to implement.

This problem can be solved by configuring the D-A converter as follows.

In other words, for example, a digital code is divided into upper bits and lower bits, a matrix circuit of minute current sources is constructed in relation to these upper bits and lower bits, and the circuits are placed at the intersections of the matrix circuits according to the code of the digital data. A DA converter is configured to determine the number of intersection selection elements and convert them to analog signals.

When using a 16-bit D-A converter with a resistor ladder circuit, if 11 bits are assembled into a matrix circuit, the standard deviation of the minute current source σ
Assuming that is 0.01, the microlinearity is σ〓/2048≒4.9×10 ^-6 …(4). This value is equivalent to 1/3 LSB of 16 bits, and it is understood that its accuracy is sufficiently guaranteed, especially in D-A converters where monotonicity and differential linearity are important.

That is, by adopting a novel means of arranging minute current sources in a matrix, it is possible to significantly reduce the number of minute current sources while maintaining high accuracy.

FIG. 1 is a system diagram showing an example of a new D-A converter with such a configuration. In an n-bit D-A converter, n-bit digital data is converted into upper _bits ( _n and the lower bit n _z , and the minute current source ΔI is divided into 2(n _x + n
_y ) are used to configure a 2 _ox × 2 _oy matrix circuit 1, and the intersection selection element including the minute current source ΔI arranged at the intersection of this matrix circuit 1 is selected according to the input digital data to generate an analog signal. Convert to quantity. Further, the lower _nz bits are subjected to analog processing by, for example, a resistor ladder circuit 3 whose accuracy is sufficiently guaranteed. Then, the configuration is such that the synthesized analog amount obtained from these is taken out as an output. 4A,
4B and 5 are decoders.

When resistor ladder circuit 3 is not used, n _z
=0, so in this case, the above-mentioned matrix circuit is configured with n _x + _ny = n.

The matrix circuit 1 is as shown in FIG.
In addition to the X and Y lines, the same number of Z lines as the X lines are provided on the X line side. The figure shows n _x =6, n _y
=5, thus indicating a 2 ⁶ × 2 ⁵ matrix circuit.

At least one X line is designated by the code of the input digital data, and all Y lines below the designated line are turned on.

Further, as the Z line, all lines one line or less from the designated X line (or the last line if there are multiple designated lines) are designated.

The above-mentioned intersection selection element 2 is provided at each intersection of the X and Z lines and the Y line, and this has a configuration as shown in FIG. 3, for example.

In the figure, Q ₁ is a transistor that constitutes a minute current source ΔI, D is a switching diode, and 6
is its control circuit, which is composed of transistors Q ₂ and Q ₃ . One transistor _Q3 is a multi-emitter transistor.

Next, the operation of the intersection selection element 2 will be explained with reference to FIG. 4, which shows the operation mode of the diode D. In the steady state, both the Xi and Yj lines are at a logical high level, ie, "H", and the Zi line is at a logical low level, ie, "L".

As is clear from Fig. 4, when the Zi line is on, that is, "H", the transistor _Q3 is
Since it is off regardless of the potential of the Xi and Yj lines and transistor Q ₂ is also off, diode D is on, and as a result, the current of the small current source, that is, the collector current of transistor Q ₁ is
The analog output corresponding to the output line OUT is obtained. Furthermore, even when the Zi line is off or "L", when both the Xi and Yj lines are on or "L", transistor _Q3 is off and transistor _Q2 is also off, so the current of the minute current source is similarly Derived as an analog output to the output line OUT.

On the other hand, when the Zi line is off or “L”, the Xi
When at least one of the and Yj lines is off, that is, “H”, transistor Q ₃ is turned on, transistor Q ₂ is turned on, and diode D is reverse biased, so the current of the minute current source is transferred to the output line OUT.
is not derived.

Therefore, in FIG. 2, for example, when the input digital data code [ ^MSB 10000010000] is supplied to the decoders 4A and 4B, the _X31 line of the matrix circuit 1 is designated. Further, by specifying the _X31 line, all lines _Z0 to _Z30 are selected and turned on in the Z line. On the other hand, the above code specifies _Y16 on the Y line, and all lines below this line, that is, lines _Y0 to _Y15 , are turned on. In this way, all intersection selection elements 2 arranged at intersections smaller than the intersection specified by the X line and the Y line become energized, and a current corresponding to the number of intersection selection elements 2 in this energized state is applied. Taken out as analog output. The shaded intersection selection element 2 in FIG. 2 indicates that it is in an energized state by the above-mentioned code.

Now, as is clear from the above explanation, the matrix circuit 1 used in the D-A converter
Since the intersection selection element 2 must use a relatively complicated control circuit 6, the matrix circuit 1
The overall configuration is complicated, and D-A with large bits is required.
Not suitable for converters. In addition, since there are many lines, it is difficult to create a circuit, and there are many failures, making it unsuitable for IC circuits.

Therefore, this invention is devised so that it can be easily constructed by using a matrix circuit.

An example of the present invention will be described in detail below with reference to the drawings.The embodiments shown in FIG. In this case, the matrix control operation in that case will first be explained with reference to FIGS. 5 and 6.

The example shown is for a 6-bit DA converter, and if n _x = _ny = n _z =2, the matrix circuit 1 will be as shown in FIG. The numbers I ₁ to _{I 16} inside the matrix circuit 1 are the numbers of the current sources ΔI. Furthermore, when the decimal numbers of the data codes included in the upper bits n _x and n _y are N _x and N _y , these are used for line designation (address data) of the X line and Y line as shown in Figure 6. .

That is, all of the X lines below N _x -1 are designated regardless of N _y , and all current sources included therein are added. The N _x line is selected by the value of N _y and all current sources of the N _x line that intersect with the Y line less than or equal to N _y -1 are specified, and
The N _x line that intersects the N _y line is designated as a current source for the resistance ladder circuit 3 . Y greater than or equal to N _y +1
The current sources of the N _x lines that intersect the lines are not specified. Similarly, X lines of N _x +1 or more are not specified regardless of the value of N _y .

Let me give you a concrete example. For example, when digital data with a 6-bit code [ ^MSB 100101] corresponding to the decimal number "37" is input, n _x = n _y = 2, so the data code included in n _x is [10], n _y
The data code included in is [01], so N _x
=2, N _y =1. So the X ₀ line and the X ₁
The line has all current sources (I ₁ to I ₈ ) specified,
The X ₂ line specifies a current source I ₉ that intersects the Y ₀ line, and a current source I ₁₀ that intersects the Y ₁ line.
is designated as the current source of the resistance ladder circuit 3.

The resistance ladder circuit 3 in the case of n _z =2 is configured as shown in FIG. 7, for example, and when the code of n _z is [01], a current of 1/4ΔI is obtained by the output of the decoder 5.

Therefore, since the total current I _M specified by the matrix circuit 1 is I _M =I ₁ +I ₂ +...I ₉ =9ΔI, when the current I _R specified by the resistance ladder circuit 3 is added, the total current I I=I _M +I _R =9ΔI+1/4ΔI=37/4ΔI, and an analog output current 37/4ΔI corresponding to the decimal number "37" is obtained.

FIG. 8 shows a specific example of the matrix circuit 1, and corresponds to FIG.

In the X direction, four sets of control lines each consisting of a pair of lines Ai and Bi are arranged, and in the Y direction, four sets of control lines each consisting of a pair of lines Ci and Di are also arranged. An intersection selection element 2 is arranged at the intersection of each control line. The intersection selection element 2 includes a minute current source ΔI and four switching diodes Aij connected between each control line and the minute current source ΔI.
〜Dij and these diodes Aij〜Dij
is controlled by controlling switching transistors Qai to Qdi connected to each control line.

The control lines Ai and Ci are also used as signal lines, and the collectors of the switching transistors Qai provided on the control line Ai are connected in common to the output terminal 10, and the collectors of the switching transistors Qai provided on the other control line Ci are connected in common. The respective collectors of the switching transistors Qci are also connected in common and then connected to the above-mentioned output terminal 10 via the resistance ladder circuit 3.

Note that the collectors of the switching transistors Qbi and Qdi provided on the other control lines Bi and Di are also commonly connected and connected to the power supply terminal 11, but the current flowing through this terminal 11 is the current for the D-A converter. It is not used as such.

Transistors Qai and Qbi are controlled by the output of decoder 4A, and transistors Qci and Qdi are controlled by the output of decoder 4B. Figure 9 is a transistor
An example of decoded output for controlling Qa to Qd is shown.

In this figure, Vc is the reference voltage and ΔV is 0.2~
A minute voltage of 1.0V, -∞, represents a voltage sufficiently lower than the reference voltage Vc. The decode output voltage is
There are four types of voltages: Vc, Vc-ΔV, Vc-2ΔV, and -∞, and the -∞ voltage is further divided into two types depending on the combination of decode outputs. In this example, -∞ ₁ = (Vc-3ΔV) or less -∞ ₂ = (Vc-2ΔV) or less. Of course, the following selection may be made: −∞ ₁ =−∞ ₂ =(Vc−3ΔV).

In the case of the decimal number "37", the data code input to the decoder 4A is "10", and the data code input to the decoder 4B is "01". At this time, a decode output having a predetermined potential as shown in FIG. 9 is obtained from the husband's decoders 4A and 4B, and transistors Qai to Qdi are controlled by this, so that X ₀
On the line, all diodes A ₀₀ to _{A 03} are turned on,
In the X ₁ line, all diodes A ₁₀ to _{A 13} are turned on, and in the X ₂ line, diodes A ₂₀ (Y ₀ line), C ₂₁ (Y ₁ line), D ₂₂ (Y ₂ line) and D ₂₃ are turned on.
( _Y3 line) are respectively turned on, and all of the diodes _B30 to _B33 are turned on in the _X3 line.

Therefore, a signal line as shown by the broken line is formed between the output terminal 10 and the minute current source ΔI, and a signal line as shown by the broken line is formed between the resistance ladder circuit 3 and the minute current source ΔI (current source corresponding to _I10 ). A signal line as shown by a broken line is also formed. The resistance ladder circuit 3 is controlled by the output of the decoder 5, and therefore the output terminal 1
A current of 37/4ΔI flows through 0.

On the other hand, diodes D ₂₂ , D ₂₃ and B ₃₀ to B ₃₃
The minute current source in the control line formed by this does not contribute at all to DA conversion.

Note that in FIG. 8, the first line _D0 of the control lines Di does not contribute to the circuit operation, so it is not necessary to provide this line. Therefore, diodes D ₀₀ to D ₃₀ and transistor Qd ₀ are unnecessary.

FIG. 10 shows another specific example of the matrix circuit 1. That is, the specific example of FIG. 8 mentioned above is 1
This is a case where control lines for signals and other control lines for the two intersection selection elements 2 are provided independently for the X line and the Y line, respectively.
The example in Figure 0 is a case where the number of control lines is further omitted. That is, both the X line and the Y line are composed of one control line Ri, Si, and the switching diodes Rij, Sij are also connected to each control line Ri, Si.
One is provided corresponding to each.

The control line A, which is also used for signal extraction, from which the output terminal 10 for signal extraction is derived is connected to the common control line Ri via the switching transistor Qai.
A control line B, which is also connected to the current drain terminal 11 and also used for current draining, is connected to a common control line Ri via a switching transistor Qbi.

On the other hand, the common control line Si provided on the Y line side is provided with three switching transistors Qci to Qei, and one line C is connected to the output terminal 10 as a control line for signal extraction. One line E is connected to the output terminal 11 as a control line for draining current, and the remaining control line D is connected to the current path of the resistance ladder circuit 3.

In the case of such a configuration, the same operation as described above can be achieved by forming a decoded output as shown in FIG.

Here, the potential relationship between −∞ ₂ and −∞ ₄ is selected as follows: −∞ ₂ = Vc−2ΔV or less −∞ ₃ = Vc−ΔV or less −∞ ₄ = Vc or less, but −∞ ₂ =− ∞ ₃ = −∞
₄ = Vc - 2ΔV or less may be selected.

Also, as is clear from Fig. 11, the control terminal
Since the potential of both C ₃ and D ₀ remains at _-∞2 , this control system does not need to be provided. Therefore, transistors Qc ₃ and Qe ₀ do not need to be provided.

As explained above, according to the present invention, since a matrix circuit is configured using minute current sources as unit current sources to perform D-A conversion, accuracy such as differential linearity and monotonicity is sufficiently guaranteed. A D-A converter can be obtained. Therefore, the number of minute current sources can be significantly reduced while maintaining high accuracy.

In this invention, the intersection selection element 2 is composed of a minute current source ΔI and a switching element according to the number of lines, and the control lines arranged in the X and Y directions are used as a control line for selecting the switching element. In addition, since it is also used as a signal extraction line for the selected minute current source, the control circuit 6 is not required and the number of lines required is reduced compared to when the intersection selection element 2 is configured as shown in FIG. , and the configuration can be simplified. Therefore, it is suitable for application to a DA converter with a large number of bits, and this DA converter is also suitable for integration into an IC.

Incidentally, when the matrix circuit 1 is configured as shown in FIG. 10, it is possible to further reduce the number of control lines and switching diodes.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing an example of this invention, Fig. 2 is a block diagram of a matrix circuit for explaining the invention, Fig. 3 is a block diagram of the intersection selection element, and Fig. 4 is for explaining its operation. , FIG. 5 is an explanatory diagram of the matrix circuit in this invention, FIG. 6 is an explanatory diagram of its operation, FIG. 7 is an explanatory diagram of the resistance ladder circuit, and FIGS. 8 and 10 are diagrams of the matrix circuit. FIGS. 9 and 11, which are configuration diagrams showing specific examples, are diagrams for explaining the operation. 1 is a matrix circuit, 2 is an intersection selection element, 3
is a resistance ladder circuit, 4A, 4B, 5 are decoders,
ΔI is a minute current source, Aij〜Dij, Rij, Sij, Qai〜
Qei is a switching element, and Ai, Ai to Si are control lines.

Claims (1)

[Claims] 1 A matrix in which input digital data is divided into at least two bit groups, at least two control lines X and Y provided corresponding to the divided data bits, and the control lines X and Y. and a plurality of current switching circuits provided corresponding to the current sources for switching the current paths of the current sources to the X line and the Y line, respectively. , selectively connects the current sources at the intersections of the predetermined matrix to the control lines X and Y in response to input data codes applied to the control lines X and Y; A D-A converter characterized by adding currents from current sources.