JPH05268093A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To provide the DAC artificially improving the accuracy while combining DAC parts with low accuracy and requiring small area and consumption current. CONSTITUTION:The system is provided with DAC parts 1 and 2 with low accuracy outputting even-numbered resistance contact voltage of the first resistance ladder which is serially connected between reference voltage VR and ground and uneven-numbered resistance contact voltage. The voltage of the resistance contact of the second resistance ladder serially connected between the output of the DAC parts 1 and 2 is outputted at a DAC part 3 with low accuracy. The DAC parts 1-3 are under the control of the control circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter integrated on a semiconductor substrate, and more particularly to a VCXO.
The present invention relates to a digital-analog converter for control.

[0002]

2. Description of the Related Art A conventional digital-analog converter (hereinafter referred to as a DAC device), particularly a resistor ladder type high resolution DAC device, receives a high-order bit for conversion.
Second DAC section for converting the lower bit to input
An AC output section is provided, and an analog output voltage is obtained by adding these outputs by an operational amplifier. Such DA
In order to guarantee the monotonic increase in the C device, the first DAC is used.
The precision of the part is not the precision of the upper bits, but an error of 1/2 or less of the least significant bit of all the bits is required. That is, the first DAC unit is required to have high accuracy in resolution. As a countermeasure, high accuracy is obtained by changing the full-scale voltage of the second DAC section, or by providing a redundant bit in the second DAC section and writing compensation data in the PROM.

FIG. 4 is a block diagram of a conversion unit in a high precision DAC device for explaining such a conventional example. Figure 4
As shown in FIG. 1, the conventional DAC device has (2 ⁸ −1) resistors RC1 to RC between the reference voltage terminal VR and the ground potential terminal.
It has a resistor ladder connected to 255 and 2 ^four resistors RD0~RD15 in series, connects the master decoder 15 and a slave decoder 16 to the resistor ladder.
Moreover, the contact voltages selected by the decoders 15 and 16 are added by the operational amplifier 18 and the adder circuit 17 including a resistor to output the added voltage. Here, the accuracy of each resistor cannot guarantee the monotonic increase unless it satisfies 15 × RD <RC <17 × RD. Therefore, if the resistance RD is a unit resistance, 2 ^{(8 + 4)} = 4
It is necessary to connect 096 unit resistors.

[0004]

SUMMARY OF THE INVENTION The conventional DAC described above.
In order to increase the accuracy of the ladder resistance, the device must have a large number of unit resistances arranged by the number of resolutions, and must pass a relatively large current. Therefore, there is a drawback that the area is increased and the current consumption is increased in order to increase the resolution.

An object of the present invention is to improve the resolution with high accuracy, and to reduce the area and current consumption.
To provide an AC device.

[0006]

The DAC device of the present invention comprises:
A first digital-analog converter for outputting the voltage of an even-numbered resistance contact of the 2 ⁿ first resistance ladders connected in series between the reference voltage terminal and the ground potential terminal; and the first resistance ladder. inner odd-th and second digital-to-analog converter for outputting a voltage of the resistor contact, cascaded to 2 ^i-number of the second resistor between the output of the first and second digital-to-analog conversion of the A third digital-analog converter that outputs the voltage of the resistance contact of the ladder, and (n + i) -bit control data by inputting n-bit digital data to generate the first to third digital-analogs. And a control circuit for outputting to the conversion unit.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a converter in a DAC device for explaining an embodiment of the present invention. As shown in FIG. 1, the present embodiment has a resistor ladder connected two ^eight resistors RA0~RA255 directly between the reference voltage terminal VR and the ground potential terminal, which is used in common. The voltage of the even-numbered resistance contact of the resistance ladder is converted by the first DAC unit 1, and the voltage of the odd-numbered resistance contact of the same resistance ladder is converted by the second DAC unit 2. The first and second DAC units 1 and 2 are respectively a decoder 4, an operational amplifier 5 and
And a decoder 6 and an operational amplifier 7. Also, the first
And the second is between the output of the DAC portion 1, has a resistance ladder two ^four resistors RB0~RB15 connected in series,
It has a third DAC section 3 for converting the voltage of the resistance contact via a decoder 8 and an operational amplifier 9. These first to third DAC units 1 to 3 select one of the contact points of the resistance ladder by the decoders 4, 6 and 8 and output it by the operational amplifiers 5, 7 and 9. As described below, the first to third DAC units 1 to
Although 3 itself has low accuracy, the accuracy is improved by combining these.

FIG. 2 is a block diagram of a control circuit for controlling the converter shown in FIG. As shown in FIG. 2, the control circuit 10 is a circuit for controlling the above-mentioned three decoders 4, 6, 8 and includes a CPU 11, latches 12, 13 and a counter 14. 8-bit input data is DAT
The latch 12 or 13 is given to the CPU 11 from the A terminal.
Rewrite data on one side. At this time, the latch 12,
The CPU 11 determines which of 13 is larger, and the 4-bit up / down counter 14 for counting the clock φ starts counting according to the result. Next, latch 1
2, 13 and the output of the counter 14 are the first to third DACs.
It is input to the decoders 4, 6 and 8 in the units 1 to 3. Although the resolution when the counter 14 finishes counting 4 bits is 8 bits, the change during counting is 12 at maximum.
It has a bit resolution and can improve the resolution in a pseudo manner.

Since the decoder 4 is connected so as to select an even number and the decoder 6 is selected so as to select an odd number, the least significant bit of the 8 bits of the input data is a selection bit for rewriting either the latch 12 or 13. Used in the top 7
Only bits are sent out. Also, by comparing the data in the latches 12 and 13, and by increasing or decreasing from the previous data,
The up count or down count of the counter 14 is determined. That is, when the data in the latch 12 is large and increases from the previous time, and when the data in the latch 12 is small and decreases from the previous time, the count is up.
When the data of 6 is small and increased from the previous time, and when the data of latch 12 is large and decreased from the previous time, the count is down. Particularly, when the same as the previous time, the clock φ of the count 14 is prohibited.

FIG. 3 is an operation timing chart of each part in FIGS. 1 and 2. As shown in FIG. 3, the third DAC
The output c of the section 3 is the output a of the first DAC section 1 and the second D
The output b of the AC unit 2 is changed in 16 steps, but only 4 steps are shown in the figure for simplification. For example, when the change from the previous time is 3H or more, a quick response is given, and when the change is 2H or less, the error is within the 8-bit resolution.

The DAC device of this embodiment is 1 in the process of change.
Since it changes with 2-bit precision and has 8-bit precision when stable, it is used at low speed and for applications where rapid changes are disliked. Especially in the VCXO control, the output frequency fluctuates due to changes in the DAC output, so a low-pass filter with a large time constant is used or a high-resolution DAC device is used, but this embodiment can be easily implemented. Becomes For example, in case of 8 bits at 4V full scale, it changes about 16mV per LSB, the frequency of VCXO is 10MHz, and the sensitivity is 10ppm.
If it is / V, it will change by 1.6 Hz. On the other hand, with the DAC device of the present embodiment, if the pseudo 12 bits are used, the change is that the output of the DAC device changes by 1 mV and the output frequency of the VCXO changes by 0.1 Hz.

[0012]

As described above, the DAC device of the present invention is provided with the third DAC section which uses the output voltages of the first and second DAC sections as two reference voltages, and has the resistance ladder of 8 bit accuracy and the 4 bit. There is an effect that pseudo resolution of up to 12 bits can be obtained by combining precision resistance ladders. Moreover, there is an effect that the monotonic increase of 12 bits can be guaranteed in principle, although the accuracy of each resistance ladder is low. Furthermore, since the first resistance ladder and the second resistance ladder are separated by the operational amplifier, their resistance value and current are irrelevant, and there is an effect that the degree of freedom in design is increased. Further, since the same operational amplifier is always used, the gain and offset do not affect the error. Therefore, by combining the DAC unit using the low-precision resistor ladder and the operational amplifier, it is possible to realize a high-precision DAC device suitable for integration.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a conversion unit in a DAC device for explaining an embodiment of the present invention.

FIG. 2 is a block diagram of a control circuit that controls the conversion unit shown in FIG.

FIG. 3 is an operation timing chart of each unit in FIGS. 1 and 2.

FIG. 4 is a configuration diagram of a conversion unit in a DAC device showing a conventional example.

[Explanation of symbols]

 1 1st DAC section 2 2nd DAC section 3 3rd DAC section 4, 6, 8 Decoder 5, 7, 9 Operational amplifier 10 Control circuit 11 CPU 12, 13 Latch 14 Counter

Claims (3)

[Claims] 1. A first digital-analog converter for outputting a voltage of an even-numbered resistance contact of 2 ⁿ first resistance ladders connected in series between a reference voltage terminal and a ground potential terminal; 2 ⁱ in cascade connection between the second digital-analog converter that outputs the voltage of the odd-numbered resistance contact of the first resistance ladder and the outputs of the first and second digital-analog converters. And a third digital-analog converter for outputting the voltage of the resistance contact of the second resistance ladder, and (n + i) -bit control data are created by inputting n-bit digital data And a control circuit for outputting to the digital-analog conversion unit of 3. 2. The digital-analog converter according to claim 1, wherein each of the first to third digital-analog converters includes a decoder and an operational amplifier. 3. The control circuit changes one of the first and second digital-analog converters according to input n bits, and changes the outputs of the first and second digital-analog converters. 2. The digital-analog converter according to claim 1, which automatically generates i-bit data that changes minutes with time.