JPS6259492B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Field of Application of the Invention The present invention provides a high-precision AD converter by correcting the output error of an AD converter with poor conversion accuracy using an external logic circuit. This invention relates to a method that facilitates the integration of converters into integrated circuits.

(2) Prior Art In relatively high-speed AD converters with a conversion time of 1 ms or less, successive approximation methods and serial/parallel conversion methods are commonly used as conversion methods. In the latter case, a comparator is provided corresponding to each bit of the output digital signal, and the values of 0 and 1 are determined in order from the most significant bit, and the weight value corresponding to that bit is subtracted from the value of the input analog signal. It involves repeated comparisons and decisions. In the latter case, one comparator is used repeatedly, and the values of 0 and 1 of each bit are sequentially determined by successive comparison of the input analog signal and the DA-converted value of the digital output sequentially specified from the upper bit. The accuracy (especially linear accuracy) of an AD converter using these conversion methods is mainly determined by the conversion accuracy of the DA conversion circuit, which is one of the constituent circuits (in the latter case, the output accuracy of the load circuit). This DA
The conversion circuit also consists of a load circuit, and the conversion accuracy is determined by the degree of variation in constituent elements such as resistors and transistors. Conventionally, when integrating these into integrated circuits,
Due to variations in the constituent elements (resistors, transistors, etc.) of integrated circuits, the upper limit of AD conversion accuracy that can be achieved with good yield is as low as 0.2 to 2% (equivalent to 8 to 6 bits).

(3) Purpose of the Invention The purpose of the present invention is to improve the poor conversion accuracy of the AD converter, and to provide a high-speed, high-precision AD conversion method suitable for integrated circuit implementation.

(4) General description of the invention The principle of the invention is that, as shown in FIG. 1, the output 3 of an AD converter 1 with poor accuracy is input to a memory circuit 2 that stores accurate values corresponding to the output data. , this is a method to obtain high precision output 4.

(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. FIG. 2 is a diagram for explaining the principle diagram shown in FIG. 1 in more detail. In the figure, 1 is an AD converter with low precision, 2 is the address of the output 3 of the AD converter 1, and the output 6 of the high precision AD converter 5.
is a memory element that takes input data.

For convenience of explanation, it is assumed that the number of output bits (=resolution) of both AD converters 1 and 5 is 4 bits. For example, assume that for a certain input _e1 , the output 6 of the reference AD converter 5 is 1101 in order from the most significant bit (hereinafter abbreviated as MSB). On the other hand, assume that the AD converter 1 has poor conversion accuracy and its output 3 becomes 1110. At this time, 1101 is stored in memory 2 at address 1110. Similarly, all output values of the AD converter 1, ie, accurate values for 0000 to 1111, are stored. Once the storage is completed, accurate digital output can be obtained from the output 4 even if the reference AD converter 5 is disconnected. By setting the storage element 2 in this way, an AD converter with poor accuracy can be used with high accuracy. Furthermore, if an RM (read-only memory) is used in which the memory element can be written, it is only necessary to write an accurate value once, and a reference AD converter is required only at that time. For example, AD converter 1 and memory 2 are connected to an IC
(integrated circuit), and if you store accurate values in memory using the above procedure when manufacturing the IC, you can use the IC as an accurate AD converter from now on. In this way, the use of this method has the advantage of making it easier to integrate high-precision AD converters into ICs, which has been difficult in the past.

Next, another embodiment is shown in FIG. The embodiment shown in FIG. 2 requires a very large memory capacity because it stores accurate values for all values of the output of the AD converter, which has poor accuracy.
(For example, for 10 bits, ^{210.times.10104} bits are required.) The embodiment of FIG. ³ improves on this drawback. AD of about 10 bits
If the converter is integrated into an IC, the lower 6 bits can be created with high precision and no correction is required.

Furthermore, although the precision of the upper bits is also poor, the error can be corrected at most with the lower few bits. In the embodiment shown in FIG. 3, the precision of the upper 4 bits is poor in the 10-bit AD converter 11.
This is an example where it is assumed that the error can be corrected using the lowest four bits. The operation is based on the low precision outputs 3-1 to 3-10 of the AD converter 11 and high precision.
The difference between the outputs 6-1 to 6-10 of the AD converter 51, that is, the error of the AD converter 11, is determined by the subtracter 71, and the signal (3-1 to 3-4) consisting of the upper 4 bits is used as an address signal. Write it to memory element 21. Since the above error data obtains positive and negative values,
Sign bit (9-1) + 4 bits (9-2 to 9-
5) for a total of 5 bits. Next, the input voltage is sequentially changed in the same way, and the upper 4 of the AD converters 11
All error amounts for 2 ⁴ =16 types of data consisting of bits are written into the memory 21. After this, if you set the memory 21 to read mode, the AD
Error correction outputs 4-1 to 4-5 can be obtained according to the outputs 3-1 to 3-4 of the converter 11, and if these are added to the outputs 3-1 to 3-10 by the adder 72, Accurate output signal with error correction 8-1~
You can get 8-10. The advantage of this method is that the memory capacity is small, 2 ⁴ × 5 = 80 bits.

Another embodiment is shown in FIG. This embodiment is a method for further reducing memory capacity than the embodiment shown in FIG. In the figure, it is assumed that the 10-bit AD converter 11 has poor accuracy in the upper 4 bits, as in the previous embodiment (FIG. 3), and the error can be corrected with the lowest 4 bits. 21-1～
21-4 is each bit output of the upper 4 bits (3-1 to
This is a memory for storing the error of 3-4), and when the bit output is "1" (or "0"), it outputs the stored contents of the memory corresponding to that bit. Further, 73 is a digital adder for adding the output signals of 21-1 to 21-4. The other parts are the same as the embodiment shown in FIG. That is, the embodiment of FIG. 4 uses memories 21-1 to 21-4 and an adder 73 instead of the memory 21 of the embodiment of FIG.
This uses memory 21
Each of the capacitances from -1 to 21-4 requires a correction bit number, that is, 4 bits in this example, and a total of 16 bits is sufficient.

The embodiments described above (FIGS. 2 to 4) have the following problems. In order to clarify the problem, we used a 4-bit AD converter with successive approximation method as an AD converter with poor accuracy.
Considering the converter, the load accuracy of the lower 2 bits is accurate, and the load accuracy of the upper 2 bits is 20% higher than the ideal value.
Consider the case where it is low. The relationship between analog input and output code when all 4-bit loads are accurate is the fifth one.
As shown in Figure a, if the above-mentioned AD converter is used, the result will be as shown in Figure b. In other words, the loads on each bit of the AD converter are 40, 20, 12.5, and 6.25, respectively, assuming the full scale is 100.
For example, when the input level is 30, the MSB weight is >30, so MSB=0.
Then, since the load of the second bit is <30, the second bit becomes 1, and the AD input level becomes 30-20=10. Therefore, the third bit becomes 0, and then the fourth bit becomes 1. In the end, an output of 0101 is obtained. On the other hand, the ideal value is 0100, so
There is no problem if the correction memory is prepared to output 0100 for 0101 input, but on the other hand, if the input level is 78.75 (40 + 20 + 12.5 + 6.25) or higher, all outputs will be 1111, which is the ideal value and 1: This results in the problem that the solution described in step 1 cannot be taken.

In order to solve this problem, consider the circuit shown in FIG.

FIG. 6 shows an improved circuit configuration of a conventional successive approximation type AD converter. The difference from the conventional circuit is the MSB~
In addition to the load circuit 111 corresponding to LSB, there is also a load circuit 112 for error compensation. Its operation is almost the same as the conventional circuit. For example, 4 bit AD
Considering the converter, first the MSB of register 114
If only is set to 1, the corresponding analog value appears at the output of the loading circuit 111 and is compared with the input voltage e ₁ by the comparator 110. When the input voltage is higher than the load circuit output, the control circuit 113 controls so that the second bit also becomes 1 while MSB=1. Conversely, if the input voltage is smaller than the load circuit output, the MSB is set to 0 and the second bit is set to 1. Here, the input voltage and the load circuit output are compared again, and the register 114 is controlled in the same manner as above.

The lower bits are found in the following order. Here, the comparison order of the error compensation bits may be inserted in the middle of the comparison order of the higher-order bits with poor accuracy (for example, MSB→2nd bit→error compensation bit→3rd bit, etc.). However, the weight value of the error compensation bit is greater than or equal to the maximum value of the sum of errors of the upper bits.

A detailed example of the operation of this circuit is shown below.

Now, an example in which the load value of the error compensation load circuit is set to 25 and applied to the case of FIG. 6 is shown in FIG. 5c.
However, the order of successive approximation is MSB → 2nd bit →
Error compensation bit → 3rd bit → 4th bit. For example, if the input level is 90, MSB = 1
Therefore, the input level is 90-40=50. Therefore, the second bit = 1, and the input level is 50-20
=30. Then, the error compensation bit becomes 1,
The input level is 30-25=5, and the third and fourth bits are both 0. In the end, an output signal of 11100 can be obtained, which corresponds one-to-one with the ideal value 1110. As can be seen from the comparison between c and a in FIG. 5, it is possible to associate one ideal value with each of the outputs of all AD conversion circuits, so the above-mentioned problem can be solved.

As can be seen from this, when this idea is applied to the embodiment shown in Figure 2, the number of output bits of the AD converter (=number of memory address inputs) is equal to the number of conventional digital output bits and compensation bit (1 bit). It is. Further, when applied to the embodiment shown in FIG. 3 (10-bit AD), the memory address has a total of 5 bits, including the upper 4 bits + the compensation bit. Similarly, in the embodiment of FIG. 4, a memory for compensation bits and an adder are required in addition to the memories 21-1 to 21-4.

(6) Summary As explained above, according to the present invention, by adding a simple digital memory to an AD converter with poor linear accuracy, it has the advantage of being able to be used as a high-precision AD converter. This provides an extremely effective method for integrating converters into integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is an embodiment of the present invention for explaining FIG. 1 in detail,
3 and 4 are examples of the present invention, FIG. 5 is a diagram for explaining the necessity of one component of an improved embodiment of the present invention, and FIG. 6 is a diagram showing the components of the improved embodiment described above. 1 is a block diagram of a certain AD conversion circuit.

Claims (1)

[Claims] 1. In an AD conversion device that converts analog input in a predetermined range into a digital signal with a desired number of bits,
Regarding each bit of the desired number of binary weighted bits and a correction bit provided in the middle of each bit, a weight greater than the maximum value of the sum of the errors of each bit weight is applied, An AD conversion circuit that determines the digital output value by a comparator in order from the most significant bit, and a digital value for correction indicating the linear accuracy error of the conversion of the AD conversion circuit for each predetermined value of the most significant bit of the AD conversion circuit. a storage means in which the digital value for correction is read out using the upper bits of the digital output of the AD conversion circuit as an address;
An AD conversion device that includes an adder that adds an output digital value of a conversion circuit and a read correction digital value, and uses the output of the adder as a conversion output.