JPH07321656A - A/d converter and microcomputer mounted a/d converter - Google Patents

Abstract

PURPOSE:To manufacture an A/D converter appropriate for a semiconductor integrated circuit and to easily attain miniaturization and high accuracy by using the output of a 1st D/A converter circuit and summing voltage of 1st and 2nd D/A converter circuits for successive approximation voltages of high and low-order digital bit group respectively. CONSTITUTION:The level of output control signals DCK22, DCK32, DCK44 is kept to an H level during successive approximation of high-order 5 bits. Since CMOS switches CM22, CM32, CM42 are set, the voltage of a voltage division terminal 16 of a resistor ladder circuit 32 is outputted to terminals 101-103. A high level sampling clock SCK is given to switches CM1, CM3 and the left terminal of a capacitor C1 is connected to an unknown input VIN to charge the capacitor. In this case a voltage VSA of a terminal 35 is kept to a constant bias voltage VB. A switch CM2 is set by giving a high level comparison clock RCK to the CM2 and an output VDA of a D/A converter is given to one terminal of the capacitor C1 to compare them. Then in the case of 3-bit successive approximation, summing voltages of the 1st D/A converter circuit and a 2nd D/A converter circuit comprising a 2nd switch decoder circuit 50 and capacitor groups C1-C4 are used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a successive approximation analog
The present invention relates to a digital converter, and more particularly to an analog / digital converter which is required to be small in size and high in accuracy and suitable for being mounted on a microcomputer for use.

[0002]

2. Description of the Related Art As is well known, an A / D converter (analog / digital converter) is a device for converting an analog signal into a digital signal, and there are several methods. One of them is a successive approximation. There is a system A / D converter. As a conventional example of this successive approximation type A / D converter, a capacitance array type, a resistance ladder type, or an R-2R type is used.
Various types such as a resistance type are used depending on the configuration of the comparison voltage generation circuit (D / A conversion circuit).

Therefore, in the following description, the resistance ladder method will be described for the sake of convenience, but the other methods are the same in that the comparison voltage is generated. First, in this resistance ladder type A / D converter, the reference voltage, which is a full-scale voltage, is equally divided by resistors, and a connection point of each resistor is selected by a switch group to obtain a comparison voltage. It is designed to generate. FIG. 9 shows a conventional example of a successive approximation A / D converter having a resolution of 8 bits. In this conventional example, a D / A conversion circuit 100 for generating a comparison voltage, a comparator 102, a control circuit 103, It is composed of an 8-bit successive approximation register 104 and a data bus 105 to which the A / D conversion result is output.

First, in the D / A conversion circuit 100, 2 ⁸ (= 256) resistance elements are connected in series and the resistance ladder circuit 10 is connected.
6, and a voltage equally divided by this is selected by the decoder switch circuit (tree-shaped switch circuit) 107 to generate a comparison voltage. At this time, in order to have the half offset D / A transfer characteristic, in the resistance ladder circuit 106, the resistance values of the resistance elements at both ends of the resistance ladder are 1 with respect to the unit resistance values R of the other portions.
The values are / 2 and 3/2 times.

By the way, in this conventional example, for A / D conversion with a resolution of n bits, 2n resistances and at least 2n or more switch groups are required, and therefore occupied. There is a problem that the area becomes large. On the other hand, the invention according to the application of Japanese Patent Application No. 4-63190 is characterized in that a reference voltage generating region having a low resolution and a reference voltage generating region having a high resolution are provided. However, the essential solution is difficult from the viewpoint of many resistance elements and precision matching.

[0006]

SUMMARY OF THE INVENTION The above conventional technique is
No consideration has been given to the increase in the number of circuit elements accompanying the improvement in the resolution of the D converter, and the high-precision A / D converter has a problem in that the chip size and the cost are increased.
For example, the resolution of the resistance ladder type 10-bit A / D converter is four times that of the 8-bit A / D converter, and while high-precision A / D conversion is possible, the scale of the comparison voltage generation circuit is also four times larger. growing.

That is, in the prior art, in order to increase the resolution of the A / D converter, it is necessary to subdivide the reference voltage (increase the number of resistance elements), so that the scale of the switch circuit and the resistance ladder is increased accordingly. The chip size becomes large, resulting in a large chip size and high cost. An object of the present invention is to provide a small-scale, high-accuracy, high-resolution successive approximation type A / D converter at a low cost in which the increase in the scale of the comparison voltage generation circuit, that is, the D / A conversion circuit, is suppressed as the resolution increases. To do.

[0008]

The above object is to divide a digital group into an upper bit group and a lower bit group in a D / A conversion circuit of a successive approximation A / D converter,
High-order bit group comparison voltage generation circuit (first D / A
Conversion circuit) and a comparison voltage generation circuit for lower bit groups
(Second D / A conversion circuit) is provided, and for the upper bit group successive approximation, the output of the first D / A conversion circuit is used as a comparison voltage for the unknown input analog voltage, and the lower bit group successive comparison is performed. The voltage obtained by adding and subtracting the outputs of the first and second D / A conversion circuits is used as a comparison voltage for the unknown input analog voltage.

[0009]

Operation: For example, successive approximation method A / having a resolution of 8 bits
In the D converter, for example, a D / A conversion circuit having a resistance ladder configuration for high-order 5 bits successive approximation, a D / A conversion circuit having a resistance ladder configuration for low-order 3 bits successive approximation, and a weighting capacitance configuration are used.
A / A conversion circuit, the upper bit group uses the divided voltage of the resistance ladder circuit as the comparison voltage, and the lower bit group generates the comparison voltage by dividing the divided voltage of the resistance ladder circuit with the weighting capacitance. And the successive approximation operation is performed.

Therefore, the number of resistance elements can be greatly reduced as compared with the case where the 8-bit comparison voltage is generated all at once, and as a result, the scale of the D / A conversion circuit can be reduced and high precision can be achieved. It is possible to downsize the A / D converter.

Although the resolution of the A / D converter has been described as an example of the 8-bit configuration to the 10-bit configuration, the present invention limits the number of bits and the allocation of upper and lower bit groups in particular. It may be any number of bits, not just one.

[0012]

Embodiments of the A / D converter according to the present invention will be described below.
This will be described in detail with reference to the illustrated embodiment. FIG. 1 shows an embodiment in which the present invention is embodied as an 8-bit A / D converter. The overall configuration of the A / D converter is shown in FIG.
Since it is the same as the prior art example, only the analog processing section to which the present invention is concerned will be shown in the following description including the drawings unless otherwise specified.

The embodiment shown in FIG. 1 corresponds to claim 1 of the claims, and as shown in the drawing, a resistance ladder circuit 32, a first switch decoder circuit 33, and a second switch. Decoder circuit 50, weighting capacitors (capacitors) C2, C3, C4, sampling capacitors (capacitors) C1, C constituting a chopper type comparator
MOS logic inverter 34 and CMOS switch C
It is composed of M1, CM2, and CM3.

First, the resistance ladder circuit 32 has 2 ⁵ (= 3
2) A plurality of resistance elements R0 to R31 are connected in series. At this time, in order to have a half offset D / A transfer characteristic, the resistance R0 at both ends of the resistance ladder is similar to the conventional example of FIG. And the resistance value of R31 is the other resistance R1.
The unit resistance value R of R30 is 1/2 times and 3 times, respectively.
/ 2 times the value.

Next, the first switch decoder circuit 33
Is composed of, for example, a tree-shaped switch circuit shown in FIG. 2 (a), and has a successive approximation register (not shown.
Upper addresses A3 to A7 supplied from the conventional example).
By the combination of the above, one of the 32 voltage-dividing terminals 1 to 31 including GND, which is divided by the resistance ladder circuit 32, is selected, and the voltage is output as the D / A conversion circuit output voltage V _DA . The first switch decoder circuit 33 is not limited to the above tree-shaped switch circuit, and may be configured by, for example, a matrix switch circuit.

Next, the second switch decoder circuit 50
Is an input terminal (voltage divider terminal), for example, as shown in Fig. 2 (b).
CMOS switches CM21, CM22, CM23 for connecting one of 20, 16, 12 to the output terminal 101
And one of the voltage dividing terminals 18, 16 and 14 as the output terminal 1
CMOS switches CM31, CM32 connected to 02,
CM33 and CMOS switch CM4 for connecting one of the input terminals 17, 16 and 15 to the output terminal 103
1, CM 42, and CM 43.

The selection control operation of the first and second switch decoder circuits 33 and 50 is shown in Table 1 according to the combination of the lower addresses A0 to A2 from a successive approximation register (not shown). Control signal DC
K21, DCK22, DCK23, DCK31, DCK
32, DCK33, DCK41, DCK42, DCK4
It is performed by 3.

[0018]

[Table 1]

Here, the element denoted by CMn is CM.
As shown in the lower right part of FIG. 1, the CMOS switch is an OS switch.
It is composed of a parallel circuit of the MOS transistor PM1 and an inverter gate 40. When the signal of the gate electrode 38 is at "H" level, it is turned on to transmit the signal of the input terminal 37 to the output terminal 39, and when it is "L". Is an off state.

Next, the operation of the embodiment shown in FIG. 1 will be described. In the following description, the upper 5 bits of the successive approximation operation will be described first, and then the lower 3 bits of the successive approximation operation will be described.

During the initial high-order 5 bit successive approximation operation,
The output control signals DCK22, DCK32, DCK42 are kept at "H". Therefore, the CMOS switch C
Since M22, CM32, and CM42 are turned on, the voltage of the voltage dividing terminal 16 of the resistance ladder circuit 32 is output to the terminals 101, 102, and 103. Here, it is assumed that CMOS switches not particularly mentioned are in the off state. In addition, the other side of the sampling capacitor C1 (right end of the figure)
The voltage of the terminal 35 in the sampling period is V _SA ,
The voltage during the comparison period described later is V _CO .

First, the sampling clock SCK is set to "H" to turn on the CMOS switches CM1 and CM3, and one terminal (the left end in the figure) of the sampling capacitor C1 is connected to the analog unknown input V _IN. Input V _IN
Charge with the voltage of (sampling period). At this time, since the input / output terminal of the inverter gate 34 is short-circuited by the CMOS switch CM3, the voltage V _SA 1 of the terminal 35
Is fixed to a constant bias voltage VB. Next, the comparison clock RCK is set to “H” (sampling clock SCK =
"L") and turn on CM2, and sampling capacity C
The comparison operation is performed by transmitting the D / A conversion circuit output V _DA to one terminal of 1 (comparison period). At this time, the voltage V _CO of the terminal 35 changes as expressed by the following equation since the charge amount of the sampling capacitor C1 does not change from the sampling period to the comparison period. Change in _{V CO -V SA = C1 (V} DA -V IN) / (C1 + C2 + C3 + C4) ...... ...... (1) The voltage V _CO is amplified by multistage inverter gate (only the first-stage inverter gates 34), the last stage The logic amplitude is determined at the inverter gate output terminal (not shown). At this time, the resistance ladder circuit side terminals 101, 102, and 103 of the capacitors C2, C3, and C4 are kept at a constant voltage during the high-order 5-bit successive approximation mode, and therefore do not affect the comparison result.

The same sampling / comparison operation is repeated 5 times in total by changing the addresses A3 to A7 in accordance with the successive approximation sequence to obtain the A / D result of the upper 5 bits. Then, this result is reflected in the addresses A3 to A7 after the end of the fifth sampling / comparison operation.

Next, the (second) successive approximation operation of the lower 3 bits is performed. During the 3-bit successive approximation operation, the upper addresses A3 to A7 are fixed to the final result and the sampling / comparison operation is performed. Then, as in the case of the higher-order 5-bit successive approximation operation, in the sampling period,
The CMOS switches CM22, CM32, and CM42 in the second switch decoder circuit 50 are turned on, and the capacitors C2, C3, and C4 have the voltage V of the voltage dividing terminal 16 in common.
d1 is transmitted.

For example, in the case of the comparison period of the third least significant bit, after performing the same sampling operation as above, C
The MOS switches CM2 and CM21 (or CM23, which is determined by the successive comparison result of the 5th bit from the most significant bit of the previous time) are turned on, and the capacitors C1 and C2 have the D / A conversion circuit output V _DA and the output V _DA , respectively. Terminal 20 (or terminal 1
Apply the divided voltage of 2). However, the capacitors C3 and C4 remain at the same voltage at the terminal 16.

Here, the terminal 3 in the sampling period
The voltage of 5 is V _SA (= VB), and terminal 3 in the comparison period
Each V _CO a voltage of 5,101,102,103, Vd
2, Vd3, Vd4, the voltage change V _{CO of the} terminal 35
−V _SA is expressed by the following equation.

V _CO −V _SA = C1 (V _DA −V _IN ) / ΣCi + C2 (Vd2-Vd1) / ΣCi + C3 (Vd3-Vd1) / ΣCi + C4 (Vd4-Vd1) / ΣCi ...... (2) Here, if C1 = C and C2 = C3 = C4 = C / 8, the voltage change V _CO −V _SA is expressed by the following equation.

V _CO −V _SA = (8/11) {(V _DA −V _IN ) + (Vd2-Vd1) / 8 + (Vd3-Vd1) / 8 + (Vd4-Vd1) / 8} ... (3) There is a potential difference of + 4V _LSB and -4V _LSB (V _LSB is a resolution voltage of 5 bits) between the terminals 16 and 20 and between the terminals 16 and 12, respectively.
Since there is a potential difference of + 2V _LSB and -2V _LSB between terminals 14 and 14, and a potential difference of + V _LSB and -V _LSB between terminals 16 and 17 and between terminals 16 and 15, respectively,
The second term of (3) is a weight of ± V _LSB / 2, and the third term is ± V _LSB.
The fourth term has a weight of / 4, and the fourth term has a weight of ± V _LSB / 8, which change, and the successive approximation operation is performed. It should be noted that in the comparison period, the third and fourth terms in the equation (3) are “0”, which means that only the first and second terms are calculated.

Like the normal successive approximation operation, this successive approximation operation appropriately outputs the output control signal DCK2 according to the change of the addresses A0 to A2 according to the comparison result of the comparator.
1, DCK22, DCK23, DCK31, DCK3
2, DCK33, DCK41, DCK42, DCK43
Is performed by changing the. By repeating such a sampling / comparing operation three times, the logical value of the lower 3 bits is determined and the 8-bit A / D conversion operation is completed.

Therefore, according to the embodiment of FIG. 1, when the resolution is 8 bits, 32 resistance elements, 4 capacitors, and a small selection switch are sufficient, and as a result, the accuracy is lowered. And can be sufficiently miniaturized. Further, according to this embodiment, since the weighting capacitors may have two types of capacitance of 1: 8, there is a feature that the configuration is simple.

Although the above embodiments have been described by exemplifying the case of the A / D converter having a resolution of 8 bits, it is not necessary to limit the resolution to 8 bits and the present invention can be applied to any number of bits. It is clear that The configuration of the voltage dividing terminal of the resistance ladder circuit and the weighting capacitor is not limited to this embodiment. For example, the voltage between the adjacent voltage dividing terminals of the resistance ladder circuit 32 is extracted and C1: C2: C3: C4. It is obvious that the voltage may be divided by a capacity ratio of 1: 2: 4: 8.

Further, when configured as an LSI chip, it is not limited to a dedicated LSI having only an A / D converter function, including the embodiments described below, but an A / D converter
One-chip microcomputer L equipped with a D converter
It may be SI.

Next, another embodiment of the present invention will be described. FIG. 3 shows a second embodiment of the present invention. Including this embodiment, hereinafter, the same thing as the above-mentioned case or the equivalent is as follows.
It shall be represented by the same symbol. The embodiment of FIG. 3 corresponds to claim 4 of the claims, and is a reference voltage source.
(Not shown), a first 5-bit resistance ladder circuit 32 and a first switch decoder circuit 33 which form a first D / A conversion circuit, and a second D / A conversion circuit which forms a second D / A conversion circuit. The 3-bit resistance ladder circuit 53, the second switch decoder circuit 50, the sampling capacitor C1, and the weighting capacitors C2 and CMO designed to have a capacitance value of 1/8 of the capacitance C1.
It is composed of S switches CM1 to CM4 and a non-inverting differential amplifier 54.

The first 5-bit resistance ladder circuit 32 has equal resistance elements R1 to R30 each having a unit resistance R.
And a resistance element R whose resistance values are R / 2 and 3R / 2, respectively.
0, R31. However, the resistance element R8 is composed of four unit resistors. The second 3-bit resistance ladder circuit 53 includes six equal resistance elements R201 to R206 and resistance elements R200 having resistance values of R / 2 and 3R / 2, respectively.
It is composed of R207.

The first switch decoder circuit 33 and the second switch decoder circuit 50 are shown in FIG.
It may be a tree-like switch circuit as shown in FIG. 5, a matrix-like switch circuit, or a circuit including an address decoder and a voltage dividing terminal selecting MOS switch group.

In this embodiment, two series circuits composed of two unit resistors are connected in parallel to form the resistance element R8, and the intermediate terminal of the series circuit is the non-inverting terminal 36 of the differential amplifier 54. Therefore, the voltage of the non-inverting terminal (voltage dividing terminal) 36 is the voltage V _REF / 4 (V _REF is the first reference voltage value) corresponding to the voltage across the resistance terminals of 8R. ).

Accordingly, the output voltage value of the differential amplifier 54, that is, the second reference voltage value V _REF2 becomes approximately V _REF / 4, and the 3-bit voltage dividing terminal voltage by the second resistance ladder circuit 53 becomes the second voltage. It is transmitted to the capacitor C2 via the switch decoder circuit 50. As described above, this capacity C
The capacitance value of 2 is set to 1/8 of the capacitance C1.

Next, the operation of the embodiment of FIG. 3 will be described. Since the operation of this embodiment is basically the same as that of the embodiment of FIG. 1, only the characteristic points of this embodiment will be described below.

In the sampling period, the sampling clock SCK and the comparison clock RCK both become "H", and the CMOS switches CM1, CM3, CM4 are in the ON state. At this time, the address signals A0 to A2 are all "0", and therefore the terminal voltage GND (ground) is output from the output terminal 51 of the second switch decoder circuit 50.

Then, in the first comparison period in the successive approximation operation of the lower 3 bits, (A2, A1, A0) = (1,
0, 0), and therefore the second switch decoder circuit 50 divides the divided voltage 44 at the midpoint of the second resistance ladder circuit 53.
(Not shown) is transmitted to the other end of the capacitor C2 via the CMOS switch CM4.

At this time, the voltage change of the terminal 35 V _CO -V _SA
Is expressed by the following equation, as is clear from equations (2) and (3). V _CO −V _SA = (8/9) [{(V _DA + V _REF * d / (2 ³ * 2 ² )} − V _IN ) ... (4) where d is the second ladder resistance circuit. It represents the voltage division ratio (output coefficient), and varies in units of 1/2 ³ .

The sum of the first and second terms of this equation becomes the output voltage value of the D / A conversion circuit, which is the minimum of 1/2 ⁵ and 1/2 ⁸ with respect to the reference voltage value V _REF . It changes with the resolution, and successive comparison with the input voltage V _IN is performed.

Therefore, according to this embodiment, in addition to being able to reduce the circuit scale, since the resistance ladder circuit is buffered by the differential amplifier, the resistance value can be set independently and freely. is there.

Next, FIG. 4 shows a third embodiment of the present invention. The embodiment of FIG. 4 corresponds to claim 3 of the claims, and the first D / A conversion circuit constitutes the first embodiment.
Resistance ladder circuit 32 and first switch decoder circuit 3
3. Second resistance ladder circuit 53 and second switch decoder circuit 50, which form a second D / A conversion circuit, CMOS
It is composed of switches CM1 to CM4, a sampling capacitor C1, a weighting capacitor C5 having a capacitance value of ¼ of this capacitor C1, and a logic inverter gate 34. Note that configurations that are not particularly referred to are the same as or equivalent to those described above, and therefore will not be described.

The second resistance ladder circuit 53 is composed of a series resistance circuit of nine resistance elements RT0 to RT8.
The second switch decoder circuit 50 is shown in FIG. 5, and as shown in the drawing, the NMOS transistors NM2 to NM2.
NM10 and an address decoder circuit 52, and selects one of the voltage dividing terminals 41 to 49 of the second resistance ladder circuit 53 according to the combination of the address signals A0, A1 and A2. It is output from the output terminal 51.

In the embodiment shown in FIG. 4, the first ladder resistance circuit 32 is provided with a voltage dividing resistor composed of resistance elements R1 to R4 having a resistance value 2R and a resistance element R0 having a unit resistance value R in the lower bit. And a resistance element RT0 having a unit resistance value R0
Using the second ladder resistance circuit 53 composed of RT8,
The second ladder resistor circuit 53 is connected in parallel to the voltage dividing resistors of the lower bits of the ladder resistor circuit 32, and the voltage dividing terminals 1 to 5 of the first resistor ladder circuit 32 are thereby formed.
Is to generate a voltage in units of resolution of upper 5 bits without being affected by the connection of the second resistance ladder circuit 53. voltage terminal 41 to 49, if the resolution voltage of the upper 5 bits and V _LSB, is obtained to be able to generate a potential difference V _LSB / 2 units.

Here, the output terminal 51 remains at the potential of the voltage dividing terminal 45 during the successive comparison operation of the upper 5 bits.
(Address signals A2, A1, A0 = 1, 0, 0) Since this is the same as the above description, the successive approximation operation of the lower 3 bits will be described below. During the successive approximation operation of the lower 3 bits, the addresses A3 to A7 are fixed to the address value reflecting the A / D conversion result of the upper 5 bits. For example, in the successive comparison of the third least significant bit, the sampling period (SCK = “H”, RCK =
For “L” and RCK2 = “H”), the central voltage dividing point 45 is selected in the same manner as above.

Next, the comparison period (SCK = "L", RCK
= “H”, RCK2 = “H”), the voltage dividing terminal 49 (address signals A2, A1, A0
= 1, 1, 1), or the voltage dividing terminal 41 (address signal A2,
A1, A0 = 0, 0, 0) is selected. At this time, the terminal 3 is divided by the voltage division of the resistance ladder circuit 50 and the capacitance C5.
A fluctuation of ± V _LSB / 2 appears at 5, and the comparison operation is performed.

In the comparison period of the second least significant bit, the voltage dividing terminal 47 (or the voltage dividing terminal 43) is selected and + V _LSB / 4
(Or −V _LSB / 4) fluctuation appears, and when the least significant bit is compared, the voltage dividing terminal 46 (or the voltage dividing terminal 44) is selected, and +
Fluctuation of V _LSB / 8 (or -V _LSB / 8) appears. Therefore,
These fluctuations are added to the D / A conversion circuit output V _DA ,
The A / D conversion operation will be obtained by comparison with the unknown input signal voltage V _IN .

Therefore, according to the embodiment of FIG. 4, in the case of the 8-bit A / D converter, the number of unit resistors (resistance value R) is 36 for the first ladder resistor and the second ladder resistor. 9 with resistance
A total of 45, that is, two capacitors are required. Further, since it can be configured only by the combination of the same unit resistance, there is a feature that the error fluctuation of the voltage dividing terminal can be reduced. It should be noted that this can be applied to other embodiments, but since resistors of the same shape can be repeatedly arranged in the layout of an IC (semiconductor integrated circuit device), variations in resistance and resistance ratio This is because the fluctuation of

Next, FIG. 6 shows the second ladder resistance circuit 50 and the first ladder resistance circuit 32 in the embodiment of FIG.
It corresponds to claim 5 of the scope of the invention in one embodiment in the case of parallel connection to the central part of
Since the operation is the same as that of the embodiment shown in FIG.
Then, only the first and second resistance ladder circuits are shown.

Therefore, in the case of this embodiment, in addition to the effect of the embodiment of FIG.
Since it can be provided in the central portion where there is little variation in resistance, there is a feature that accuracy can be sufficiently improved. This is because in an IC, a resistance ladder circuit is usually generated by diffusion layer resistance, polysilicon resistance, etc., and has uneven resistance due to non-uniformity of characteristics and distortion on the chip surface. Because it is often done.

Further, another embodiment according to the present invention is shown in FIG. The embodiment of FIG. 7 is defined in claim 2 of the claims.
In the embodiment of FIG. 4, the second resistance ladder circuit 53 is directly connected to the voltage dividing terminal 2 of the first resistance ladder circuit 32. , CMOS switches CM5 to CM7 and sampling capacitors C1 with capacitance values of 1 and 1 respectively.
The capacitors C6, C7, and C8 having the weights of / 2 and 1/4 are provided. Therefore, in this embodiment, the ladder resistance circuit in which the ground side is seen from the voltage dividing terminal 2 is a parallel circuit having a resistance value of 3R. The result is that the terminals 71 and 7 are formed.
The voltage between 2 and the voltage between terminals 71 and 70 are +
It becomes V _LSB / 2 and -V _LSB / 2.

In addition, the second switch decoder circuit 50
Is composed of nine NMOS transistors NM11 to NM19 and an address decoder 69, and the lower address signal A
Depending on the combination of 0 to A2, the output signal group 73 from the address decoder 69 is transferred to the NMOS transistor NM11.
~ Input to the gate of NM19, which turns on any three sets of NMOS switches. Then, during the sampling period, the NMOS transistors NM12 and NM1
5, the MN 18 is turned on, and the voltage of the voltage dividing terminal 71 is output from the output terminals 101, 102 and 103.

By the way, in this embodiment as well, the successive approximation operation of the upper 5 bits is the same as that in each of the above-mentioned embodiments.
The successive approximation operation of the lower 3 bits will be described below.
During the comparison period, the voltage dividing terminal 72,
Alternatively, the voltage dividing terminal 70 is selectively output, divided by the weighting capacitor, and the successive comparison operation with the input voltage V _IN is performed. That is, the voltage V _LSB / 2 generated by the second resistance ladder circuit 53 is set to the weighting capacitors C6, C7, C8.
Divided by ± V _LSB / 2, ± V _LSB / 4,
It is transmitted to the terminal 35 with a resolution of ± V _LSB / 8.

Therefore, according to this embodiment, the unit resistance is
Since the number of (resistance value R) is 36 and the number of capacitive elements is 4 (in the case of 8 bits), miniaturization can be sufficiently achieved.

Next, FIG. 8 shows still another embodiment of the present invention, which corresponds to claim 6 of the claims. In the embodiment of FIG. The second reference voltage trimming circuit is added.

What is particularly noteworthy in this embodiment is the non-inverting type differential amplifier 76, the second resistance ladder circuit 53, the second switch decoder circuit 50, the third switch decoder circuit 74, and the selection CMOS. Switch CM8, C
M9, sampling capacitor C1, weighting capacitor C9
It is a configuration including each part of.

First, in the second resistance ladder circuit 53, four resistor strings (resistance value 4R) each consisting of four unit resistors are connected in parallel in the vicinity of the intermediate voltage dividing terminal, and a voltage dividing voltage terminal for trimming is connected. 78 to 82 are obtained, whereby the second reference voltage V is output as the voltage of the output terminal 77.
_The voltage trimmed with an accuracy of 1/8 × 1/4 = 1/32 with respect to _REF2 can be taken out.

Next, negative feedback acts on the differential amplifier 76 via the second resistance ladder circuit 53 and the third switch decoder circuit 74, whereby the voltage at the terminal 77 is applied. , And is controlled to be equal to the voltage value of the voltage dividing terminal 1 of the first resistance ladder circuit 32.

Here, as described above, the second reference voltage V _REF2 can be adjusted by the trimming address signal 75, which allows the voltage V _{REF2 to} have a desired second reference voltage value. Is set to.
The trimming operation using the address signal 75 is
This is done while externally monitoring the voltage V _REF2 at the terminal 77.

In the successive approximation operation of the lower 3 bits, the sampling period is clock DCK1 = "H" and CMO
The S switch CM9 is turned on, and the D / A of the capacitor C9
The terminal on the conversion circuit side is fixed to the ground potential. Next, in the comparison period, the clock DCK2 = “H”, RCK = “H”
Then, the CMOS switches CM2 and CM8 are turned on to perform the comparison operation. Since the other operations are the same as those of the embodiment shown in FIG. 3, the description thereof will be omitted.

According to this embodiment, the number of elements is small, and the second reference voltage is externally trimmed, so that high accuracy can be easily obtained. Further, in this embodiment, the variable resistance for trimming also serves as the second resistance ladder circuit, so that miniaturization can be obtained.

In the above embodiment, it is clear that the parallel circuit of the unit resistor string may be connected to the corresponding voltage dividing terminals of each parallel circuit (the equivalent voltage dividing ratio does not change).

By the way, according to the present invention, as is clear from the above embodiments, a highly accurate and compact A / D converter can be easily obtained. On the other hand, a microcomputer often requires an A / D converter for its use. Therefore, if the A / D converter according to the present invention is mounted on the same LSI as the microcomputer, a compact and high-performance microcomputer can be easily obtained.

[0066]

According to the present invention, the number of resistor ladders and weighting capacitors can be suppressed without degrading accuracy, so that the circuit scale can be reduced, and therefore,
When integrated into an IC, the area occupied by the A / D converter module can be reduced, and the number of chips to be acquired can be increased, so that a highly accurate A / D converter can be provided at low cost.

Further, according to the present invention, since the resistance ladder can be constructed by the repeated layout of unit equal resistance, high accuracy can be easily obtained.

Further, according to the present invention, since the trimming can be arbitrarily performed, a highly accurate A / D converter can be easily realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of an A / D converter according to the present invention.

FIG. 2 is a circuit diagram showing an example of a switch decoder circuit according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of an A / D converter showing a second embodiment of the A / D converter according to the present invention.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the A / D converter according to the present invention.

FIG. 5 is a circuit diagram showing another example of the switch decoder circuit in the embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a fourth embodiment of an A / D converter according to the present invention.

FIG. 7 is a circuit configuration diagram showing a fifth embodiment of an A / D converter according to the present invention.

FIG. 8 is a circuit configuration diagram showing a sixth embodiment of an A / D converter according to the present invention.

FIG. 9 is a circuit configuration diagram showing a conventional example of an A / D converter.

[Explanation of symbols]

32 1st resistance ladder circuit 33 1st switch decoder circuit 34 Inverter gate 50 2nd switch decoder circuit 53 2nd resistance ladder circuit 54,76 Non-inverting type differential amplifier 74 3rd switch decoder circuit CM1-CM9 , CM21, CM22, CM23, CM
31, CM32, CM33, CM41, CM42, CM
43 CMOS switches C1 to C9 ... Capacitance elements (capacitors) R0 to R31 Resistance elements configuring a first resistance ladder circuit R200 to R207, RT0 to RT11 ... Resistance elements configuring a second resistance ladder circuit NM1 to NM19 NMOS switch PM1 PMOS switch

Claims (7)

[Claims] 1. A comparison voltage generation circuit, and a comparator having an output of the comparison voltage generation circuit and an analog input voltage as one input and the other input, respectively, and the output of the comparison voltage generation circuit according to the output of the comparator. In the successive approximation type analog-to-digital converter of the method of sequentially switching the voltage, the comparison voltage generation circuit includes a resistance voltage dividing circuit that divides a reference voltage to generate a plurality of divided voltages, and a voltage dividing circuit for the resistance voltage dividing circuit. A first switch decoder circuit for selecting and outputting a piezo-voltage according to the output of the comparator; a sampling capacitor element connected between the output of the first switch decoder circuit and one input of the comparator; A second switch decoder circuit for selecting and outputting the divided voltage of the resistance voltage dividing circuit according to the output of the comparator; and the second switch decoder. And a weighting capacitance element group for adding / subtracting the output of the sampling circuit to the voltage of the sampling capacitance element, and a successive approximation operation of the upper bit group using the output voltage of the first switch decoder circuit as a comparison voltage; The output voltage of the switch decoder circuit is configured to sequentially perform the successive approximation operation of the lower bit group using the voltage obtained by adding and subtracting the output voltage of the first switch decoder circuit via the weighted capacitive element group as the comparison voltage. An analog-to-digital converter characterized by. 2. A comparison voltage generation circuit, and a comparator having an output of the comparison voltage generation circuit and an analog input voltage as one input and the other input, respectively, and the output of the comparison voltage generation circuit according to the output of the comparator. In a successive approximation type analog-to-digital converter of a method of sequentially switching voltages, the comparison voltage generation circuit includes an equal resistance voltage dividing circuit that divides a reference voltage to generate a plurality of divided voltages, and the equal resistance voltage dividing circuit. A first switch decoder circuit that selects and outputs the divided voltage of the switch according to the output of the comparator, and a sampling capacitor element that is connected between the output of the first switch decoder circuit and one input of the comparator. A resistor ladder circuit that further divides a part of the divided voltage of the equal resistance voltage divider circuit, and the divided voltage of the resistor ladder circuit according to the output of the comparator. A second switch decoder circuit that selects and outputs the same, and a weighting capacitive element group that adds and subtracts the output of the second switch decoder circuit to and from the voltage of the sampling capacitive element. The successive comparison operation of the upper bit group using the output voltage as the comparison voltage is compared with the voltage obtained by adding or subtracting the output voltage of the second switch decoder circuit to the output voltage of the first switch decoder circuit via the weighting capacitive element group. An analog-digital converter characterized in that it is configured to sequentially perform a successive approximation operation of a lower-order bit group used as a voltage. 3. A comparison voltage generation circuit, and a comparator having an output and an analog input voltage of the comparison voltage generation circuit as one input and the other input, respectively, and the output of the comparison voltage generation circuit according to the output of the comparator. In the successive approximation type analog-to-digital converter of the method of sequentially switching between, the comparison voltage generating circuit includes a first resistance voltage dividing circuit that divides a reference voltage to generate a plurality of divided voltages, and the first resistance dividing circuit. A first switch decoder circuit for selecting and outputting a first divided voltage of the voltage dividing circuit according to the output of the comparator, and a part of the divided voltage of the first resistance voltage dividing circuit as a second reference. A second resistance voltage dividing circuit for generating a plurality of second voltage divided voltages by dividing this second reference voltage, and the voltage divided by the second resistance voltage dividing circuit as the output of the comparator. Select and output according to Composed of a second switch decoder circuit, the successive comparison operation of the upper bit group that comparison voltage the output voltage of the first switching decoder circuit, the first
And an output voltage of the second voltage divider circuit is added to or subtracted from the output voltage of the switch decoder circuit of FIG. Digital converter. 4. The invention according to claim 3, wherein the second reference voltage is supplied from a part of the divided voltage of the first resistance voltage dividing circuit through a buffer amplifier to the second resistance voltage dividing circuit. An analog-to-digital converter characterized in that it is configured to be supplied to. 5. The second reference voltage according to claim 3, wherein the second reference voltage is applied to two voltage dividing terminals on both sides in the vicinity of a central portion of the first resistance voltage dividing circuit. An analog-digital converter characterized in that it is configured to be supplied to the second resistance voltage dividing circuit by connecting both terminals of the circuit in parallel. 6. The invention according to claim 3, wherein the second reference voltage is applied to the first reference voltage via one input of a differential amplifier.
A part of the divided voltage of the resistance voltage dividing circuit is supplied to the second resistance voltage dividing circuit, and the trimming voltage is supplied to the other input of the differential amplifier. And analog-digital converter. 7. A microcomputer comprising the analog-digital converter according to claim 1.