JP3971663B2 - AD converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to an AD converter that converts an analog signal into a digital signal, and more particularly relates to a successive approximation AD converter that converts an analog signal into a digital signal by a successive approximation operation.
[Prior art]
The successive approximation AD converter is realized with a relatively simple circuit configuration, has high compatibility with a CMOS process, can be manufactured at a relatively low cost, and can achieve a relatively fast conversion time. Of the successive approximation AD converters, the double stage type can realize a high-resolution AD converter with a small mounting area.
[0002]
The double-stage successive approximation AD converter includes a main DAC (DA converter) for determining the maximum bit (MSB) side and a sub DAC (DA converter) for determining the minimum bit (LSB) side. And a two-stage configuration. First, the upper bit is determined by comparing the analog potential set by the main DAC (DA converter) with the input analog potential. The analog potential of the main DAC corresponding to the determined upper bit and the analog potential set by the sub DAC are added, and the lower bit is determined by comparing this sum with the input analog potential.
[0003]
The DAC constituting the main DAC or the sub DAC can be realized by a resistor string or a capacitor array. Depending on which type is used for the main DAC and the sub DAC,
(1) Capacity array + capacitance array type (hereinafter referred to as C-C type),
(2) Resistor string + capacitance array type (hereinafter R-C type),
(3) Capacitance array + resistance string type (hereinafter referred to as C-R type),
(4) Resistor string + resistor string type (hereinafter referred to as RR type),
There are four types.
[0004]
FIG. 1 is a circuit diagram of a successive approximation AD converter using a conventional CR double stage DAC.
[0005]
1 includes an input terminal 10 to which an input potential Vin is applied, nodes 20 to 23, nodes 40 to 44, a switch circuit 100, a switch circuit 200, a switch circuit 201, a switch circuit 202, a comparator 300, A successive approximation control circuit 301, resistors R1 to R16, and capacitors C1 to C5 are included. The successive approximation control circuit 301 controls operations of the switch circuits 100, 200, 201, 202, and the like.
[0006]
R1 to R16 and the switch circuit 100 constitute a 4-bit sub DAC, and C1 to C5 and the switch circuit 200 (and 201 and 202) constitute a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted with C3 being 2Cx, C4 being 4Cx, and C5 being 8Cx, where C1 and C2 have capacitance values of Cx, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and charged to the input potential Vin. At this time, the switch 202 is controlled so that the node 20 becomes GND. In order to ensure relative accuracy, the sampling capacitors C3 to C5 are generally realized by connecting, for example, two, four, or eight unit capacitors Cx in parallel.
[0007]
After completion of sampling, a comparison operation is started, and digital data corresponding to the input potential Vin is determined in order from the MSB. Specifically, the switch 202 is opened to bring the node 20 into a floating state. For example, the nodes 40 to 43 are connected to GND via the switches 200 and 201, and the node 44 is connected to the reference potential Vref (terminal 1). . With this connection, the charge stored by the input potential Vin during sampling is redistributed between the sampling capacitors C1 to C5, and the potential of the node 20 becomes Vref / 2−Vin. The node 20 is connected to the input of the comparator 300, and it can be determined from the potential of the node 22 that is the output of the comparator 300 whether the analog input potential Vin is larger or smaller than ½ of the reference potential Vref.
[0008]
In the above connection, the node 44 is connected to the reference potential Vref, and the other nodes 40 to 43 are connected to GND. That is, 8Cx of C5 was connected to the reference potential Vref, and a total of 8Cx of the remaining C1 to C4 was connected to GND. Generally, if the number of unit capacitors Cx connected to the reference potential Vref is m and the number of remaining unit capacitors Cx connected to GND is 16-m, the potential V of the node 20 is
V = (m / 16) Vref−Vin
It becomes. For example, when the node 41 is connected to Vref and the remaining nodes 40, 42, 43, and 44 are connected to GND, since m is 1, the potential of the node 20 becomes Vref / 16−Vin.
[0009]
Accordingly, by sequentially changing m, the potential of the node 20 can be changed in increments of Vref / 16, and the MSB side (upper 4 bits) of the digital data can be determined.
[0010]
Next, m determined as described above is m ′, m ′ unit capacitors Cx among C2 to C5 are connected to the reference potential Vref, and the remaining 15-m ′ among C2 to C5 is connected. The unit capacitors Cx are connected to GND, and the node 40 of one unit capacitor Cx of C1 is connected to the sub DAC (R1 to R16 and the switch circuit 100). By changing the potential of the node 40 in increments of Vref / 16 by the sub DAC, the potential of the comparator input 20 can be changed in increments of Vref / 256. As a result, the LSB side (lower 4 bits) of the digital data can be determined, and a total of 8 bits of digital data can be obtained.
[0011]
In the circuit of FIG. 1, AD conversion with 8-bit accuracy is realized by preparing 16 unit capacitors Cx and 16 unit resistors. If a single-stage 8-bit precision DAC is to be made with only a capacitor or a resistor, 256 unit capacitors or 256 unit resistors are required. By using a double stage DAC as in the circuit of FIG. 1, the number of components can be greatly reduced. In the circuit of FIG. 1, the accuracy of the resistance of the 4-bit sub DAC may be about 4 bits, and the resistance sub DAC can be realized with a small area.
[Problems to be solved by the invention]
In recent years, there has been an increasing demand for higher speed AD converters, and it is strongly desired to increase the speed of successive approximation AD converters that can form circuits with a small area.
[0012]
A first object of the present invention is to provide a circuit that shortens the AD conversion processing time of a successive approximation AD converter.
[0013]
Further, in the conventional circuit shown in FIG. 1, when the potential of the node 23 that is the output of the sub DAC (R1 to R16 and the switch circuit 100) is set to, for example, Vref / 2, there is a problem that switching is slow. . This is because the switch circuit is generally realized by a CMOS transfer gate. Therefore, when the power supply voltage (Vref) is low, the ON resistance of both PMOS and NMOS becomes higher than the source / drain voltage of Vref / 2. This is because the delay time at 100 increases.
[0014]
Therefore, a second object of the present invention is to provide a circuit in which the delay time in the resistor DAC does not increase even when the power supply voltage is low.
[Means for Solving the Problems]
The successive approximation AD converter according to the present invention includes a capacitor array including a plurality of capacitors that sample the input potential and store charges. Thus, the first reference potential and the second reference potential are selectively applied to the capacitor array. An L-bit capacitive DA converter, a first M-bit resistive DA converter that generates a desired potential by potential division, and a second N-bit resistive DA converter that generates a desired potential by potential division; A first signal path for adding the output of the first M-bit resistive DA converter to the output of the L-bit capacitive DA converter by capacitive coupling, and the second N-bit resistive DA converter In the successive approximation AD converter having a resolution of (L + M + N) bits, including a second signal path for adding the output to the output of the L-bit capacitive DA converter by capacitive coupling and a comparator, the L-bit capacitance The type DA converter corresponds to the L bit from the most significant bit among all the bits to be AD converted, and the first M-bit resistance type DA converter corresponds to the M bit following the L bit. 2 N-bit resistor type DA converter Corresponding to the N bits following the M bit, the first M-bit resistive DA converter and the second N-bit resistive DA converter share a resistor string for potential division, and the first The M-bit resistive DA converter and the second N-bit resistive DA converter include a total of 2 (M + N) power resistive elements. Thus, the first M-bit resistive DA converter and the second N-bit resistive DA converter divide the first reference potential and the second reference potential by a resistor string, and Of the range from one reference potential to the second reference potential, the output of the first M-bit resistive DA converter and the second only in either the upper half or the lower half of the range There is an output of N-bit resistive DA converter It is characterized by that.
[0015]
In the above configuration, for example, in the case of 8-bit AD conversion, the first resistive DA converter and the switch circuit of the sub DAC of the conventional circuit are compared with the 16: 1 selector that determines the lower 4 bits. The switch circuit of the second resistance type DA converter may be a 4: 1 selector that determines 2 bits, and the scale of the switch circuit can be greatly reduced. In the switch circuit, the junction capacitance of the MOS transfer gate that constitutes the switch acts as a parasitic capacitance and causes a delay in signal change, so that the time required for the AD conversion comparison process increases. In the configuration of the present invention, since the switch circuit of the first resistance type DA converter and the second resistance type DA converter can be made small, the parasitic capacitance is greatly reduced, and the time required for the comparison processing is reduced. Can be shortened.
[0016]
Further, in order to reduce the sampling time, even when the number of bits of the capacitor DAC is reduced and the number of bits of the resistor DAC is increased, an increase in delay time in the resistor DAC can be suppressed. Therefore, the sampling time can be reduced without substantially increasing the comparison time in the conversion time of the AD converter, and the conversion time can be increased.
[0018]
In this configuration, for example, in the case of a resistor string that divides Vref into 16, by setting the output of the first resistor type DA converter to the highest possible voltage range such as 12 Vref / 16 to 15 Vref / 16, the resistance type The switch circuit of the DA converter can be used in a region where the ON resistance is small. In the PMOS and NMOS transfer gates, the ON resistance becomes large at a voltage near ½ of the power supply voltage (Vref) and high speed operation becomes difficult. However, the delay time is reduced by using a voltage close to the power supply voltage (Vref). Thus, the conversion process can be speeded up.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0019]
FIG. 2 is a circuit diagram showing a first embodiment of a successive approximation AD converter according to the present invention. In FIG. 2, the same elements as those of FIG. 1 are referred to by the same numerals.
[0020]
2 includes an input terminal 10 to which an input potential Vin is applied, nodes 20 to 23, nodes 40 to 45, a switch circuit 101, a switch circuit 102, a switch circuit 200, a switch circuit 201, and a switch circuit 202. , A comparator 300, a successive approximation control circuit 302, resistors R1 to R16, and capacitors C1 to C6. The successive approximation control circuit 302 controls the operations of the switch circuits 101, 102, 200, 201, 202, and the like.
[0021]
Resistors R1 to R16, switch circuits 101 and 102, and capacitor C6 constitute a sub DAC, and C1 to C5 and switch circuits 200 (and 201, 202) constitute a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted with C3 being 2Cx, C4 being 4Cx, and C5 being 8Cx, where C1 and C2 have capacitance values of Cx, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and charged to the input potential Vin. At this time, the switch 202 is controlled so that the node 20 becomes GND. In order to ensure relative accuracy, the sampling capacitors C3 to C5 are generally realized by connecting, for example, two, four, or eight unit capacitors Cx in parallel.
[0022]
After completion of sampling, a comparison operation is started, and digital data corresponding to the input potential Vin is determined in order from the MSB. Specifically, the switch 202 is opened to bring the node 20 into a floating state. For example, the nodes 40 to 43 are connected to GND via the switches 200 and 201, and the node 44 is connected to the reference potential Vref (terminal 1). . The node 45 is connected to GND by the switch circuit 102. With this connection, the charge stored by the input potential Vin at the time of sampling is redistributed among the sampling capacitors C1 to C5, and the potential of the node 20 becomes a potential proportional to Vref / 2−Vin. The node 20 is connected to the input of the comparator 300, and it can be determined from the potential of the node 22 that is the output of the comparator 300 whether the analog input potential Vin is larger or smaller than ½ of the reference potential Vref.
[0023]
In the above connection, for the sampling capacitors C1 to C5, the node 44 is connected to the reference potential Vref, and the other nodes 40 to 43 are connected to GND. That is, 8Cx of C5 was connected to the reference potential Vref, and a total of 8Cx of the remaining C1 to C4 was connected to GND. Generally, if the number of unit capacitors Cx connected to the reference potential Vref is m and the number of remaining unit capacitors Cx connected to GND is 16-m, the potential V of the node 20 is
V = (16/17) [(m / 16) Vref−Vin] (1)
It becomes. For example, when the node 41 is connected to Vref and the remaining nodes 40, 42, 43, and 44 are connected to GND, the potential of the node 20 is (16/17) [Vref / 16-Vin] because m is 1. It becomes. Note that the coefficient (16/17) in the above equation takes into account the influence of the capacitor C6 that is not used as a sampling capacitor.
[0024]
By sequentially changing m, the potential of the node 20 can be changed in increments of Vref / 16. Therefore, the MSB side (upper 4 bits) of the digital data can be determined.
[0025]
FIG. 3 is a diagram conceptually showing the configuration and operation of the circuit of FIG.
[0026]
The successive approximation AD converter of FIG. 3 includes a successive approximation control circuit 302, a local DA converter 303, and a comparator 300A. The local DA converter 303 is a combination of the main DAC and the sub DAC of FIG. 2, and generates a voltage in increments of Vref / 256 by an 8-bit DA conversion operation. The successive approximation control circuit 302 controls the operation of the local DA converter 303 by controlling opening and closing of the switch circuit. The comparator 300A compares the voltage generated by the local DA converter 303 with the input voltage Vin to determine the magnitude relationship. In the configuration of FIG. 2, after sampling Vin, the result of subtracting Vin from (m / 16) Vref is supplied to the comparator 300 as an input, but FIG. 3 shows a conceptual configuration as a comparator. The comparison is made by subtracting Vin from (m / 16) Vref by 300A.
[0027]
In the successive approximation AD converter circuit of FIG. 3, the successive approximation control circuit 302 sets digital data, and the local DA converter 303 DA converts the digital data to generate a local analog voltage. The comparator 300A compares and determines the magnitude relationship between the input analog voltage Vin and the local analog voltage of the local DA converter 303, and the successive approximation control circuit 302 controls the local DA converter 303 based on the comparison determination output 22. . As a result, digital data is obtained when the local analog voltage output of the local DA converter 303 is substantially equal to the input analog voltage Vin, and this digital data is used as an AD conversion output. In the comparison operation, each bit of the digital data is determined sequentially from the MSB toward the LSB side.
[0028]
In the following, processing for determining lower bits on the LSB side by the sub DAC will be described.
[0029]
Using the 2-bit resistor DAC (R1 to R16 and the switch circuit 101) at the node 40 of C1 having a capacitance value Cx that is 1/16 of the total sampling capacitance 16Cx of C1 to C5, Vref / 4 Change the potential in increments. Thereby, the potential of the node 20 as the comparator input can be changed in increments of Vref / 64.
[0030]
For example, the capacitance value of the capacitor connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitor connected to GND by the switch circuit 200 is (15−m) Cx. Further, the potential of the node 40 of C1 set by the 2-bit resistor DAC is nVref / 4 (n is 0 to 3). At this time, the potential V of the node 20 determined by charge redistribution is
V = (16/17) [(m / 16 + n / 64) Vref−Vin] (2)
It becomes. In the above equation, it is assumed that the potential of the node 45 is set to GND.
[0031]
Therefore, after determining the value of m corresponding to the upper 4 bits of digital data, the value of V can be changed in increments of 64 by dividing the reference potential Vref, and the value of n can be determined by the comparator 300. That is, 2 bits of data corresponding to n can be determined following the upper 4 bits of digital data.
[0032]
As described above, 6-bit digital data can be obtained from the MSB side.
[0033]
Further, at the node 45 of C6 having a capacitance value Cx that is 1/16 of the total sampling capacitance 16Cx of C1 to C5, Vref is used by using a 2-bit resistor DAC (R1 to R16 and the switch circuit 102). The potential is changed in increments of / 16. Thereby, the potential of the node 20 as the comparator input can be changed in increments of Vref / 256.
[0034]
For example, the capacitance value of the capacitor connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitor connected to GND by the switch circuit 200 is (15−m) Cx. Furthermore, the potential of the node 40 of C1 is nVref / 4 (n is 0 to 3), and the potential of the node 45 of C6 set by the 2-bit resistor DAC is pVref / 16 (p is 0 to 3). At this time, the potential V of the node 20 determined by charge redistribution is
V = (16/17) [(m / 16 + n / 64 + p / 256) Vref−Vin] (3)
It becomes.
[0035]
Therefore, after determining the values of m and n corresponding to the upper 6 bits of digital data, the value of V is changed in increments of 256 by dividing the reference potential Vref, and the value of p can be determined by the comparator 300. it can. That is, 2-bit data corresponding to p can be determined following the upper 6-bit digital data.
[0036]
As described above, all 8-bit digital data can be obtained.
[0037]
FIG. 4 is a diagram showing a configuration of local DA converter 303 in FIG. 3 in order to conceptually explain the operation of the circuit in FIG.
[0038]
The local DA converter 303 in FIG. 3 includes a capacitance array type DA converter 304, a resistance type DA converter 305, and a resistance type DA converter 306.
[0039]
m is the upper 4 bits of the digital data, n is the middle 2 bits of the digital data, and p is the lower 2 bits of the digital data. The capacitor array type DA converter 304 is a capacitor array DAC that converts upper bits in the local DA converter 303, and corresponds to C1 to C5 and the switch circuit 200 (and 201, 202) in FIG. The resistive DA converter 305 is a resistor DAC that converts the middle 2 bits of the local DA converter 303 and corresponds to R1 to R16 and the switch circuit 101 in FIG. The resistance DA converter 306 indicates a resistor DAC that converts the lower 2 bits of the local DA converter 303, and corresponds to R1 to R16 and the switch circuit 102 in FIG. In FIG. 2, C1 is shown as a part of the capacitor array DAC, but in FIG. 4, it is shown separately from the capacitor array DAC.
[0040]
The output of the resistive DA converter 305 is capacitively coupled via C1 to the output of the capacitive array DA converter 304, and the output of the resistive DA converter 306 is capacitively coupled via C6. By capacitively coupling the output of the resistive DA converter 305, the voltage corresponding to the middle bit represented by n can be scaled down and added. Also, by capacitively coupling the output of the resistance DA converter 306, the voltage corresponding to the lower bit represented by p can be scaled down and added.
[0041]
2 and FIG. 4, the configuration in which the output potentials of the two resistors DAC are added to the output potential of the capacitor DAC is shown. However, the number of resistors DAC is not limited to two, and two or more resistors DAC are connected. It is good also as a structure provided with a coupling means. The output potential of the resistor DAC applied to the node 45 of C6 only needs to be changed in increments of Vref / 16 as a relative change from the time of sampling, and the absolute value does not need to be a potential corresponding to R1 to R4.
[0042]
Further, although the capacitor DAC is associated with 4 bits and the resistor DAC is associated with 4 bits, the present invention is not limited to this. For example, the capacitor DAC may be associated with 3 bits and the resistor DAC may be associated with 5 bits.
[0043]
Further, since the switch circuit 100 of the conventional circuit of FIG. 1 is a 16: 1 selector, the switch circuit 101 and 102 in the circuit of the present invention of FIG. It can be greatly reduced.
[0044]
Specifically, the switch circuit is realized by a MOS transfer gate. When the resistor DAC is 4 bits as shown in FIG. 1, the junction capacitance of the MOS transfer gate for 16 taps becomes the parasitic capacitance of the node 23. Due to the influence of this parasitic capacitance, the signal change of the node 23 is delayed, the settling time of the node 20 becomes long, and the time required for the comparison process increases.
[0045]
Since the switch circuits 101 and 102 in FIG. 2 have a small circuit scale, the parasitic capacitances in the nodes 23 and 45 in FIG. 2 are significantly smaller than the parasitic capacitance in the node 23 in FIG. 1, and the time required for the comparison processing is shortened. I can do it.
[0046]
In the successive approximation AD converter, the AD conversion processing time for converting an analog signal into a digital signal is based on the sampling time for storing the analog signal in the sampling capacity and the comparison time for determining the digital value after the sampling is completed. Become. In order to shorten the conversion processing time, the sampling time and the comparison time must be shortened. In order to shorten the sampling time, if the signal source impedance of the external circuit that supplies the analog input signal is constant, it is necessary to reduce the sampling capacitance. However, in order to maintain relative accuracy, the value of the unit capacity cannot be reduced so much, and the sampling capacity can only be reduced by reducing the number of capacitors.
[0047]
In order to reduce the capacitance value of the sampling capacitor, for example, the capacitive main DAC may have a 3-bit configuration and the resistive sub DAC may have a 5-bit configuration. In this case, since the sampling capacity is 8 unit capacity, the capacity value can be halved with respect to the original total sampling capacity. However, since the number of bits of the resistor DAC is 5 bits, the junction capacitance of the MOS transfer gate for 32 taps becomes the parasitic capacitance of the node 23, and the settling time of the node 20 is increased and the comparison time is increased.
[0048]
In the configuration according to the present invention, the comparison time can be shortened by shortening the delay time of the resistor DAC output as compared with the configuration of the prior art with the same number of resistance DAC bits. Further, in order to reduce the sampling time, even when the number of bits of the capacitor DAC is reduced and the number of bits of the resistor DAC is increased, an increase in delay time in the resistor DAC can be suppressed. Therefore, the sampling time can be reduced without substantially increasing the comparison time in the conversion time of the AD converter, and the conversion time can be increased.
[0049]
FIG. 5 is a diagram showing a modification of the successive approximation AD converter according to the present invention.
[0050]
5, the switch circuit 103 is provided in the successive approximation A / D converter according to the present invention shown in FIG. 2, and the divided potential generated by the resistor strings R1 to R16 can be supplied to the outside.
[0051]
In the circuit of FIG. 2, a DAC operation corresponding to 4 bits is realized by taking out a DA output corresponding to 2 bits from the resistor string by the two switch circuits 101 and 102, respectively. With this configuration, it is impossible to directly extract a 4-bit resistance DAC output (16-stage output).
[0052]
During testing or actual use, it may be necessary to supply a divided potential equivalent to 4 bits to the outside of the apparatus. Therefore, in the configuration of FIG. 5, the switch circuit 103 is provided so that a 4-bit DAC output can be extracted. Even if the switch circuit 103 is added, the parasitic capacitances of the nodes 23 and 45 do not increase, so that the AD conversion performance is not deteriorated.
[0053]
FIG. 6 is a circuit diagram showing a second embodiment of the successive approximation AD converter according to the present invention. In FIG. 6, the same elements as those in FIG. 2 are referred to by the same numerals.
[0054]
6 includes an input terminal 10 to which an input potential Vin is applied, nodes 20 to 23, nodes 40 to 44 and 47, a switch circuit 101, a switch circuit 104, a switch circuit 200, a switch circuit 201, and a switch. A circuit 202, a comparator 300, a successive approximation control circuit 302A, resistors R1 to R16, and capacitors C1-C5 and C7 are included. The operation of each switch circuit 102, 104, 200, 201, 202, etc. is controlled by the successive approximation control circuit 302A.
[0055]
Resistors R1 to R16, switch circuits 102 and 104, and capacitor C7 constitute a sub DAC, and C1 to C5 and switch circuits 200 (and 201, 202) constitute a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted with C3 being 2Cx, C4 being 4Cx, and C5 being 8Cx, where C1 and C2 have capacitance values of Cx, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and charged to the input potential Vin. At this time, the switch 202 is controlled so that the node 20 becomes GND. Further, the potential of the node 60 is supplied to the node 47 through the switch circuit 104. The charge stored in C1-C5 and C7 during this sampling is 16CxVin + 4CxV ₆₀ (V ₆₀ Is the potential of the node 60). The capacity of C7 is 4Cx.
[0056]
After completion of sampling, a comparison operation is started, and digital data corresponding to the input potential Vin is determined in order from the MSB. When the number of unit capacitors Cx connected to the reference potential Vref is m and the number of remaining unit capacitors Cx connected to GND is 16-m, the potential V of the node 20 is
V = (16/20) [(m / 16) Vref−Vin] (4)
It becomes. Here, the node 47 is connected to the node 60, and the potential V ₆₀ Is set to
[0057]
By sequentially changing m, the potential of the node 20 can be changed in increments of Vref / 16. Therefore, the MSB side (upper 4 bits) of the digital data can be determined.
[0058]
Next, processing for determining lower bits on the LSB side by the sub DAC will be described.
[0059]
At the node 47 of C7 having a capacitance value 4Cx that is 1/4 of the total sampling capacitance 16Cx of C1 to C5, Vref / 16 is used by using a 2-bit resistor DAC (R1 to R16 and the switch circuit 104). Change the potential in increments. Thereby, the potential of the node 20 as the comparator input can be changed in increments of Vref / 64.
[0060]
For example, the capacitance value of the capacitor connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitor connected to GND by the switch circuit 200 is (15−m) Cx. Further, the potential of the node 47 of C7 set by the 2-bit resistor DAC is set to nVref / 16 (n is 0 to 3) + V ₆₀ And At this time, the potential V of the node 20 determined by charge redistribution is
V = (16/20) [(m / 16 + n / 64) Vref−Vin] (5)
It becomes. At this time, the node 40 is connected to the GND.
[0061]
Therefore, after determining the value of m corresponding to the upper 4 bits of digital data, the value of V can be changed in increments of 64 by dividing the reference potential Vref, and the value of n can be determined by the comparator 300. That is, 2 bits of data corresponding to n can be determined following the upper 4 bits of digital data.
[0062]
As described above, 6-bit digital data can be obtained from the MSB side.
[0063]
Furthermore, at the node 40 of C1 having a capacitance value Cx that is 1/16 of the total sampling capacitance 16Cx of C1 to C5, using a 2-bit resistor DAC (R1 to R16 and the switch circuit 102), Vref The potential is changed in increments of / 16. Thereby, the potential of the node 20 as the comparator input can be changed in increments of Vref / 256.
[0064]
For example, the capacitance value of the capacitor connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitor connected to GND by the switch circuit 200 is (15−m) Cx. Further, the potential of the node 47 of C7 is set to nVref / 16 + V. ₆₀ (N is 0 to 3), and the potential of the node 40 of C1 set by the 2-bit resistor DAC is pVref / 16 (p is 0 to 3). At this time, the potential V of the node 20 determined by charge redistribution is
V = (16/20) [(m / 16 + n / 64 + p / 256) Vref−Vin] (6)
It becomes.
[0065]
Therefore, after determining the values of m and n corresponding to the upper 6 bits of digital data, the value of V is changed in increments of 256 by dividing the reference potential Vref, and the value of p can be determined by the comparator 300. it can. That is, 2-bit data corresponding to p can be determined following the upper 6-bit digital data.
[0066]
As described above, all 8-bit digital data can be obtained.
[0067]
As described above, an 8-bit successive approximation AD converter can be realized by the configuration shown in FIG. In the circuit of FIG. 2, the increment of the output potential of the resistor DAC used for the conversion of the middle bit is Vref / 4. On the other hand, in the configuration of FIG. 6, the increment of the output potential of the resistor DAC used for the intermediate bit conversion is Vref / 16, and C7 having a capacitance value 4Cx that is 1/4 of the total sampling capacitance 16Cx. The potential is added to the node 20 via.
[0068]
In this configuration, the bias potential V ₆₀ And the output potential of the resistor DAC is changed to nVref / 16 + V ₆₀ By setting (n is 0 to 3), the highest possible voltage range of 12Vref / 16 to 15Vref / 16 is used. Accordingly, the switch circuit 104 can be used in a region where the ON resistance is small. In a PMOS and NMOS transfer gate, the ON resistance becomes large at a voltage in the vicinity of ½ of the power supply voltage (Vref), and high-speed operation becomes difficult, but it is close to the power supply voltage (Vref) as in the switch circuit 104 of FIG. By using the voltage, it is possible to reduce the delay time, thereby achieving high-speed conversion processing.
[0069]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
【The invention's effect】
In the AD converter according to the present invention, the scale of the switch circuit can be significantly reduced by dividing the sub DAC into the first resistance type DA converter and the second resistance type DA converter. Thereby, the parasitic capacitance in the switch circuit can be significantly reduced, and the time required for the comparison process can be shortened.
[0070]
Further, by operating the resistor DAC while avoiding the voltage region where the ON resistance of the MOS transfer gate becomes high, it is possible to achieve high speed comparison processing.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a successive approximation AD converter using a conventional CR double stage DAC.
FIG. 2 is a circuit diagram showing a first embodiment of a successive approximation AD converter according to the present invention.
3 is a diagram conceptually showing the configuration and operation of the circuit of FIG. 2. FIG.
4 is a diagram showing a configuration of a local DA converter of FIG. 3 for conceptually explaining the operation of the circuit of FIG. 2;
FIG. 5 is a diagram showing a modification of the successive approximation AD converter according to the present invention.
FIG. 6 is a circuit diagram showing a second embodiment of the successive approximation AD converter according to the present invention.
[Explanation of symbols]
10 Input terminal
101 Switch circuit
102 Switch circuit
200 switch circuit
201 Switch circuit
202 Switch circuit
300 comparator
302 Successive approximation control circuit

Claims (2)

Look including the capacity array of a plurality of capacity for storing sampling the input potential charge, L bit capacity type DA converter in which the first reference potential and second reference potential is selectively applied to the capacitive array When,
A first M-bit resistive DA converter that generates a desired potential by potential division;
A second N-bit resistive DA converter that generates a desired potential by potential division;
A first signal path for adding the output of the first M-bit resistive DA converter to the output of the L-bit capacitive DA converter by capacitive coupling;
A second signal path for adding the output of the second N-bit resistive DA converter to the output of the L-bit capacitive DA converter by capacitive coupling;
A comparator;
In a successive approximation AD converter with a resolution including (L + M + N) bits,
The L-bit capacity DA converter corresponds to L bits from the most significant bit among all the bits subject to AD conversion,
The first M-bit resistive DA converter corresponds to the M bit following the L bit,
The second N-bit resistive DA converter corresponds to the N bits following the M bits,
The first M-bit resistive DA converter and the second N-bit resistive DA converter share a resistor string for potential division, and the first M-bit resistive DA converter and the first M-bit resistive DA converter the second N-bit resistive type DA converter, seen free 2 (M + N) square of the number of resistive elements in total,
The first M-bit resistive DA converter and the second N-bit resistive DA converter divide the first reference potential and the second reference potential by a resistor string, and Of the range from the reference potential to the second reference potential, the output of the first M-bit resistive DA converter and the second N only in either the upper half or the lower half of the range A successive approximation type AD converter characterized in that an output of a bit resistance type DA converter exists .   2. The successive approximation AD converter according to claim 1, further comprising a switch circuit that selectively outputs a divided potential having a resolution of (M + N) bits to the outside.

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