JP6131102B2 - Successive comparison type A / D converter and driving method thereof - Google Patents

Description

  The present invention relates to a successive approximation A / D converter and a driving method thereof.

  A successive approximation type analog-to-digital converter (SAR-ADC) has an advantage that it can be manufactured at a relatively low cost and can be converted at a relatively high speed. The successive approximation A / D converter is built in a semiconductor device such as a microcontroller (MCU), and is widely used for various applications.

  A typical successive approximation A / D converter includes a sampling circuit, a D / A converter (Digital-to-Analog Converter), a comparator, and a logic circuit such as a successive approximation register. The logic circuit sequentially changes the input code (digital code) of the D / A converter so that the difference between the voltage of the analog signal sampled by the sampling circuit and the output voltage of the D / A converter is minimized. The logic circuit outputs the input code of the D / A converter as a solution when the difference between the voltage of the analog signal and the output voltage of the D / A converter becomes the smallest.

  In the successive approximation A / D converter, when obtaining a solution, an operation for obtaining an intermediate point of a section including the solution is repeated. This technique is called binary search. When performing this binary search, the offset voltage of the comparator is a factor that limits the performance of the successive approximation A / D converter.

  In the successive approximation A / D converter, a D / A converter having a self-correction function is used in order to realize a high resolution of, for example, 14 bits or more. However, the offset voltage of the comparison unit also affects the self-correction of the D / A converter, and degrades the accuracy of the self-correction of the D / A converter.

JP 2011-77902 A JP 2011-205230 A JP 2012-74979 A

H. Xiaozong, Z. Jing, G. Weiqi, S. Jiangang and W. Hui, "A 16-bit, 250ksps successive approximation register ADC based on the charge-redistribution technique," Electron Devices and Solid-State Circuits (EDSSC) , 2011 International Conference of, pp.1-4

  It is an object of the present invention to provide a successive approximation A / D converter and a driving method thereof that can reduce the influence of the offset voltage of the comparator.

  According to one aspect of the disclosed technology, a D / A converter including a resistance ladder and outputting a voltage corresponding to an analog input signal and a control code from a first output terminal; and the first of the D / A converter A comparator connected to one output terminal, and a controller that outputs the control code in accordance with the output of the comparator. The comparator receives an offset voltage of the comparator from the resistor ladder. A successive approximation A / D converter is provided that is supplied with a canceling voltage.

  According to another aspect of the disclosed technology, a D / A conversion unit including a resistance ladder, a comparison unit, and a control unit are provided, and a sample phase and a conversion phase are alternately executed to cope with an analog input signal. In the driving method of the successive approximation A / D converter for determining the digital code to be applied, a voltage corresponding to the offset voltage of the comparison circuit in the comparison unit is applied from the D / A conversion unit to the comparison unit during the sample phase. A driving method of a successive approximation A / D converter is provided that is generated by the resistor ladder and is held in a capacitor, and in the conversion phase, the offset voltage of the comparator circuit is canceled by the charge held in the capacitor.

  According to the successive approximation A / D converter and the driving method according to the above aspect, the D / A converter is used to generate a voltage that cancels the offset voltage of the comparator. Thereby, the configuration of the successive approximation A / D converter can be simplified.

FIG. 1 is a circuit diagram (part 1) illustrating an example of a successive approximation A / D converter. FIG. 2 is a circuit diagram (part 2) illustrating an example of the successive approximation A / D converter. 3A and 3B are enlarged views of the capacitance D / A converter shown in FIGS. FIG. 4 is an enlarged view of the resistor D / A converter in FIGS. 1 and 2. FIG. 5 is an enlarged view of the comparator in FIGS. 1 and 2. FIGS. 6A and 6B are diagrams showing the state of the switches in the capacitive D / A converter in the conversion phase. FIG. 7 is a diagram illustrating a state of a switch in the comparator in the conversion phase. FIG. 8 is a circuit diagram showing another example of the successive approximation A / D converter. FIG. 9 is an enlarged view showing the comparator in FIG. FIG. 10 is a circuit diagram (part 1) illustrating the successive approximation A / D converter according to the first embodiment. FIG. 11 is a circuit diagram (part 2) illustrating the successive approximation A / D converter according to the first embodiment. FIG. 12 is an enlarged view of the comparator in FIGS. 10 and 11. FIGS. 13A and 13B are diagrams showing an example of the circuit configuration of the preamplifier. FIG. 14 is a diagram illustrating a circuit configuration example of the dynamic latch circuit. FIG. 15 is a timing chart of the first clock signal, the second clock signal, and the third clock signal during normal operation. FIG. 16 is a flowchart illustrating a control code determination method. FIG. 17 is a flowchart showing the operation of the successive approximation A / D converter according to the first embodiment. FIG. 18 is a circuit diagram (part 1) illustrating the successive approximation A / D converter according to the second embodiment. FIG. 19 is a circuit diagram (part 2) illustrating the successive approximation A / D converter according to the second embodiment. FIG. 20 is an enlarged view of the comparator in FIGS. 18 and 19. FIG. 21 is a flowchart showing a control code determination method.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  As described above, the offset voltage of the comparison unit affects the performance of the successive approximation A / D converter.

  By using a comparison unit composed of a preamplifier having an auto-zero function and a dynamic latch circuit, the influence of the offset voltage of the comparison unit can be reduced.

  1 and 2 are circuit diagrams showing an example of a successive approximation A / D converter using this type of comparison unit. FIG. 1 shows the state of the sample phase, and FIG. 2 shows the state of the conversion phase.

  A successive approximation A / D converter 10 illustrated in FIGS. 1 and 2 includes a capacitive D / A converter 11a and 11b and a resistor D / A converter having a resistor ladder in which a plurality of resistor elements are connected in series. 12, a comparator 13, a logic circuit 14, decoders 15 a and 15 b, and switches SW 1 and SW 2. The comparator 13 is an example of a comparison unit.

  The capacitive D / A converters 11a and 11b determine the upper N bits (N is an arbitrary integer) of the digital code to be a solution, and the resistor D / A converter 12 is the lower M bits of the digital code to be the solution (M is Any integer).

  3A is an enlarged view of the capacitive D / A converter 11a in FIGS. 1 and 2, and FIG. 3B is an enlarged view of the capacitive D / A converter 11b in FIGS. FIG.

As shown in FIG. 3A, the capacitor D / A converter 11a includes a plurality of capacitors C _1,0 ′, C _{1,0 to} C _{1, N−1} and switches S _1,0 ′, S _{1. , 0 to} S1 _{, N-1} , switches _S2,0 , to S2 _{, N-1} , and switches _{SA1,0 to} SA1 _{, N-1} .

When the capacitance values of the capacitors C _1,0 ′ and C _1,0 are C, the capacitance value of the capacitor C _1,1 is 2C,..., And the capacitance value of the capacitor C _{1, N-2} is 2 ^N−2 C The capacitance values of the capacitors C _{1, N-1} are set to 2 ^N-1 C.

The switches S _1,0 ′, S _{1,0 to} S _{1, N-1} are turned on / off by a first clock signal, and the switches S _{2,0 to} S _{2, N-1} are turned on by a second clock signal. On-off operation. Further, the switches SA _{1,0 to} SA _{1, N-1} are switched by a signal output from the logic circuit 14.

The terminal 23a is supplied with a positive signal V _{inp of a} pair of positive and negative analog input signals. This terminal 23a is connected to each contact a of the switches S _1,0 ′, S _{1,0 to} S _{1, N−1} . Further, the contacts b of the switches S _1,0 ′, S _{1,0 to} S _{1, N−1} are respectively connected to the bottom plates of the corresponding capacitors C _1,0 ′, C _{1,0 to} C _{1, N−1.} It is connected. Further, the top plates of the capacitors C _1,0 ′, C _{1,0 to} C _{1, N−1} are all connected to the node N ₁₁ .

The contacts a of the switches S _{2,0 to} S _{2, N-1} are respectively connected to the common contacts c of the corresponding switches SA _{1,0 to} SA _{1, N-1} , and the contacts b are respectively connected to the corresponding capacitors C _1,0. ~ C _{1, N-1} is connected to the bottom plate.

Further, the contacts a of the switches SA _{1,0 to} SA _{1, N-1} are all connected to the terminal 22a, and the contacts b are all connected to the terminal 21a. A positive reference voltage V _refp is supplied to the terminal 21a, and a negative reference voltage V _refm is supplied to the terminal 22a.

The bottom plate of the capacitor C _1,0 ′ is further connected to a contact b of the switch SW1 disposed between the capacitor D / A converter 11a and the resistor D / A converter 12.

As shown in FIG. 3B, the capacitor D / A converter 11b also includes a plurality of capacitors C _2,0 ', C _{2,0 to} C _{2, N-1} and switches S _3,0 ', S _{3. , 0 to} S _{3, N-1} , switches S _{4,0 to} S _{4, N-1} , and switches SB _{1,0 to} SB _{1, N-1} .

When the capacitance values of the capacitors C _2,0 ′ and C _2,0 are C, the capacitance value of the capacitor C _2,1 is 2C,..., And the capacitance value of the capacitor C _{2, N-2} is 2 ^N−2 C The capacitance values of the capacitors C _{2 and N-1} are set to 2 ^N-1 C.

The switches S _3,0 ', S _{3,0 to} S _{3, N-1} are turned on / off by the first clock signal, and the switches S _{4,0 to} S _{4, N-1} are turned on by the second clock signal. Operates on-off. Further, the switches SB _{1,0 to} SB _{1, N-1} are switched by a signal output from the logic circuit 14.

The terminal 23b is supplied with a negative signal V _{inm of a} pair of positive and negative analog input signals. This terminal 23b is connected to each contact a of the switches _S3,0 ', _S3,0 , to S3 _{, N-1} . Further, the contacts b of the switches S _3,0 ', S _3,0 , ~ S _{3, N-1} are respectively connected to the bottoms of the corresponding capacitors C _2,0 ', C _{2,0 to} C _{2, N-1} . Connected to the plate. Further, the top plates of the capacitors C _2,0 ′, C _{2,0 to} C _{2, N−1} are all connected to the node N ₁₂ .

The contacts a of the switches S _{4,0 to} S _{4, N-1} are respectively connected to the common contacts c of the corresponding switches SB _1,0 to SB _{1, N-1} , and the contacts b are respectively connected to the corresponding capacitors C _2,0. ~ C _{2, N-1} is connected to the bottom plate.

The contacts a of the switches SB _{1,0 to} SB _{1, N-1} are all connected to the terminal 22b, and the contacts b are all connected to the terminal 21b. A positive reference voltage V _refp is supplied to the terminal 21b, and a negative reference voltage V _refm is supplied to the terminal 22b.

The bottom plate of the capacitor C _2,0 ′ is further connected to a contact b of the switch SW2 disposed between the capacitor D / A converter 11b and the resistor D / A converter 12.

FIG. 4 is an enlarged view of the resistor D / A converter 12 shown in FIGS. As shown in FIG. 4, the resistor D / A converter 12 includes 2 ^M resistors R _{1 to} R _2M , switches SC _{1 to} SC _2M-1 , and switches SD to SD _2M−1 .

The resistors R _{1 to} R _2M are connected in series between a terminal 24a to which a positive reference voltage V _refp is supplied and a terminal 24b to which a negative reference voltage V _refm is supplied. The resistance values of these resistors R _{1 to} R _2M are set to be the same.

The switches SC _{1 to} SC _2M-1 are connected between the nodes NR _{1 to} NR _2M-1 and the node N ₃₁ between the resistors R _{1 to} R _2M , respectively. Node N ₃₁ is connected to the contact a of the switch SW1 disposed between the capacitor D / A converter 11a and the resistor D / A converter 12.

The switches SD _{1 to} SD _2M-1 are connected between the nodes NR _{1 to} NR _2M-1 and the node N ₃₂ between the resistors R _{1 to} R _2M , respectively. The node N ₃₂ is connected to the contact a of the switch SW2 disposed between the capacitance D / A converter 11b and the resistor D / A converter 12.

The switches SC _{1 to} SC _2M-1 are turned on / off according to the signal output from the decoder 15a, and the switches SD _{1 to} SD _2M-1 are turned on / off according to the signal output from the decoder 15b.

FIG. 5 is an enlarged view of the comparator 13 shown in FIGS. As shown in FIG. 5, the comparator 13 includes a plurality preamplifier (these three in the example) A1, A2, A3, and dynamic latch circuits 16, and a plurality of switches SW ₁₁ to SW _18.

A capacitor C ₃₁ is connected between the inverting output terminal (−) of the preamplifier A1 and the non-inverting input terminal (+) of the preamplifier A2, and the non-inverting output terminal (+) of the preamplifier A1 and the front A capacitor _C32 is connected between the inverting input terminal (−) of the preamplifier A2.

A capacitor _C33 is connected between the inverting output terminal (−) of the preamplifier A2 and the non-inverting input terminal (+) of the preamplifier A3, and the non-inverting output terminal (+) of the preamplifier A2. And a capacitor _C34 is connected between the inverting input terminal (−) of the preamplifier A3.

Further, a capacitor C ₃₅ is connected between the inverting output terminal (−) of the preamplifier A3 and the non-inverting input terminal (+) of the dynamic latch circuit 16, and the non-inverting output terminal (+) of the preamplifier A2. And a inverting input terminal (−) of the dynamic latch circuit 16 is connected with a capacitor C ₃₆ .

The non-inverting input terminal of the preamplifier A1 (+) is connected to the contact b and the node N ₁₁ of the switch SW _11. The inverting input terminal of the preamplifier A1 (-) is connected to the contact b and the node N ₁₂ of the switch SW _12. The contacts a of the switches SW ₁₁ and SW ₁₂ are both connected to the terminal 25. The terminal 25 is held at a common voltage (V _cm ).

A switch SW ₁₃ is connected between the non-inverting input terminal (+) and the terminal 25 of the preamplifier A 2, and a switch SW ₁₄ is connected between the inverting input terminal (−) and the terminal 25. Yes. Further, the switch SW ₁₅ is connected between the non-inverting input terminal (+) and the terminal 25 of the preamplifier A 3, and the switch SW ₁₆ is connected between the inverting input terminal (−) and the terminal 25. Has been.

Further, the switch SW ₁₇ is connected between the non-inverting input terminal (+) and the terminal 25 of the dynamic latch circuit 16, and the switch SW ₁₈ is connected between the inverting input terminal (−) and the terminal 25. Has been. The output of the dynamic latch circuit 16 is input to the logic circuit 14.

  In each phase of the sample phase and the conversion phase, the logic circuit 14 switches the switches SW1 and SW2, the capacitors D / A converters 11a and 11b, the resistor D / A converter 12 and the switches in the comparator 15 at a predetermined timing. Control.

  Hereinafter, the operation of the successive approximation A / D converter 10 will be described.

  In the sample phase, the first clock signal is “H” and the second clock signal is “L”. As shown in FIG. 1, the switches SW1 and SW2 are turned off, and the capacitance D / A converters 11a and 11b and the resistor D / A converter 12 are electrically separated.

Further, as shown in FIGS. 3A and 3B, the switches S _1,0 ′, S _{1,0 to} S _{1, N-1} in the capacitance D / A converter 11a are turned on, and the switch S ₂ is turned on. _{, 0} ~S _{2, N-1} is turned off, is supplied to the input terminal 23a positive differential input signal V _inp capacitance C _{1, 0} ', held in C _1,0 ~C _{1, N-1} The

Similarly, the switches S _3,0 ′, S _{3,0 to} S _{3, N-1} in the capacitance D / A converter 11b are turned on, and the switches S _{4,0 to} S _{4, N-1} are turned off. Thus, the negative differential input signal V _inm supplied to the input terminal 23b is _held in the capacitors C _2,0 ′, C _{2,0 to} C _{2, N.}

At this time, as shown in FIG. 5, the switches SW _{11 to} SW ₁₈ of the comparator 13 are all turned on, and the non-inverting input terminal (+) and the inverting input terminal of the preamplifiers A 1, A 2 and A 3 and the dynamic latch circuit 16. All (-) are held at the common voltage.

Then, in the capacitor C _31, C ₃₂ is accumulated charge corresponding to the offset voltage of the preamplifier A1, the capacitor C _33, C ₃₄ is accumulated charge corresponding to the offset voltage of the preamplifier A2, capacitance C _35, electric charge corresponding to the offset voltage of the preamplifier A3 to C ₃₆ is accumulated.

  Next, the sample phase shifts to the conversion phase. In the conversion phase, the first clock signal is “L” and the second clock signal is “H”. Then, as shown in FIG. 2, the switches SW1 and SW2 are turned on.

Further, as shown in FIGS. 6A and 6B, the switches S _1,0 ′, S _{1,0 to} S _{1, N−1} , S _3,0 in the capacitance D / A converters 11a and 11b are used. ', S _{3,0 to} S _{2, N-1} are turned off, and switches S _{2,0 to} S _{2, N-1} , S _{4,0 to} S ₄ and _N-1 are turned on. Further, as shown in FIG. 7, all the switches SW _{11 to} SW ₁₈ in the comparator 13 are turned off.

Then, the logic circuit 14, on volume D / A converter 11a, the switch SA _{1, 0} -SA ₁ of _{11b, N-1} and the switch SB _1,0 ~SB _{1, N-1} in a predetermined order - Off Operate and search for the solution in order from the upper bit by the binary search method.

When the upper N bits is determined, on the logic circuit 14 further decoders 15a, through 15b of the resistive D / A converter 12 switches _{SC 1 ~SC 2M-1, SD} 1 ~SD 2M-1 in a predetermined order -Turn off and search for lower M bits.

When the upper N bits and the lower M bits are determined in this way, the logic circuit 14 outputs a digital code _Dout corresponding to the analog signal input to the terminals 23a and 23b.

Incidentally, in the conversion phase, the charge stored in the capacitor C ₃₁ -C ₃₆ during the sample phase, the influence of the offset voltage of the preamplifier A1, A2, A3 is canceled. That is, the comparator 13 shown in FIG. 7, the preamplifier A1, A2, A3 capacitance C ₃₁ -C ₃₆ arranged on the output side of the auto-zero function of the preamplifier A1, A2, A3 can be realized. Thereby, highly accurate D / A conversion becomes possible.

  In the successive approximation A / D converter 10 described above, the offset voltage of the preamplifiers A1, A2, and A3 is reduced by the auto-zero function, and the input equivalent offset voltage of the dynamic latch circuit 16 is reduced by the preamplifiers A1, A2, and A3. It is reduced by being reciprocal times the gain. Therefore, as the number of preamplifiers increases, the influence of the input conversion offset voltage of the dynamic latch circuit 16 is reduced.

  However, in the successive approximation A / D converter 10 described above, as the higher resolution is required, a larger number of preamplifiers are required to reduce the influence of the offset voltage. For this reason, there are drawbacks in that downsizing of the semiconductor device is hindered and power consumption is increased.

  FIG. 8 is a circuit diagram showing another example of the successive approximation A / D converter, and FIG. 9 is an enlarged view of the comparator 13a in FIG. In FIG. 8, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the successive approximation A / D converter 10a illustrated in FIG. 8, the comparator 13a includes a dynamic latch circuit 16a, decoders 26a and 26b, D / A converters 27a and 27b, and switches SW ₂₁ and SW _22. It is configured.

The non-inverting input terminal of the dynamic latch circuit 16a (+) as shown in FIG. 9 is connected to the node N _11, the inverting input terminal (-) is connected to the node N _12. Further, the switch SW ₂₁ is connected between the non-inverting input terminal (+) and the terminal 25 of the dynamic latch circuit 16 a, and the switch SW ₂₂ is connected between the inverting input terminal (−) and the terminal 25. Has been.

  The logic circuit 14a uses the decoders 26a and 26b and the D / A converters 27a and 27b to correct the dynamic latch circuit 16a so that the offset voltage is minimized.

  However, the successive approximation A / D converter 10a illustrated in FIG. 8 requires a D / A converter with high resolution when high resolution is required. However, it is difficult to reduce the size of a high-resolution D / A converter and power consumption is large.

  Further, in the successive approximation A / D converter 10a illustrated in FIG. 8, the offset voltage of the dynamic latch circuit 16a changes according to the temperature and the power supply voltage, so that a correction error occurs due to the fluctuation of the temperature or the power supply voltage. There is also a problem.

  In the following embodiments, a successive approximation A / D converter that can reduce the influence of the offset voltage of the comparator with a relatively simple configuration and a driving method thereof will be described.

(First embodiment)
10 and 11 are circuit diagrams showing the successive approximation A / D converter according to the first embodiment. FIG. 10 shows the state of the sample phase, and FIG. 11 shows the state of the conversion phase. 10 and 11, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 10 and 11, the successive approximation A / D converter 30 according to the present embodiment includes capacitance D / A converters 11a and 11b, a resistor D / A converter 12, a comparator 33, It has a logic circuit 34, decoders 35a and 35b, and switches SW1 and SW2.

  The D / A conversion unit includes capacitance D / A converters 11a and 11b, a resistor D / A converter 12, and switches SW1 and SW2. The capacitive D / A converters 11a and 11b are an example of a first D / A converter, and the resistor D / A converter 12 is an example of a second D / A converter. The switches SW1 and SW2 are examples of switch elements.

Since the configurations of the capacitance D / A converters 11a and 11b and the resistor D / A converter 12 have already been described with reference to FIGS. 3A, 3B, and 5, description thereof will be omitted here. . However, in this embodiment, the nodes N ₃₁ and N ₃₂ in the resistor D / A converter 12 are connected to the switches SW ₅₃ and SW ₅₄ in the comparator 33.

Nodes N ₁₁ and N ₁₂ are examples of first output terminals of the D / A converter, and nodes N ₃₁ and N ₃₂ are examples of second output terminals of the D / A converter.

FIG. 12 is an enlarged view showing the comparator 33 in FIGS. As shown in FIG. 12, the comparator 33 includes a pre-amplifier A11, a dynamic latch circuit 39, a capacitor C _61, C _62, and a switch SW ₅₁ to SW _54.

The comparator 33 is an example of a comparison unit, and the dynamic latch circuit 39 is an example of a comparison circuit. The capacitors C ₆₁ and C ₆₂ are an example of the first capacitor. Furthermore, the switches SW ₅₃ and W ₅₄ are an example of a first switch.

In the present embodiment, when the number of bits of the capacitive D / A converters 11a and 11b is N, the gain A of the preamplifier A11 is 2 ^N or more (A ≧ 2 ^N ).

The non-inverting input terminal of the preamplifier A11 (+) is connected to the contact point b of the node N ₁₁ and the switch SW _51, an inverting input terminal (-) is connected to the contact point b of the node N ₁₂ and the switch SW ₅₂ Yes. Further, the contact a of the switch SW _{51 and} the contact a of the switch SW ₅₂ are both connected to the terminal 25. The terminal 25 is held at a common voltage (V _cm ).

Inverting output terminal of the preamplifier A11 (-) is connected to the bottom plate of the capacitor C _61, the top plate of the capacitor C ₆₁ is connected to the non-inverting input terminal of the dynamic latch circuits 39 (+). The non-inverting output terminal of the preamplifier A11 (+) is connected to the bottom plate of the capacitor C _62, the top plate of the capacitor C ₆₂ is the inverting input terminal of the dynamic latch circuits 39 - is connected to () .

The contact a of the switch SW ₅₃ is connected to the node N ₃₁ in the resistor D / A converter 12, and the contact b is connected to the non-inverting input terminal (+) of the dynamic latch circuit 39. Further, the contact a of the switch SW ₅₄ is connected to the node N ₃₂ in the resistor D / A converter 12, and the contact b is connected to the inverting input terminal (−) of the dynamic latch circuit 39.

All of the switches SW _{51 to} SW ₅₄ are turned on and off by the first clock signal.

FIGS. 13A and 13B are diagrams showing a circuit configuration example of the preamplifier A11. FIG. 13A shows a preamplifier with an active load, which includes a current source I ₁ and four transistors Q _{11 to} Q ₁₄ . FIG. 13B shows a preamplifier for a passive load, which is composed of a current source I ₂ , two transistors Q ₂₁ and Q _22, and two resistors R ₁ and R ₂ .

FIG. 14 is a diagram showing a circuit configuration example of the dynamic latch circuit 39. The dynamic latch circuit shown in FIG. 14 is composed of nine transistors Q _{31 to} Q ₃₉ .

  As shown in FIGS. 10 and 11, the logic circuit 34 includes a register 34a and a clock generator 34b. As will be described later, a control code corresponding to the offset voltage of the dynamic latch circuit 39 is stored in the register 34a. The logic circuit 34 is an example of a control unit, and the register 34a is an example of a storage unit.

  The clock generator 34b generates a first clock signal, a second clock signal, and a third clock signal.

  FIG. 15 is a timing chart of the first clock signal Clk1, the second clock signal Clk2, and the third clock signal Clk3 during normal operation.

  As can be seen from FIG. 15, when the first clock signal Clk1 is “H”, the second clock signal Clk2 is “L”, and when the first clock signal Clk1 is “L”, the second clock signal Clk2 is. Becomes “H”.

  During normal operation, the sample phase is entered when the first clock signal Clk1 becomes “H”, and the conversion phase is entered when the second clock signal Clk2 becomes “H”. In the conversion phase, the third clock signal Clk3 having a predetermined frequency is output.

Switches S _1,0 ′, S _{1,0 to} S _{1, N−1} , S _3,0 ′, S _{3,0 to} S _{3, N−1} and comparator 33 in the capacitance D / A converters 11 a and 11 b The switches SW _{51 to} SW ₅₄ are turned on when the first clock signal Clk1 is “H” and turned off when it is “L”.

The switches SW1, SW2 and the switch _{S 2,0 ~S 2, N-1} , S 4,0 ~S 4, N-1 in volume D / A converter 11a, 11b, the second clock signal Clk2 Turns on when H is “H”, and turns off when “L”.

Switches SA _{1 to} SA _N-1 and SB _{1,0 to} SB _{1, N-1 in} the capacitance D / A converters 11a and 11b, and switches SC _{1 to} SC _2M-1 in the resistor D / A converter 12 , SD _{1 to} SC _2M-1 are turned on / off at a timing synchronized with the third clock signal Clk3. The dynamic latch circuit 39 also latches the signal output from the preamplifier A11 at a timing synchronized with the third clock signal Clk3.

In the present embodiment, a voltage corresponding to the offset voltage of the dynamic latch circuit 39 is generated by the resistor D / A converter 12 (resistor ladder), and the voltage is applied to the capacitors C ₆₁ and C ₆₂ . Then, the influence of the offset voltage of the dynamic latch circuit 39 is canceled by the charges accumulated in the capacitors C ₆₁ and C ₆₂ .

  FIG. 16 is a flowchart showing a method of determining a control code for generating a voltage corresponding to the offset voltage of the dynamic latch circuit 39 by the resistor D / A converter 12.

  First, in step S11, the logic circuit 34 sets the first clock signal Clk1 to “L” and the second clock signal Clk2 to “H”.

As a result, the switches SW1 and SW2 are turned off, and the capacitance D / A converters 11a and 11b and the resistor D / A converter 12 are electrically separated. Also, as shown in FIG. 12, the switches SW _{51 to} SW ₅₄ in the comparator 33 are all turned on, and charges corresponding to the offset voltage of the preamplifier A11 are accumulated in the capacitors C ₆₁ and C ₆₂ .

In step S12, the logic circuit 34 supplies the third clock signal Clk3 to the decoders 35a and 35b and the dynamic latch circuit 39, and outputs a control signal (digital signal) to the decoders 35a and 35b. At this time, the logic circuit 34 outputs a control signal so that the voltages of the nodes N ₃₁ and N ₃₂ of the resistor D / A converter 12 are intermediate between the positive reference voltage Vrefp and the negative reference voltage Vrefm.

  In step S13, the logic circuit 34 changes the control signal supplied to the decoders 35a and 35b in accordance with the current output of the dynamic latch circuit 39.

  For example, when the output of the dynamic latch circuit 39 is “H”, the logic circuit 34 changes the control signal supplied to the decoders 35 a and 35 b to change the differential output voltage of the resistor D / A converter 12 by one bit. Only (LSB) is changed to the negative side.

  When the output of the dynamic latch circuit 39 is “L”, the logic circuit 34 changes the control signal supplied to the decoders 35a and 35b to change the differential output voltage of the resistor D / A converter 12 by 1 bit. Change to the positive side by (LSB).

  Next, the process proceeds to step S14, and the logic circuit 34 determines whether or not the polarity of the output voltage of the dynamic latch circuit 39 has changed. If the polarity has not changed (NO), the process returns to step S13, and the control signal is further changed.

  By repeating steps S13 and S14, the polarity of the output voltage of the dynamic latch circuit 39 changes. The output voltage of the resistor D / A converter 12 when the polarity of the output voltage of the dynamic latch circuit 39 changes corresponds to the offset voltage of the dynamic latch circuit 39.

  If a change in the polarity of the output voltage of the dynamic latch circuit 39 is detected in step S14, the process proceeds to step S15. Then, the logic circuit 34 stores the control signal at this time in the register 34 a as a control code corresponding to the offset voltage of the dynamic latch circuit 39.

  In this way, a control code for generating a voltage corresponding to the offset voltage of the dynamic latch circuit 39 by the resistor D / A converter 12 is determined. Hereinafter, a series of flows shown in FIG. 16 is referred to as a control code determination flow.

In this embodiment, the control code is determined by sequentially changing the control signals supplied to the decoders 35a and 35b, but the control code determination method is not limited to this. For example, in the sample phase, C _{1, N-1 is connected} to the reference voltage Vrefp, the remaining capacitance is connected to the reference voltage Vrefm, and the capacitors C ₆₁ and C ₆₂ are connected to the midpoint between the reference voltage Vrefp and the reference voltage Vrefm. When an operation similar to the A / D conversion operation is performed, a digital code corresponding to the offset voltage of the dynamic latch circuit 39 is output as Dout. The upper M bits of this digital code may be used as a control code.

  FIG. 17 is a flowchart showing the operation of the successive approximation A / D converter 30 according to this embodiment.

  First, when the power is turned on, the control code determination flow illustrated in FIG. 16 is executed in step S21 to determine the control code.

  When the control code determination flow ends in step S21, the process proceeds to step S22. In step S22, the logic circuit 34 sets the first clock signal Clk1 to “H” and sets the second clock signal Clk2 to “L”, and executes the sample phase.

In the sample phase, the capacitors C _1,0 ′, C _{1,0 to} C _{1, N−1} , C _2,0 ′, C _{2,0 to} C _{2, N−1} of the capacitors D / A converters 11 a and 11 b are used. In addition, the differential input signals Vinp and Vinm are held.

The non-inverting input terminal (+) and the inverting input terminal of the preamplifier A11 in the comparator 33 (-) none is held to the common voltage V _cm, before charge capacity corresponding to the offset voltage of the preamplifier A11 C _61, is stored in C _62.

Further, the control code stored in the register 34 a is output to the decoders 35 a and 35 b, and charges corresponding to the offset voltage of the dynamic latch circuit 39 are also stored in the capacitors C ₆₁ and C ₆₂ in the comparator 33.

  Next, the process proceeds to step S23, where the logic circuit 34 sets the first clock signal Clk1 to “L” and sets the second clock signal Clk2 to “H”, and executes the conversion phase.

In the conversion phase, the logic circuit 34, the capacitance D / A converters 11a and 11b, the resistor D / A converter 12 and the comparator 33 correspond to the differential analog signals V _inp and V _inm input to the terminals 23a and 23b. The digital signal is determined in order from the upper bit.

Terminal 23a, the analog signal V _inp input to 23b, when all the bits of the digital signal corresponding to the V _inm is determined, the digital signal is output as a digital code D _out from the logic circuit 34.

Conversion phase, the charge stored in the capacitor C _61, C _62, the offset voltage of the offset voltage and the dynamic latch circuit 39 of the preamplifier A11 is canceled. Thereby, accurate A / D conversion becomes possible.

  Next, the process proceeds to step S24, and it is determined whether or not to end the A / D conversion. When continuing the A / D conversion, the process returns to step S22.

  Since the successive approximation A / D converter 30 according to the present embodiment corrects the offset voltage of the dynamic latch circuit 39 using the resistor D / A converter 12, the number of components of the comparator 33 can be reduced. As a result, the semiconductor device can be further reduced in size and power consumption.

The successive approximation A / D converter 30 according to the present embodiment uses the offset voltage of the dynamic latch circuit 39 as the successive approximation A / D converter 30 when the gain A of the preamplifier A11 is 2 ^N or more. Can be corrected more finely than the resolution (N + M bits).

  In this embodiment, the control code determination flow is performed when the power is turned on. However, the control code determination flow may be performed only when the power is first turned on, or may be performed when a predetermined signal is received from an external device.

By the way, the offset voltage of the dynamic latch circuit 39 is generated due to a mismatch between the differential amplifiers constituting the dynamic latch circuit 39. Assuming that the offset voltage generated by the mismatch between the differentials is V _ofst , the input differential signal V _{in, latch} of the dynamic latch circuit 39 is expressed by the following equation (1) according to the charge conservation law.

Here, V _calDAC is a correction voltage, that is, an output voltage of the resistor D / A converter 12. As apparent from the equation (1), the output voltage V _calDAC of the resistor D / A converter 12 is matched with the offset voltage V _ofst (V _ofst = −V _calDAC ), so that the offset voltage of the dynamic latch circuit 39 is set. The influence of can be eliminated.

Further, according to the present embodiment, when the gain of the preamplifier A11 is A, the influence of the correction residual voltage (V _calDAC + V _ofst ) on the temperature and power supply voltage is reduced to 1 / A times. .

(Second Embodiment)
18 and 19 are circuit diagrams showing a successive approximation A / D converter according to the second embodiment. FIG. 18 shows the state of the sample phase, and FIG. 19 shows the state of the conversion phase. 18 and 19, the same components as those in FIGS. 10 and 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

The first embodiment is applied when the gain of the preamplifier in the comparator is large (A ≧ 2 ^N ), and the second embodiment has a small gain of the preamplifier in the comparator (A <2 ^N). ) Apply when.

  As shown in FIGS. 18 and 19, the successive approximation A / D converter 40 according to the present embodiment includes capacitive D / A converters 11 a and 11 b, a resistor D / A converter 12, a comparator 43, It has a logic circuit 44, decoders 35a and 35b, and switches SW1 and SW2.

FIG. 20 is an enlarged view of the comparator 43 in FIGS. As shown in FIG. 20, the comparator 43 includes a pre-amplifier A12, a dynamic latch circuit 39, a capacitor C ₆₁ -C _64, and a switch SW ₅₁ to SW _58.

Capacitances C ₆₃ and C ₆₄ are examples of the second capacity. The switches SW ₅₇ and SW ₅₈ are examples of the second switch. Furthermore, the switches SW ₅₅ and SW ₅₆ are an example of a third switch.

In this embodiment, when the number of bits of the capacitive D / A converters 11a and 11b is N, the gain A of the preamplifier A12 is assumed to be smaller than 2 ^N (A <2 ^N ).

The non-inverting input terminal of the preamplifier A12 (+) is connected to the contact point b of the node N ₁₁ and the switch SW _51, an inverting input terminal (-) is connected to the contact point b of the node N ₁₂ and the switch SW ₅₂ Yes. The contacts b of the switches SW ₅₁ and SW ₅₂ are both connected to the terminal 25. The terminal 25 is held at a common voltage (V _cm ).

Inverting output terminal of the preamplifier A12 (-) is connected to the bottom plate of the capacitor C _61, the top plate of the capacitor C ₆₁ is connected to the non-inverting input terminal of the dynamic latch circuits 39 (+). The non-inverting output terminal of the preamplifier A12 (+) is connected to the bottom plate of the capacitor C _62, the top plate of the capacitor C ₆₂ is the inverting input terminal of the dynamic latch circuits 39 - is connected to () .

The contact a of the switch SW ₅₃ is connected to the node N ₃₁ in the resistor D / A converter 12, and the contact b is connected to the contact b of the switch SW ₅₅ and the bottom plate of the capacitor C ₆₃ . The contact a of the switch SW ₅₅ is grounded, and the top plate of the capacitor C ₆₃ is connected to the non-inverting input terminal (+) of the dynamic latch circuit 39.

The contact a of the switch SW ₅₄ is connected to the node N ₃₂ in the resistor D / A converter 12, and the contact b is connected to the contact b of the switch SW ₅₆ and the bottom plate of the capacitor C ₆₄ . The contact a of the switch SW ₅₆ is grounded, and the top plate of the capacitor C ₆₄ is connected to the inverting input terminal (−) of the dynamic latch circuit 39.

The contact b of the switch SW ₅₇ is connected to the non-inverting input terminal (+) of the dynamic latch circuit 39, and the contact a is connected to the terminal 25. The contact b of the switch SW ₅₈ is connected to the inverting input terminal (−) of the dynamic latch circuit ₃₉ , and the contact a is connected to the terminal 25.

  The logic circuit 44 includes a register 44a and a clock generator 44b as shown in FIGS. A control code corresponding to the offset voltage of the dynamic latch circuit 39 is stored in the register 44a.

  As in the first embodiment, the clock generator 44b outputs a first clock signal Clk1, a second clock signal Clk2, and a third clock signal Clk3. In addition, the clock generator 44b outputs a clock signal Clk1 ′ different from the first clock signal Clk1 and a clock signal Clk2 ′ different from the second clock signal Clk2 in the control code determination flow as will be described later. To do.

During normal operation (sample phase and conversion phase), the switches SW ₅₁ , SW ₅₂ , SW ₅₃ , SW ₅₄ , SW ₅₇ , SW ₅₈ are turned on and off by the first clock signal, and the switches SW ₅₅ , SW ₅₆ Is turned on and off by the second clock signal.

However, when the control code decision flow is executed, the switches SW ₅₃ , SW ₅₄ , SW ₅₇ , SW ₅₈ are turned on / off by the clock signal Clk1 ′, and the switches SW ₅₅ , SW ₅₆ are turned on / off by the clock signal Clk2 ′. . The switches SW ₅₁ and SW ₅₂ are turned on / off by the first clock signal Clk1 also in the control code determination flow.

  FIG. 21 is a flowchart showing a control code determination method (control code determination flow) for generating a voltage corresponding to the offset voltage of the dynamic latch circuit 39 by the resistor D / A converter 12.

First, in step S31, the logic circuit 44 sets the first clock signal Clk1 to “H” and the second clock signal Clk2 to “L”. As a result, the switches SW1 and SW2 are turned off, and the capacitance D / A converters 11a and 11b and the resistor D / A converter 12 are electrically separated. Further, both the switches SW ₅₁ and SW ₅₂ in the comparator 43 are turned on.

Next, the process proceeds to step S32, and the logic circuit 44 makes the voltage at the nodes N ₃₁ and N ₃₂ of the resistor D / A converter 12 intermediate between the positive reference voltage Vrefp and the negative reference voltage Vrefm. Control signals are output to the decoders 35a and 35b.

Next, in step S33, the logic circuit 44 sets the clock signal Clk1 ′ to “H” and the clock signal Clk2 ′ to “L”. As a result, intermediate voltages between the positive reference voltage Vrefp and the negative reference voltage Vrefm are applied to the capacitors C ₆₃ and C ₆₄ , respectively.

Next, the process proceeds to step S34, and the logic circuit 44 sets the clock signal Clk1 ′ to “L” and the clock signal Clk2 ′ to “H”. As a result, the voltages held in the capacitors C ₆₃ and C ₆₄ are input to the non-inverting input terminal (+) and the inverting input terminal (−) of the dynamic latch circuit 39.

  Next, the process proceeds to step S35, and when the third clock signal Clk3 output from the logic circuit 44 becomes “H”, the dynamic latch circuit 39 is input to the non-inverting input terminal (+) and the inverting input terminal (−). Latch the signal. At this time, the same voltage is input to the non-inverting input terminal (+) and the inverting input terminal (−) of the dynamic latch circuit 39, but the output voltage of the dynamic latch circuit 39 is affected by the offset voltage of the dynamic latch circuit 39. Is either “H” or “L”. The logic circuit 44 determines whether the output of the dynamic latch circuit 39 is “H” or “L”.

  Next, the process proceeds to step S36, where the logic circuit 44 determines whether the polarity of the output voltage of the dynamic latch circuit 39 has changed. When there is no comparison target in the first loop or when the polarity has not changed (in the case of NO), the process proceeds to step S37.

  In step S37, the logic circuit 44 changes the control signal. For example, when it is determined in step S35 that the output of the dynamic latch circuit 39 is “H”, the logic circuit 49 changes the control signal supplied to the decoders 35a and 35b, and the differential of the resistor D / A converter 12 is changed. The output voltage is changed to the negative side by 1 bit (LSB).

  On the other hand, if it is determined in step S35 that the output of the dynamic latch circuit 39 is “L”, the logic circuit 44 changes the control signal supplied to the decoders 35a and 35b, and the difference between the resistors D / A converter 12 is changed. The dynamic output voltage is changed to the positive side by 1 bit (LSB).

  By repeating steps S33 to S37, the polarity of the output voltage of the dynamic latch circuit 39 changes. The output voltage of the resistor D / A converter 12 when the polarity of the output voltage of the dynamic latch circuit 39 changes corresponds to the offset voltage of the dynamic latch circuit 39.

  When a change in the polarity of the output voltage of the dynamic latch circuit 39 is detected in step S36, the process proceeds to step S38. Then, the logic circuit 44 stores the control signal at this time in the register 44 a as a control code corresponding to the offset voltage of the dynamic latch circuit 39.

  Since the subsequent operations in the sample phase and the conversion phase are the same as those in the first embodiment, description thereof is omitted here.

  Also in this embodiment, since the offset voltage of the dynamic latch circuit 39 is corrected using the resistor D / A converter 12, the number of components of the comparator 33 can be reduced. As a result, the semiconductor device can be further reduced in size and power consumption.

When the gain A of the preamplifier A11 is smaller than 2 ^N , the successive approximation A / D converter 40 according to the present embodiment uses the offset voltage of the dynamic latch circuit as the value of the successive approximation A / D converter 40. Correction can be made more finely than the resolution (N + M bits).

By the way, if the capacitance values of the capacitors C ₆₁ and C ₆₂ are C ₁ , the capacitance values of the capacitors C ₆₃ and C ₆₄ are C _2, and the offset voltage generated due to the differential mismatch of the dynamic latch circuit 39 is V _ofst , dynamic The input differential signal V _{in, latch} of the latch circuit 39 is expressed by the following equation (2).

As apparent from the equation (2), by _setting V _ofst = − (C ₂ / C ₁ ) V _calDAC , the influence of the offset voltage of the dynamic latch circuit 39 can be eliminated.

  In each of the first and second embodiments described above, the case where the D / A converter is configured by a capacitance D / A converter and a resistor D / A converter has been described. . However, the D / A converter may be composed of only a resistor D / A converter.

  For example, in FIG. 10 and the like, an A / D converter that receives a pair of positive and negative analog signals and converts them into a digital output has been described as an example. However, the present invention provides an A / D that receives a single-phase analog input and converts it into a digital output. It can also be applied to a D converter. In this case, the comparison unit compares the output of the D / A conversion unit with a predetermined reference value.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) A D / A converter that includes a resistor ladder and outputs a voltage corresponding to an analog input signal and a control code from a first output terminal;
A comparator connected to the first output terminal of the D / A converter;
A control unit that outputs the control code according to the output of the comparison unit;
The successive approximation A / D converter, wherein the comparator is supplied with a voltage that cancels the offset voltage of the comparator from the resistor ladder.

(Supplementary note 2)
A preamplifier to which an output from the first output terminal of the D / A converter is input;
A comparison circuit;
A first capacitor disposed between an output terminal of the preamplifier and an input terminal of the comparison circuit;
The sequential switch according to claim 1, further comprising: a first switch disposed between the second output terminal of the resistance ladder and the input terminal of the comparison circuit and turned on and off by the control unit. Comparison type A / D converter.

(Additional remark 3) Furthermore, the 2nd capacity | capacitance arrange | positioned between the said input terminal and the said 1st switch of the said comparison circuit,
A second switch controlled by the control unit to hold the input terminal of the comparison circuit at a common voltage;
The successive approximation type A / D converter according to appendix 2, further comprising a third switch arranged between the second capacitor and the ground.

(Supplementary Note 4) The D / A converter is
A first D / A converter that determines upper N bits (N is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A second D / A converter including the resistor ladder for determining lower M bits (M is an arbitrary integer) of a digital signal corresponding to the analog input signal;
And a fourth switch connected between the first D / A converter and the second D / A converter and turned on and off by a signal from the control unit. The successive approximation A / D converter according to 2 or 3.

  (Supplementary note 5) The successive approximation type A / D converter according to supplementary note 4, wherein the first D / A converter is a capacitive D / A converter.

  (Supplementary Note 6) The analog input signal includes a first analog input signal and a second analog input signal having a phase opposite to that of the first analog input signal, and the capacitor D / A converter includes the first analog input signal. A positive-capacitance D / A converter that receives a signal and outputs a positive signal; and a negative-capacitance D / A converter that receives a second analog input signal and outputs a negative signal. The successive approximation type A / D converter according to appendix 5, which is a feature.

  (Supplementary note 7) The successive approximation type A / A according to Supplementary note 4, further comprising a drive circuit that drives the second D / A converter in accordance with the control code output from the control unit. D converter.

  (Supplementary note 8) The successive approximation A / D according to any one of supplementary notes 1 to 7, wherein the control unit stores a control code corresponding to a voltage for canceling the offset voltage. converter.

  (Supplementary note 9) The successive approximation type A / D converter according to any one of supplementary notes 2 to 8, wherein the comparison circuit is a dynamic latch circuit.

  (Additional remark 10) The said control part samples the said analog input signal to the said 1st D / A converter, The conversion phase which searches the digital code corresponding to the analog signal sampled during the said sample phase Are alternately executed, and during the sample phase, the second D / A converter is controlled to generate a voltage that cancels the offset voltage, and is transmitted to the first capacitor and the second capacitor. The successive approximation type A / D converter according to appendix 4, wherein:

(Supplementary Note 11) Sequential comparison including a D / A conversion unit including a resistance ladder, a comparison unit, and a control unit, and alternately executing a sample phase and a conversion phase to determine a digital code corresponding to an analog input signal In a method for driving a type A / D converter,
During the sample phase, a voltage corresponding to the offset voltage of the comparison circuit in the comparison unit is generated from the D / A conversion unit to the comparison unit by the resistor ladder and held in the capacitor.
In the conversion phase, the offset voltage of the comparison circuit is canceled by the electric charge held in the capacitor. A driving method of the successive approximation A / D converter, characterized in that:

(Additional remark 12) The said control part outputs a control code to the said D / A conversion part, changes the signal voltage output from the said D / A conversion part sequentially, and changes the polarity of the signal output from the said comparison circuit When the presence or absence of a change is detected, the control code at that time is stored in the storage unit,
The control code stored in the storage unit during the sample phase is output to the D / A conversion unit, and the D / A conversion unit generates a voltage corresponding to the offset voltage of the comparison circuit. The driving method of the successive approximation A / D converter according to appendix 11.

(Supplementary note 13) The D / A converter is
A first D / A converter that determines upper N bits (N is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A second D / A converter including the resistor ladder for determining lower M bits (M is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A switch element connected between the first D / A converter and the second D / A converter and turned on and off by a signal from the control unit;
The control unit samples the analog input signal to the first D / A converter during the sample phase and controls the second D / A converter to cope with the offset voltage of the comparison circuit. 13. A method for driving a successive approximation A / D converter according to appendix 11 or 12, characterized in that a voltage is generated.

  (Supplementary note 14) The supplementary note 13, wherein the first D / A converter is a capacitance D / A converter, and the second D / A converter is a resistance D / A converter. Driving method of successive approximation type A / D converter.

  (Supplementary note 15) The successive approximation A / D conversion according to any one of supplementary notes 11 to 14, wherein a control code corresponding to a voltage for canceling the offset voltage is stored in the control unit. Device driving method.

  DESCRIPTION OF SYMBOLS 10,10a, 30,40 ... Successive comparison type A / D converter, 11a, 11b ... Capacitance D / A converter, 12 ... Resistor D / A converter, 13, 13a, 33, 43 ... Comparator, 14, 14a , 34, 44 ... logic circuit, 15a, 15b, 26a, 26b, 35a, 35b ... decoder, 16, 16a, 39 ... dynamic latch circuit, 27a, 27b ... D / A converter, 34a, 44a ... register, 34b, 44b: Clock generator, A1 to A3, A11, A12: Preamplifier.

Claims (9)

A D / A converter that includes a resistance ladder and outputs a voltage corresponding to the analog input signal and the control code from the first output terminal;
A comparator connected to the first output terminal of the D / A converter;
Storing the control code corresponding to the voltage for canceling the offset voltage of the comparison unit from the resistance ladder, and a control unit for outputting the control code according to the output of the comparison unit,
Wherein the comparison unit, successive approximation A / D converter, wherein the voltage for canceling the offset voltage from the resistor ladder is supplied. The comparison unit includes:
A preamplifier to which an output from the first output terminal of the D / A converter is input;
A comparison circuit;
A first capacitor disposed between an output terminal of the preamplifier and an input terminal of the comparison circuit;
2. The first switch according to claim 1, further comprising a first switch disposed between the second output terminal of the resistor ladder and the input terminal of the comparison circuit and turned on and off by the control unit. Successive comparison type A / D converter. A second capacitor disposed between the input terminal of the comparison circuit and the first switch;
A second switch controlled by the control unit to hold the input terminal of the comparison circuit at a common voltage;
The successive approximation A / D converter according to claim 2, further comprising a third switch disposed between the second capacitor and the ground. The D / A converter is
A first D / A converter that determines upper N bits (N is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A second D / A converter including the resistor ladder for determining lower M bits (M is an arbitrary integer) of a digital signal corresponding to the analog input signal;
4. A fourth switch connected between the first D / A converter and the second D / A converter and turned on and off by a signal from the control unit. Item 4. The successive approximation A / D converter according to Item 2 or 3.   5. The successive approximation A / D converter according to claim 4, wherein the first D / A converter is a capacitive D / A converter.   5. The successive approximation A / D converter according to claim 4, further comprising a drive circuit that drives the second D / A converter in accordance with the control code output from the control unit. . The comparison circuit, a successive approximation type A / D converter according to any one of claims 2 to 6, characterized in that a dynamic latch circuit. A successive approximation A / D that includes a D / A conversion unit including a resistance ladder, a comparison unit, and a control unit, and alternately executes a sample phase and a conversion phase to determine a digital code corresponding to an analog input signal. In the driving method of the converter,
During the sample phase, a voltage corresponding to the offset voltage of the comparison circuit in the comparison unit is generated from the D / A conversion unit to the comparison unit by the resistor ladder and held in the capacitor.
In the conversion phase, the offset voltage of the comparison circuit is canceled by the charge held in the capacitor ,
The control unit outputs a control code to the D / A conversion unit, sequentially changes the signal voltage output from the D / A conversion unit, and determines whether or not the polarity of the signal output from the comparison circuit has changed. When detected, the control code at that time is stored in the storage unit,
The successive approximation type A , wherein the control code is output to the D / A converter during the sample phase, and the D / A converter generates a voltage corresponding to the offset voltage of the comparison circuit. / D converter driving method. The D / A converter is
A first D / A converter that determines upper N bits (N is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A second D / A converter including the resistor ladder for determining lower M bits (M is an arbitrary integer) of a digital signal corresponding to the analog input signal;
A switch element connected between the first D / A converter and the second D / A converter and turned on and off by a signal from the control unit;
The control unit samples the analog input signal to the first D / A converter during the sample phase and controls the second D / A converter to cope with the offset voltage of the comparison circuit. It is characterized by generating a voltage to
The method for driving a successive approximation A / D converter according to claim 8 .

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