JP3104952B2 - Analog-to-digital converter and microcomputer equipped with the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a successive approximation type analog
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital converter, and particularly to an analog-digital converter which is required to be small and have high precision, and which is suitable for being mounted on a microcomputer.

[0002]

2. Description of the Related Art As is well known, an A / D converter (analog-to-digital converter) is a device for converting an analog signal to a digital signal. There is an A / D converter of the system. Conventional examples of the successive approximation type A / D converter include a capacitance array method, a resistance ladder method, and an R-2R converter.
Various types are used depending on the configuration of a comparison voltage generation circuit (D / A conversion circuit) such as a resistance type.

In the following description, the resistance ladder method will be described for convenience. However, the other methods are the same in that a comparison voltage is generated. First, in this resistance ladder type A / D converter, the reference voltage, which is a full-scale voltage, is divided equally by a resistor, and the connection point of each resistor is selected by a switch group, so that the comparison voltage is obtained. Is to be generated. FIG. 9 shows a conventional example of a successive approximation type A / D converter having a resolution of 8 bits. In this conventional example, a D / A conversion circuit 100 for generating a comparison voltage, a comparator 102, a control circuit 103, It comprises an 8-bit successive approximation register 104 and a data bus 105 to which an A / D conversion result is output.

First, the D / A conversion circuit 100 connects 2 ⁸ (= 256) resistive elements in series to form a resistance ladder circuit 10.
6, and a voltage thus equally divided is selected by a decoder switch circuit (tree-like switch circuit) 107 to generate a comparison voltage. At this time, in order to provide a half-offset D / A transfer characteristic, in the resistance ladder circuit 106, the resistance values of the resistance elements at both ends of the resistance ladder are respectively 1 with respect to the unit resistance values R of the other portions.
/ 2 times and 3/2 times.

In this conventional example, since 2 / n resistors and at least 2n or more switch groups are required for A / D conversion with a resolution of n bits, the A / D conversion is occupied. There is a problem that the area becomes large. On the other hand, in the invention according to the application of Japanese Patent Application No. 4-63190, a successive approximation type A / D converter characterized by providing a low-resolution reference voltage generation region and a high-resolution reference voltage generation region. However, it is difficult to solve the problem essentially because of the large number of resistance elements and the precision matching.

[0006]

SUMMARY OF THE INVENTION The above-mentioned prior art is based on A /
No consideration has been given to an increase in the number of circuit elements due to an increase in the resolution of the D converter, and there has been a problem with the high-precision A / D converter in terms of an increase in chip size and an increase in cost.
For example, the resolution of a resistance ladder type 10-bit A / D converter is four times that of an 8-bit A / D converter, and high-precision A / D conversion is possible, but the size of the comparison voltage generation circuit is also four times. growing.

That is, in the prior art, in order to increase the resolution of the A / D converter, it is necessary to subdivide the reference voltage (increase the number of resistive elements). As a result, the chip size increases and the cost increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a small-sized, high-accuracy, high-resolution successive approximation A / D converter at a low cost, which suppresses an increase in the scale of a comparison voltage generation circuit, that is, a D / A conversion circuit accompanying an increase in resolution. Is to do.

[0008]

The object of the present invention is to provide a comparative voltage generator.
And the output of the comparison voltage generation circuit and the analog input voltage.
And a comparator that uses the voltage as one input and the other as input.
Generating the comparison voltage according to the output of the comparator.
Successive approximation type analog circuit with successive switching of circuit output voltage
In the digital-to-digital converter, the comparison voltage generation circuit
Equalizer that divides the reference voltage to generate multiple divided voltages.
The resistive voltage dividing circuit and the divided voltage of the equal resistance voltage dividing circuit
First switch for selecting and outputting according to the output of the parator
A decoder circuit and an output of the first switch decoder circuit
And one of the inputs of the comparator
The coupling capacitance element and the divided voltage of the
A resistor ladder circuit for further dividing a part,
Select the divided voltage of the circuit according to the output of the comparator.
A second switch decoder circuit for outputting the second switch decoder circuit and the second switch decoder circuit.
The output of the latch decoder circuit is
And a weighted capacitive element group for adding and subtracting from the voltage.
The output voltage of the first switch decoder circuit is used as a comparison voltage.
Successive comparison operation of the upper bit group
The output voltage of the multi-decoder circuit is
To the output voltage of the first switch decoder circuit.
The order of the lower bit group using the subtracted voltage as the comparison voltage
It is achieved by the following comparison operation to sequentially row of Migihitsuji. the same
The above-mentioned object is to provide a comparison voltage generation circuit and a comparison voltage generation circuit.
Circuit output and analog input voltage
And a comparator as the output of the comparator.
Method of sequentially switching the output of the comparison voltage generation circuit according to
In the successive approximation type analog-to-digital converter of the formula:
The comparison voltage generation circuit divides the reference voltage into a plurality of
A first resistor voltage-dividing circuit for generating a divided voltage;
The first divided voltage of the voltage dividing circuit is output to the output of the comparator.
A first switch decoder circuit for selecting and outputting according to the
A part of the divided voltage of the first resistor voltage dividing circuit is used as a second reference voltage.
And dividing the second reference voltage into a plurality of second reference voltages.
A second resistive voltage dividing circuit for generating a divided voltage;
The divided voltage of the anti-division circuit is set according to the output of the comparator.
And a second switch decoder circuit for selecting and outputting
And compares the output voltage of the first switch decoder circuit.
And sequential ratio 較動operation of the high-order bit group that voltage, the above-mentioned
The second voltage is applied to the output voltage of the first switch decoder circuit.
The voltage obtained by adding or subtracting the output voltage of the voltage divider circuit is used as the comparison voltage.
And successive approximation operations of the lower bit groups
It is achieved even if you do. At this time, the second reference voltage
Is connected to the first resistor voltage dividing circuit via a buffer amplifier.
Is supplied to the second resistor voltage dividing circuit from a part of the divided voltage of
Or the first resistor voltage dividing circuit
To the two voltage dividing terminals on both sides near the center of
By connecting both terminals of the resistance voltage dividing circuit in parallel,
The voltage may be supplied to the second resistor voltage dividing circuit.
Through one input of the differential amplifier to the first resistor
A second resistive voltage dividing circuit from a part of the divided voltage of the voltage dividing circuit;
To the other input of the differential amplifier.
A voltage may be supplied.

[0009]

For example, successive approximation method A /
In the D converter, for example, a D / A conversion circuit having a resistor ladder configuration for successive approximation of the upper 5 bits, and a D / A converter having a resistor ladder configuration for successive approximation of the lower 3 bits and a weighting capacitance configuration are used.
/ A conversion circuit, the upper bit group generates the comparison voltage by dividing the divided voltage of the resistance ladder circuit by the weighting capacity by using the divided voltage of the resistance ladder circuit as the comparison voltage. Thus, the successive approximation operation is performed.

Therefore, the number of resistance elements can be greatly reduced as compared with the case where the comparison voltages for 8 bits are collectively generated. As a result, the scale of the D / A conversion circuit can be reduced, and high precision can be achieved. The size of the A / D converter can be reduced.

Although the resolution of the A / D converter has been described using an example of an 8-bit configuration to a 10-bit configuration, the present invention particularly limits the number of these bits and the division of the upper and lower bit groups. It is not limited to this, and any number of bits may be used.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an A / D converter according to the present invention will be described.
This will be described in detail with reference to the illustrated embodiment. First, the basics of the present invention
The configuration of the book will be described with reference to the basic example of FIG.
The basic example shown in FIG. 1 embodies the present invention as an 8-bit A / D converter. The overall configuration of the A / D converter is the same as that of the conventional example shown in FIG.
In the following description, only the analog processing unit related to the present invention will be described unless otherwise specified.

The basic example shown in FIG. 1 includes a resistance ladder circuit 32, a first switch decoder circuit 33, a second switch decoder circuit 50, and weighting capacitors (capacitors) C2 and C3, as shown in FIG. , C4, sampling capacity (capacitor) that constitutes the chopper type comparator
C1, a CMOS logic inverter 34, and CMOS switches CM1, CM2, CM3.

First, the resistance ladder circuit 32 is composed of 2 ⁵ (= 3
2) The resistance elements R0 to R31 are connected in series. At this time, similarly to the conventional example of FIG. 9, the resistance R0 at both ends of the resistance ladder is provided in order to have a half offset D / A transmission characteristic. And R31 have resistance values of other resistors R1 to R1.
The unit resistance R of R30 is 1/2 times and 3 respectively.
/ 2 times the value.

Next, the first switch decoder circuit 33
Is composed of, for example, a tree-like switch circuit shown in FIG. 2A, and is a successive approximation register (not shown; FIG. 9).
Addresses A3 to A7 supplied from
, One of the 32 voltage dividing terminals 1 to 31 including GND, which is divided by the resistance ladder circuit 32, is selected, and the voltage is output as the D / A conversion circuit output voltage V _DA . Note that the first switch decoder circuit 33 is not limited to the above-mentioned tree-like switch circuit, and may be configured by, for example, a matrix-like switch circuit.

Next, the second switch decoder circuit 50
Is an input terminal (voltage dividing terminal), for example, as shown in FIG.
CMOS switches CM21, CM22, CM23 for connecting one of 20, 20, and 12 to output terminal 101
And one of the voltage dividing terminals 18, 16, 14 is connected to the output terminal 1
02 connected to the CMOS switches CM31, CM32,
CM33 and a CMOS switch CM4 connecting one of the input terminals 17, 16, and 15 to the output terminal 103
1, CM42 and CM43.

The selection control operation of the first and second switch decoder circuits 33 and 50 is performed according to a combination of lower addresses A0 to A2 from a successive approximation register (not shown) as shown in Table 1. Control signal DC output as
K21, DCK22, DCK23, DCK31, DCK
32, DCK33, DCK41, DCK42, DCK4
3 is performed.

[0018]

[Table 1]

Here, the element represented by the symbol CMn is CM
As an OS switch, this CMOS switch is composed of NMOS transistors NM1 and P, as shown in the lower right of FIG.
It is constituted by a parallel circuit of the MOS transistor PM1 and the inverter gate 40. When the signal of the gate electrode 38 is at "H" level, it is turned on to transmit the signal of the input terminal 37 to the output terminal 39 and when it is at "L" Is turned off.

Next, the operation of the basic example of FIG. 1 will be described. In the following description, the successive approximation operation of the upper 5 bits will be described first, and then the successive comparison operation of the lower 3 bits will be described.

During the first successive approximation operation of the upper 5 bits,
The output control signals DCK22, DCK32, DCK42 are kept at "H". Therefore, the CMOS switch C
Since M22, CM32, and CM42 are turned on, the voltage of the voltage dividing terminal 16 of the resistance ladder circuit 32 is output to the terminals 101, 102, and 103. Here, it is assumed that CMOS switches not specifically mentioned are in an off state. The other side of the sampling capacitor C1 (right end in the figure)
The voltage at the sampling period of the terminal 35 and V _SA of,
A voltage in a comparison period described later is defined as _VCO .

First, the sampling clock SCK is set to "H" to turn on the CMOS switches CM1 and CM3, and one terminal (left end in the figure) of the sampling capacitor C1 is connected to the analog unknown input V _IN. Input V _IN
Charge (sampling period). At this time, since the input / output terminal of the inverter gate 34 is short-circuited by the CMOS switch CM3, the voltage V _SA 1 of the terminal 35
Is fixed to a constant bias voltage VB. Next, the comparison clock RCK is set to “H” (sampling clock SCK =
"L") to turn on CM2, and set the sampling capacity C
The comparison operation is performed by transmitting the D / A conversion circuit output _VDA to one of the terminals (comparison period). Voltage V _CO terminal 35 at this time is in the period from the sampling period to the comparison period, the charge amount of the sampling capacitor C1 does not change, changes as represented by the following formula. Change in _{V CO -V SA = C1 (V} DA -V IN) / (C1 + C2 + C3 + C4) ...... ...... (1) The voltage V _CO is amplified by multistage inverter gate (only the first-stage inverter gates 34), the last stage The logic amplitude is determined at the inverter gate output terminal (not shown). At this time, the resistance ladder circuit terminals 101, 102, and 103 of the capacitors C2, C3, and C4 are kept at a constant voltage during the upper 5 bits successive approximation mode, so that the comparison results are not affected.

The same sampling / comparison operation is repeated five times in total according to the successive approximation sequence while changing the addresses A3 to A7, whereby the A / D result of the upper 5 bits can be obtained. This result is reflected on the addresses A3 to A7 after the end of the fifth sampling / comparison operation.

Next, the (second) successive approximation operation of the lower three bits is performed. During the 3-bit successive approximation operation, the upper addresses A3 to A7 are fixed to the final result, and the sampling / comparison operation is performed. Then, as in the case of the successive approximation operation of the upper 5 bits, during the sampling period,
The CMOS switches CM22, CM32, and CM42 in the second switch decoder circuit 50 are turned on, and the voltage V of the voltage dividing terminal 16 is commonly applied to the capacitors C2, C3, and C4.
d1 is transmitted.

For example, in the case of the comparison period of the third bit from the least significant bit, after performing the same sampling operation as described above, C
The MOS switches CM2 and CM21 (or CM23, which are determined by the previous successive comparison result of the fifth bit from the most significant bit) are turned on, and the capacitors C1 and C2 have the D / A conversion circuit output V _DA and Terminal 20 (or terminal 1
Apply the divided voltage of 2). However, the capacitors C3 and C4 are kept at the same voltage of the terminal 16.

Here, the terminal 3 during the sampling period
5 is V _SA (= VB), and the voltage of terminal 3 during the comparison period is
The voltages of 5, 101, 102 and 103 are respectively set to V _CO , Vd
2, Vd3 and Vd4, the voltage change V _{CO of the} terminal 35
−V _SA is represented by the following equation.

[0027] _{V CO -V SA = C1 (V} DA -V IN) / ΣCi + C2 (Vd2-Vd1) / ΣCi + C3 (Vd3-Vd1) / ΣCi + C4 (Vd4-Vd1) / ΣCi ...... ...... (2) Here, assuming that C1 = C and C2 = C3 = C4 = C / 8, the voltage change V _CO −V _SA is expressed by the following equation.

V _CO −V _SA = (8/11) {(V _DA −V _IN ) + (Vd 2 −Vd 1) / 8 + (Vd 3 −Vd 1) / 8 + (Vd 4 −Vd 1) / 8} (3) between the terminals 16 and 20, and is between the terminals 16 and 12, there is a potential difference of each + 4V _LSB and -4 V _LSB (resolution voltage V _LSB is 5 bits), between the terminals 16 and 18, and terminals 16
If Between 14, respectively + 2V _LSB, there is a potential difference of -2 V _LSB, and a between terminals 16 and 17, respectively between the terminals 16 and 15 + V _LSB, because there is a potential difference of -V _LSB, equation
The second term in (3) is a weight of ± _VLSB / 2, and the third term is ± _VLSB
The fourth term changes with a weight of / 4 and the fourth term changes with a weight of ± V _LSB / 8, and the successive approximation operation is performed. In this comparison period, the third and fourth terms in equation (3) are "0", which means that only the first and second terms are calculated.

In the successive approximation operation, similarly to the ordinary successive approximation operation, the output control signal DCK2 is appropriately adjusted according to the change of the addresses A0 to A2 based on the comparison result of the comparator.
1, DCK22, DCK23, DCK31, DCK3
2, DCK33, DCK41, DCK42, DCK43
This is accomplished by changing Then, by repeating such sampling / comparison operation three times, the logical value of the lower three bits is determined, and the 8-bit A / D conversion operation is completed.

Therefore, according to the basic example of FIG. 1, when the resolution is 8 bits, only 32 resistor elements, 4 capacitors and a small selection switch are required, and as a result, the accuracy is reduced. And the size can be sufficiently reduced. Further, according to this basic example , since the capacitance of the weighting capacitor may be two types of 1: 8, the configuration is simple.

In the above embodiment, the case where the A / D converter has a resolution of 8 bits has been described as an example. However, it is not necessary to limit the resolution to 8 bits. It is clear that is feasible. Further, the configuration of the voltage dividing terminal and the weighting capacitor of the resistance ladder circuit is not limited to this embodiment. For example, a voltage between adjacent voltage dividing terminals of the resistance ladder circuit 32 is extracted, and C1: C2: C3: C4. It is apparent that a configuration in which the voltage is divided at a capacity ratio of 1: 1: 2: 4: 8 may be adopted.

Further, when configured as an LSI chip, the present invention is not limited to a dedicated LSI having only an A / D converter function, including the embodiments described below.
One-chip microcomputer L with D converter
It may be SI.

Next, an embodiment of the present invention will be described.
FIG. 3 shows a first embodiment of the present invention. In the following, including this embodiment, the same or equivalent components as those described above will be denoted by the same reference numerals. Example of Figure 3, which was corresponding to claim 3 of the appended claims, reference voltage source
(Not shown), a first 5-bit resistor ladder circuit 32 and a first switch decoder circuit 33 forming a first D / A conversion circuit, and a second forming a second D / A conversion circuit. A 3-bit resistor ladder circuit 53, a second switch decoder circuit 50, a sampling capacitor C1, and weighting capacitors C2 and CMO designed to have a capacitance value of 1/8 of the capacitor C1.
It comprises S switches CM1 to CM4 and a non-inverting differential amplifier 54.

The first 5-bit resistance ladder circuit 32 has equal resistance elements R1 to R30 each having a resistance value of a unit resistance R.
And a resistance element R having a resistance value of R / 2 and 3R / 2, respectively.
0 and R31. However, the resistance element R8 is composed of four unit resistors. The second 3-bit resistance ladder circuit 53 includes six equal resistance elements R201 to R206, and resistance elements R200 having resistance values of R / 2 and 3R / 2, respectively.
R207.

The first switch decoder circuit 33 and the second switch decoder circuit 50 correspond to those shown in FIG.
Or a matrix switch circuit, or a circuit composed of an address decoder and a voltage division terminal selection MOS switch group.

In this embodiment, a resistance element R8 is formed by connecting two series circuits composed of two unit resistors in parallel, and the intermediate terminal of the series circuit is connected to the non-inverting terminal 36 of the differential amplifier 54. Therefore, the voltage of the non-inverting terminal (voltage dividing terminal) 36 is a voltage V _REF / 4 (V _REF is a first reference voltage value) corresponding to a voltage between the resistance terminals of 8R. ).

Therefore, the output voltage value of the differential amplifier 54, that is, the second reference voltage value V _REF2 becomes substantially V _REF / 4, and the 3-bit voltage dividing terminal voltage of the second resistor ladder circuit 53 becomes the second voltage. The signal is transmitted to the capacitor C2 via the switch decoder circuit 50. As described above, this capacitance C
The capacitance value of 2 is set to 1/8 of the capacitance C1.

Next, the operation of the embodiment of FIG. 3 will be described. Since the operation of this embodiment is basically the same as that of the embodiment shown in FIG. 1, only the characteristic features of this embodiment will be described below.

In the sampling period, the sampling clock SCK and the comparison clock RCK both become "H", and the CMOS switches CM1, CM3, CM4 are in the ON state. At this time, the address signals A0 to A2 are all "0", and therefore, the terminal voltage GND (ground) is output from the output terminal 51 of the second switch decoder circuit 50.

In the first comparison period in the successive approximation operation of the lower three bits, (A2, A1, A0) = (1,
0, 0), so that the second switch decoder circuit 50 has the divided voltage 44 at the middle point of the second resistance ladder circuit 53.
(Not shown) to the other end of the capacitor C2 via the CMOS switch CM4.

At this time, the voltage change V _CO −V _{SA at the} terminal 35
Is expressed by the following equation, as is apparent from equations (2) and (3). V _CO −V _SA = (8/9) [{(V _DA + V _REF * d / (2 ³ * 2 ² )} − V _IN ) (4) where d is determined by the second ladder resistance circuit. Represents the voltage division ratio (output coefficient) and varies in units of 1/2 ³ .

The sum of the first and second terms in this equation is the output voltage value of the D / A conversion circuit, and is the minimum of 1/2 ⁵ and 1/2 ⁸ with respect to the reference voltage V _REF , respectively. It changes with the resolution, and the successive comparison with the input voltage V _IN is performed.

Therefore, according to this embodiment, in addition to the fact that the circuit scale can be reduced, the resistance ladder circuit is buffered by the differential amplifier, so that the resistance value can be set independently and freely. is there.

Next, a second embodiment of the present invention is shown in FIG. The embodiment of FIG. 4 corresponds to claim 2 of the present invention, and the first D / A conversion circuit comprises a first D / A conversion circuit.
Resistance ladder circuit 32 and first switch decoder circuit 3
3. The second resistor ladder circuit 53 and the second switch decoder circuit 50 constituting the second D / A conversion circuit,
It comprises switches CM1 to CM4, a sampling capacitor C1, a weighting capacitor C5 having a capacitance value of 1/4 of the capacitor C1, and a logical inverter gate 34. Configurations that are not particularly mentioned are the same as or equivalent to those described above, and a description thereof will be omitted.

The second resistance ladder circuit 53 is composed of a series resistance circuit of nine resistance elements RT0 to RT8.
The second switch decoder circuit 50 is the one shown in FIG. 5, and as shown in FIG.
NM10 and an address decoder circuit 52, and selects one of the voltage dividing terminals 41 to 49 of the second resistance ladder circuit 53 according to a combination of the address signals A0, A1, and A2. It is output from the output terminal 51.

In the embodiment shown in FIG. 4, the first ladder resistance circuit 32 includes, as lower bits, a voltage dividing resistor composed of resistance elements R1 to R4 having a resistance value 2R and a resistance element R0 having a unit resistance value R. And a resistance element RT0 having a unit resistance value R
Using a second ladder resistance circuit 53 composed of RT8,
The second ladder resistor circuit 53 is connected in parallel to the lower-order bit voltage dividing resistor of the ladder resistor circuit 32, thereby providing the voltage dividing terminals 1 to 5 of the first resistor ladder circuit 32.
Is designed to be able to generate a voltage in increments of 5 bits of resolution without being affected by the connection of the second resistance ladder circuit 53, The voltage terminals 41 to 49 are capable of generating a potential difference of V _LSB / 2 unit, assuming that the resolution voltage of the upper 5 bits is V _LSB .

The output terminal 51 remains at the potential of the voltage dividing terminal 45 during the successive approximation operation of the upper 5 bits.
(Address signals A2, A1, A0 = 1, 0, 0) Since this is the same as that described above, the successive approximation operation of the lower three bits will be described below. During the successive approximation operation of the lower three bits, the addresses A3 to A7 are fixed to the address values reflecting the A / D conversion result by the upper five bits. For example, in the successive comparison of the third bit from the least significant bit, the sampling period (SCK = “H”, RCK =
For “L”, RCK2 = “H”), the central voltage dividing point 45 is selected in the same manner as described above.

Next, the comparison period (SCK = "L", RCK
= "H", RCK2 = "H"), the voltage dividing terminal 49 (address signals A2, A1, A0) based on the previous comparison result.
= 1, 1, 1) or the voltage dividing terminal 41 (address signal A2,
A1, A0 = 0, 0, 0) is selected. At this time, due to the voltage division of the resistor ladder circuit 50 and the capacitor C5, the terminal 3
5 has a variation of ± _VLSB / 2, and the comparison operation is performed.

In the comparison period of the second bit from the lower order, the voltage dividing terminal 47 (or the voltage dividing terminal 43) is selected, and + V _LSB / 4
(Or −V _LSB / 4) appears, and at the time of the least significant bit comparison, the voltage dividing terminal 46 (or the voltage dividing terminal 44) is selected.
Fluctuation of V _LSB / 8 (or -V _LSB / 8) appears. Therefore,
These fluctuations are added to the D / A conversion circuit output V _DA ,
The A / D conversion operation is obtained by comparison with the unknown input signal voltage V _IN .

Therefore, according to the embodiment of FIG. 4, in the case of an 8-bit A / D converter, the number of unit resistances (resistance values R) is 36 for the first ladder resistor, and 9 in resistance
A total of 45 capacitors is required, and only two capacitors are required. Further, since the configuration can be made only by the combination of the same unit resistors, there is a characteristic that the error fluctuation of the voltage dividing terminal can be reduced. Although this can be said in other embodiments, the layout of ICs (semiconductor integrated circuit devices) can be configured by repeatedly arranging resistors of the same shape. This is because the fluctuations of are suppressed to be small.

Next, FIG. 6 shows that the second ladder resistance circuit 50 is replaced with the first ladder resistance circuit 32 in the embodiment of FIG.
This embodiment corresponds to claim 4 of the claims when connected in parallel to the central portion of
The operation is the same as that of the embodiment of FIG.
In FIG. 7, only the first and second resistance ladder circuits are shown.

Therefore, in the case of this embodiment, in addition to the effect of the embodiment of FIG.
Since it can be provided in the central portion where resistance variation is small, there is a feature that accuracy can be sufficiently improved. This is because, in an IC, a resistance ladder circuit is generally generated by a diffusion layer resistance, a polysilicon resistance, and the like, and has a resistance variation due to uneven characteristics and distortion on a chip surface. This is because it is often done.

FIG. 7 shows another embodiment of the present invention. Embodiment of the FIG. 7, claim 1 of the appended claims
In the embodiment of FIG. 4, the second resistor ladder circuit 53 is directly connected to the voltage dividing terminal 2 of the first resistor ladder circuit 32. , CMOS switches CM5 to CM7 and the capacitance value of sampling capacitor C1,
The capacitors C6, C7, and C8 having weights of ／ and １ ／ are provided. Therefore, in this embodiment, a ladder resistance circuit that sees the ground side from the voltage dividing terminal 2 is a parallel circuit having a resistance value of 3R. And as a result, the terminals 71 and 7
2 and the voltage between terminals 71 and 70 are +
VLSB / 2 and -VLSB / 2.

The second switch decoder circuit 50
Is composed of nine NMOS transistors NM11 to NM19 and an address decoder 69.
According to the combination of 0 to A2, the output signal group 73 from the address decoder 69 is output from the NMOS transistor NM11.
To NM19, thereby turning on any three sets of NMOS switches. In the sampling period, the NMOS transistors NM12 and NM1
5. The MN 18 is turned on, and the voltage of the voltage dividing terminal 71 is output from the output terminals 101, 102, and 103.

By the way, also in this embodiment, the successive approximation operation of the upper 5 bits is the same as in each of the above-described embodiments.
Hereinafter, the successive approximation operation of the lower three bits will be described.
During the comparison period, the voltage dividing terminal 72,
Alternatively, the voltage dividing terminal 70 is selectively output, divided by the weighting capacitor, and successively compared with the input voltage V _IN . That is, the voltage V _LSB / 2 generated by the second resistance ladder circuit 53 is _added to the weighting capacitors C6, C7, C8.
Divided by ± _VLSB / 2, ± _VLSB / 4,
The signal is transmitted to the terminal 35 with a resolution of ± V _LSB / 8.

Therefore, according to this embodiment, the unit resistance
Since the number of (resistance value R) is 36 and only four capacitance elements are required (in the case of 8 bits), the size can be sufficiently reduced.

FIG. 8 shows still another embodiment of the present invention. This embodiment corresponds to claim 5 of the present invention. In the embodiment shown in FIG. In which a second reference voltage trimming circuit is added.

What is particularly noteworthy in this embodiment is that the non-inverting differential amplifier 76, the second resistor ladder circuit 53, the second switch decoder circuit 50, the third switch decoder circuit 74, the selected CMOS Switch CM8, C
M9, the sampling capacity C1, and the weighting capacity C9
It is a configuration composed of each part of the above.

First, the second resistor ladder circuit 53 connects a resistor string (resistance value 4R) composed of four unit resistors in parallel near the intermediate voltage dividing terminal to a divided voltage terminal for trimming. 78 to 82 are obtained, so that the second reference voltage V
A voltage trimmed with a precision of 1/8 × １ ／ = 1/32 with respect to _REF2 can be taken out.

Next, a negative feedback acts on the differential amplifier 76 via the second resistance ladder circuit 53 and the third switch decoder circuit 74, whereby the voltage at the terminal 77 is reduced. , And is controlled to be equal to the voltage value of the voltage dividing terminal 1 of the first resistance ladder circuit 32.

[0061] Here, as described above, the second reference voltage V _REF2 is adapted to be adjusted by trimming the address signal 75, thereby, the second reference voltage value this voltage V _REF2 is desired Is set to.
The trimming operation using the address signal 75 is performed as follows.
This is performed while monitoring the voltage _{VREF2 of the} terminal 77 externally.

In the successive approximation operation of the lower 3 bits, the sampling period is the clock DCK1 = “H” and the CMO
The S switch CM9 is turned on, and the D / A of the capacitor C9 is
The terminal on the conversion circuit side is fixed to the ground potential. Next, during the comparison period, the clocks DCK2 = “H” and RCK = “H”
Then, the CMOS switches CM2 and CM8 are turned on to perform the comparison operation. The other operations are the same as those in the above-described embodiment of FIG.

According to this embodiment, the number of elements can be reduced, and the function of trimming the second reference voltage from the outside can be easily obtained. Further, in this embodiment, since the variable resistor for trimming also serves as the second resistor ladder circuit, the size can be reduced.

In the above embodiment, it is apparent that the parallel circuits of the unit resistance row may connect the corresponding voltage dividing terminals of the respective parallel circuits (the equivalent voltage dividing ratio does not change).

According to the present invention, a high-precision and small-sized A / D converter can be easily obtained as is clear from the above embodiments. On the other hand, microcomputers often require an A / D converter when used. Therefore, if the A / D converter according to the present invention is mounted on the same LSI as the microcomputer, a small-sized and high-performance microcomputer can be easily obtained.

[0066]

According to the present invention, the number of resistor ladders and weighting capacitors can be reduced without lowering the accuracy, so that the circuit scale can be reduced.
When an IC is used, the area occupied by the A / D converter module can be reduced, and the number of obtained chips can be increased. Therefore, a low-cost, high-precision A / D converter can be provided.

Further, according to the present invention, since the resistance ladder can be constituted by a repetitive layout of unit resistances, high precision can be easily obtained.

Further, according to the present invention, since trimming can be performed arbitrarily, a high-precision A / D converter can be easily realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an A / D converter according to the present invention.

FIG. 2 is a circuit diagram showing an example of a switch decoder circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram of an A / D converter according to a second embodiment of the A / D converter according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the A / D converter according to the present invention.

FIG. 5 is a circuit diagram showing another example of the switch decoder circuit in the embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the A / D converter according to the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the A / D converter according to the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the A / D converter according to the present invention.

FIG. 9 is a circuit configuration diagram showing a conventional example of an A / D converter.

[Explanation of symbols]

32 first resistor ladder circuit 33 first switch decoder circuit 34 inverter gate 50 second switch decoder circuit 53 second resistor ladder circuit 54, 76 non-inverting differential amplifier 74 third switch decoder circuit CM1 to CM9 , CM21, CM22, CM23, CM
31, CM32, CM33, CM41, CM42, CM
43 CMOS switches C1 to C9 Capacitance elements (capacitors) R0 to R31 Resistance elements R200 to R207 forming a first resistance ladder circuit, RT0 to RT11 Resistance elements forming a second resistance ladder circuit NM1 to NM19 NMOS switches PM1 PMOS switch

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-133424 (JP, A) JP-A-60-132422 (JP, A) JP-A-62-94024 (JP, A) 103941 (JP, U) (58) Fields studied (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (6)

(57) [Claims] 1. A comparison voltage generation circuit, comprising: a comparator which uses the output of the comparison voltage generation circuit and an analog input voltage as one input and the other input, respectively, and outputs the output of the comparison voltage generation circuit in accordance with the output of the comparator In a successive approximation type analog-to-digital converter of a method of successively switching voltages, the comparison voltage generation circuit is divided into a reference voltage to generate a plurality of divided voltages; A first switch decoder circuit for selecting and outputting the divided voltage according to the output of the comparator; a sampling capacitor connected between the output of the first switch decoder circuit and one input of the comparator; A resistor ladder circuit for further dividing a part of the divided voltage of the equal resistance voltage dividing circuit, and a divided voltage of the resistor ladder circuit corresponding to the output of the comparator. A second switch decoder circuit for selecting and outputting the same, and a weighting capacitance element group for adding / subtracting the output of the second switch decoder circuit to / from the voltage of the sampling capacitance element. A successive approximation operation of the upper bit group using the output voltage as a comparison voltage is compared with a voltage obtained by adding / subtracting the output voltage of the second switch decoder circuit to / from the output voltage of the first switch decoder circuit via the weighted capacitance element group. An analog-to-digital converter configured to sequentially perform a successive approximation operation of a lower bit group as a voltage. 2. A comparison voltage generation circuit comprising: a comparison voltage generation circuit; and a comparator having an output of the comparison voltage generation circuit and an analog input voltage as one input and the other input, respectively, and an output of the comparison voltage generation circuit according to an output of the comparator. A successive approximation type analog / digital converter of a system for successively switching between a reference voltage generating circuit and a first resistor voltage dividing circuit for dividing a reference voltage to generate a plurality of divided voltages; A first switch decoder circuit for selecting and outputting a first divided voltage of the voltage dividing circuit in accordance with an output of the comparator; and a second reference for dividing a part of the divided voltage of the first resistive voltage dividing circuit into a second reference A second resistor voltage dividing circuit that divides the second reference voltage to generate a plurality of second divided voltages; and outputs the divided voltage of the second resistor voltage dividing circuit to the output of the comparator. Select and output according to Composed of a second switch decoder circuit, the successive comparison operation of the upper bit group that comparison voltage the output voltage of the first switching decoder circuit, the first
And a successive approximation operation of a lower bit group using a voltage obtained by adding or subtracting the output voltage of the second voltage divider circuit to or from the output voltage of the switch decoder circuit as a comparison voltage. Digital converter. 3. The voltage dividing circuit according to claim 2, wherein the second reference voltage is converted from a part of the divided voltage of the first resistor voltage dividing circuit via a buffer amplifier to the second resistor voltage dividing circuit. An analog-to-digital converter configured to be supplied to 4. The voltage dividing circuit according to claim 2, wherein the second reference voltage is supplied to two voltage dividing terminals on both sides near a center of the first resistor voltage dividing circuit. An analog-to-digital converter characterized in that the two terminals of the circuit are connected in parallel so that the two terminals are supplied to the second resistor voltage dividing circuit. 5. The invention according to claim 2, wherein the second reference voltage is supplied to the first reference voltage via one input of a differential amplifier.
And a trimming voltage is supplied to the other input of the differential amplifier from a part of the divided voltage of the resistor voltage dividing circuit. Analog-to-digital converter. 6. A microcomputer comprising the analog / digital converter according to claim 1.