JP3292070B2 - D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high resolution D / A converter, and more particularly to a D / A converter which has a small circuit scale and is effective for integrating a multi-channel input type D / A converter.

[0002]

2. Description of the Related Art As a method of constructing a conventional high-resolution D / A converter, "current-weighted D / A converter", "R-2
There are “R-type D / A converter”, “PWM-type D / A converter”, and “ΣΔ D / A converter”.

[0003] "Current weighted D / A converter" and "R-
The "2R D / A converter" can output a high-resolution analog output at high speed, while the "PWM D / A converter" and the "変 換 Δ D / A converter" require high-precision elements. There is a feature that it is unnecessary and inexpensive.

However, in the former method, a high-precision resistor is required to obtain monotonicity, and the cost is increased. On the other hand, the latter has a problem in that it is a dynamic type requiring a clock, has a lot of noise, and is slow.

Further, there is a "tap method" as a method having good monotonicity. However, if the resolution is increased, the circuit scale becomes large, which poses a practical problem. As a method of suppressing this circuit scale increase, "Peter Holloway," A Trimless 16b Digital
Potentiometer ", 1984 IEEE International Solid-State
Circuits Conference. ".

However, in this system, since the LSB stage is also of the "tap system", a ladder resistor is required, and in the case of a multi-channel input type D / A converter, it is difficult to obtain the effect of suppressing the circuit scale. Therefore, an object of the present invention is to realize a D / A converter having good monotonicity and a small circuit scale.

[0006]

In order to achieve the above object, according to a first aspect of the present invention, an upper bit conversion circuit and a lower bit conversion circuit are separated so that the upper bit conversion circuit and the lower bit conversion circuit are separated from each other. In a D / A converter that increases the resolution by adding the output of a conversion circuit, a reference voltage source and a
A resistor array that divides the output voltage of the quasi-voltage source and an upper bit
Divided by the resistor array based on the digital input signal
The first switch circuit that selects and outputs the applied voltage
An upper bit conversion circuit comprising:
The first difference in which the output voltage of the conversion circuit is applied to one input terminal
Dynamic circuit and the mutual conductance of the first differential circuit.
The transconductance is weighted and one input terminal
A plurality of second differential circuits, each of which is grounded;
The two current outputs of the differential circuit are the inverting input terminal and
Outputs analog output signal connected to non-inverting input terminal
And its analog output signal is the other of the first differential circuit.
The operational amplifier that is fed back to the input terminal of
The other of the second differential circuit based on the digital input signal.
A second switch circuit that applies a reference voltage to the input terminal
And a lower bit conversion circuit composed of

[0007]

[0008]

[0009]

[0010]

[0011]

[0012]

[0013]

[0014]

By using the "tap method" for the upper bits, the monotonicity is improved, and for the lower bits, "current weighting" is used to reduce the number of switch circuits for selecting taps and reduce the circuit scale.

In the case where a plurality of D / A converters are integrated, the power consumption can be reduced because the resistor array can be shared.
An increase in circuit scale can also be suppressed. Further, when performing automatic calibration, the calibration data can be shared, so that the storage circuit capacity can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a D / A converter according to the present invention. Here, for simplicity, a 4-bit D /
2 illustrates an A converter.

In FIG. 1, reference numeral 1 denotes a reference voltage source, 2a, 2
b, 2c and 2d are resistors, 3a, 3b, 3c, 3d, 3
e, 3f, 3g and 3h are switch circuits, 4a and 4b
Is a NOT circuit, 5, 6 and 7 are differential circuits composed of a pair of transistors and a constant current source, and 8 is an operational amplifier.

Also, 100 is an analog output signal, 10
1, 102, 103 and 104 are digital input signals, respectively, and 101 is an MSB (Most Significant Bi
t) and 104 are LSB (Least Significant Bit).

Here, 1, 2a to 2d, 3a to 3f and 4a to 4b constitute an upper bit conversion circuit 50, and 3g, 3h and 5 to 8 constitute a lower bit conversion circuit 51, respectively.

One end of the constant voltage source 1 is connected to one end of a resistor 2a, and the other end of the resistor 2a is connected to one end of a switch circuit 3a and one end of a resistor 2b. The other end of the resistor 2b is connected to one end of the switch circuit 3b and one end of the resistor 2c.

The other end of the resistor 2c is connected to one end of the switch circuit 3c, one end of the resistor 2d, and one input terminal of the switch circuits 3g and 3h.

The other end of the switch circuit 3a is connected to the other end of the switch circuit 3b and one end of the switch circuit 3e, and the other end of the switch circuit 3c is connected to the other end of the switch circuit 3d and one end of the switch circuit 3f. You.

The other end of the switch circuit 3e is connected to the switch circuit 3
f and one input terminal of the differential circuit 5,
One output of the differential circuit 5 is connected to one output of the differential circuits 6 and 7 and the inverting input terminal of the operational amplifier 8, respectively.

The other output of the differential circuit 5 is connected to the other output of the differential circuits 6 and 7 and the non-inverting input terminal of the operational amplifier 8, respectively.

The output of the operational amplifier 8 is the analog output signal 1
00 and is connected to the other input terminal of the differential circuit 5. One input terminals of the differential circuits 6 and 7 are connected to output terminals of the switch circuits 3g and 3h, respectively.

The digital signal input 101 is connected to the control terminal of the switch circuit 3e and the NOT circuit 4b.
The output of the NOT circuit 4b is connected to the control terminal of the switch circuit 3f.

The digital signal input 102 is connected to the control terminals of the switch circuits 3a and 3c and the NOT circuit 4a, and the output of the NOT circuit 4a is connected to the switch circuits 3b and 3d.
Is connected to the control terminal.

Also, digital signal inputs 103 and 10
Reference numeral 4 is connected to the control terminals of the switch circuits 3g and 3h, respectively.

Further, the other end of the constant voltage source 1, the other end of the resistor 2d, the other end of the switch circuit 3d, the switch circuits 3g and 3
The other input terminal of h and the other input terminals of the differential circuits 6 and 7 are grounded.

Here, the operation of the embodiment shown in FIG. 1 will be described. Digital input signals 101 and 1 which are upper bits
02 is ON / OFF of the switch circuits 3a to 3f respectively.
Control.

Assuming that the output voltage of the constant voltage source 1 is "Vref", the voltage is equally divided by the resistors 2a to 2d, so that the switch circuits 3a, 3b, 3c and 3d respectively have "
3/4 Vref "," 2/4 Vref "," 1/4
Vref "and" 0 / 4.Vref "are applied.

Therefore, the digital input signals 101 and 1
If 02 is “1” and “1”, the switch circuits 3a,
3c and 3e are "ON", the switch circuits 3b, 3d and 3f are "OFF", and a voltage of "3/4 Vref" is applied to one input terminal of the differential circuit 5.

Since the analog output signal 100 is fed back to the other input terminal of the differential circuit 5, the other differential circuit 6
And 7 are inactive, the analog output signal 100 is "
3 / 4.Vref "is output.

Similarly, if the digital input signals 101 and 102 are "1" and "0", the analog output signal 100 is "2/4 Vref" and the digital input signal 10 is
If 1 and 102 are “0” and “1”, “１ ／ · V”
ref "is the digital input signal 101 and 102
If they are "0" and "0", "0 / 4.Vref" will be output respectively.

On the other hand, the digital input signals 103 and 104, which are lower bits, are supplied to switch circuits 3g and 3g, respectively.
h. When the digital input signals 103 and 104 are “1”, the switch circuits 3 g and 3 h output “１ ／ · V”.
ref ", and if" 0 ", a ground level, in other words," 0 / 4.Vref "is selected.

The differential circuits 5, 6 and 7 have transconductances of "4 gm", "2 gm" and "g", respectively.
m ”, the output current of the constant current source and the size of the transistor constituting each differential circuit are“ 4I, 4 ”.
W "," 2I, 2W ", and" I, W ".

Therefore, the digital input signals 103 and 1
If "04" is "1" and "0", "1" is applied only to the differential circuit 6.
/ 4 · Vref ”is applied, and a difference of“ 2 gm × １ ／ · Vref ”is generated between the respective output drain currents of the differential circuit 6.

Here, if the digital input signals 101 and 102 as the upper bits are both "0", one input voltage of the differential circuit 5 is "0 / 4.Vref". The differential output current output to the operational amplifier 8 is “2 gm × １ ／ · Vref”.

However, the input value between the two inputs of the operational amplifier 8 must be equal, and the differential output current output from the differential circuit 5 to the operational amplifier 8 is “−2 gm × １ ／ · Vre
analog output signal 1 so that the drain current of f ″ flows.
00 is controlled.

The transconductance of the differential circuit 5 is “4 g
m ”, the analog output signal“ Vout ”is as follows: Vout = (2 gm × １ ／ · Vref) / 4gm = 2/16 · Vref (1)

For example, if the digital input signals 101 and 102, which are the upper bits, both become "1" in this state, "3 / 4.Vref" is added to the equation (1) as described above. Therefore, Vout = (2/16 + 12/16) · Vref = 14/16 · Vref (2)

Thus, the digital input signal 101
To 104 are “0000”, “0001” to “111”
0 ”and“ 1111 ”, the analog output signal 100 becomes“ 0/16 · Vref ”,“ 1/16 ”
Vref "to" 14/16 Vref "," 15 /
16 Vref "to realize a 4-bit D / A converter.

Therefore, the use of the "tap method" for the upper bits provides good monotonicity, and the use of "current weighting" for the lower bits reduces the number of switch circuits for selecting taps and reduces the circuit scale.

When a plurality of D / A converters are integrated, the power consumption can be reduced and the increase in the circuit scale can be suppressed because a resistor array including the resistors 2a to 2d can be shared. Further, when performing automatic calibration, the calibration data can be shared, so that the storage circuit capacity can be reduced.

As a result, the high-order bit conversion circuit and the low-order bit conversion circuit are separated from each other, the tap method is used as the high-order conversion circuit, and the “current weighting” is used as the low-order conversion circuit. The scale becomes smaller.

As a method of processing the upper bits, not only the "tap method" but also an "R-2R type" or a "current addition type" can be used.

Although the lower bits are weighted by a plurality of differential circuits in the embodiment shown in FIG. 1, the output of a separately provided D / A converter may be applied as the input voltage of one differential circuit. .

FIG. 2 is a circuit diagram showing another embodiment of the D / A converter according to the present invention. In FIG. 2, 8a is an operational amplifier, 9 and 10 are resistor arrays, 11, 12, and 13 are D / A converters by a tap method, 14, 15, and 1.
Reference numeral 6 denotes a differential circuit including a pair of transistors and a constant current source.

Further, 100a is an analog output signal, 10a
5, 106 and 107 are digital input signals, respectively, 105 is the upper bit, 106 is the middle bit, 10
7 indicates the lower bits.

A reference voltage is applied to one end of the resistor array 9, the other end of the resistor array 9 is connected to one end of the resistor array 10, and the other end of the resistor array 10 is grounded.

Each tap voltage of the resistance array 9 is D /
In the A converter 11, each tap voltage of the resistor array 10 is D /
They are connected to A converters 12 and 13, respectively.

The outputs of the D / A converters 11, 12 and 13 are connected to one input terminal of differential circuits 14, 15 and 16, respectively, and the other input terminals of the differential circuits 15 and 16 are grounded. You.

One output of the differential circuit 14 is a differential circuit 15
16 and one input terminal of the operational amplifier 8a. The other output of the differential circuit 14 is connected to the other output of the differential circuits 15 and 16 and the other input terminal of the operational amplifier 8a, respectively.

The operational amplifier 8a receives the analog output signal 100
a and is connected to the other input terminal of the differential circuit 14. Furthermore, digital input signals 105, 106 and 107 are connected to the D / A converters 11, 12 and 13, respectively.

Here, the analog output signal 100a sets the weights of the differential circuits 14, 15 and 16 to "16" and "1".
6 "and" 1 ", and D / A converters 11, 12 and 13
Assuming that the output voltages of “Vmain”, “V2nd” and “V3rd” are respectively, Vout = Vmain + 16/16 · V2nd + 1/16 · V3rd (3)

However, since the resistance values of the resistance arrays 9 and 10 are weighted at "16: 1", D / D
The output values of both the A converter 11 and the D / A converter 12 are “16:
1 ", and D / D as a whole in FIG.
An A converter is configured.

As shown in FIG. 2, when the outputs of the D / A converters 12 and 13 for the middle bit and the lower bit are the voltage of a specific tap of the resistor array 10, the common mode voltage between the differential circuits is Due to the difference, the matching of the transconductance of the transistors constituting each differential circuit deteriorates, and the D / A
The linearity of the converter as a whole also deteriorates.

FIG. 3 is a circuit diagram showing an embodiment of a D / A converter for preventing such deterioration of linearity. In FIG. 3, 8b is an operational amplifier, 17 and 18 are resistor arrays, 19
And 20 are D / A converters using a “tap method”,
Reference numerals 22, 23, 24, 25 and 26 denote differential circuits each including a pair of transistors and a constant current source.
b, 27c and 27d are switch circuits.

Further, 100b is an analog output signal, 10b
8, 109 and 110 are digital input signals, respectively, 108 is the upper bit, 109 is the middle bit, 11
0 indicates each lower bit.

A reference voltage is applied to one end of the resistor array 17, the other end of the resistor array 17 is connected to one end of the resistor array 18, and the other end of the resistor array 18 is grounded.

Each tap voltage of the resistor array 17 is D
/ A converter 19, each tap voltage of resistance array 18 is D
/ A converter 20 respectively.

The output “Vmain” of the D / A converter 19 is connected to one of the input terminals of the differential circuits 21 to 25 and the switch circuit 2.
7a to 27d are respectively connected to one of the input terminals.

Further, the tap voltage “V2nd” adjacent to the tap voltage “Vmain” selected as the output of the D / A converter 19 is connected to the other input terminals of the switch circuits 27a to 27d.

The output “V3rd” of the D / A converter 20 is connected to one input terminal of the differential circuit 26,
The other input terminal is grounded.

One output of the differential circuit 21 is the differential circuit 2
2, 23, 24, 25 and 26 and one input terminal of the operational amplifier 8b. The other output of the differential circuit 21 is output to the differential circuits 22, 23,
24, 25 and 26 and the other input terminal of the operational amplifier 8b.

The operational amplifier 8b receives the analog output signal 100
b and is connected to the other input terminal of the differential circuit 21. Further, digital input signals 108 and 110 are connected to the D / A converters 19 and 20, respectively.
The digital input signal 109 is connected to the switch circuit 27
a to 27d are connected to the control terminals.

With this configuration, there is no difference in the common mode voltage between the differential circuits, and the matching of the mutual conductance of the transistors constituting each differential circuit does not fluctuate. Can be prevented from deteriorating.

However, in the example shown in FIG. 3, the voltage between adjacent taps is not used for the lower bits.

For this reason, although the linearity of the middle-order bit is improved, there is a problem that the difference in the common mode voltage of the lower-order bit deteriorates the linearity.

For example, FIG. 4 is a characteristic curve diagram showing a differential nonlinearity error with respect to the setting code of the embodiment of FIG. As can be seen from FIG. 4, the differential non-linearity error worsens as the setting code increases.

This corresponds to the output “Vma” of the D / A converter 19.
in ”and the voltage difference between the output“ V3rd ”of the D / A converter 20, in other words, the difference between the common mode voltages of the differential circuit 21 and the differential circuit 26 increases, and the differential circuits 21 and 26
This is because an error occurs in the current ratio due to the effect of the output resistance of the constant current source that constitutes.

The matching of the transconductance of the transistors constituting each differential circuit fluctuates due to the error of the current ratio, and the linearity of the D / A converter as a whole deteriorates.

In this case, if the differential circuit 26 for the lower bit is configured in the same manner as the one for the middle bit as shown by the differential circuits 27a to 27d, the linearity is improved because it is not affected by the common mode voltage. However, the circuit scale is dramatically increased.

FIG. 5 is a circuit diagram showing an embodiment of a D / A converter for improving such linearity. In FIG. 5, reference numeral 28 denotes a differential circuit, and other reference numerals are the same as those in FIG.

The connection relationship is almost the same as that of FIG. 3 except that a cascode transistor "c" is provided between a pair of transistors "i" and a constant current source "b" constituting the differential circuit 28. This cascode transistor "
The output “Vmain” of the D / A converter 19 is applied to the gate of “C”.
Is applied.

With this configuration, the voltage between the terminals of the constant current source “b” forming the differential circuit 28 is the same as the voltage between the terminals of the constant current source “d” forming the differential circuit 21. Therefore, the above-described error in the current ratio is improved.

For example, FIG. 6 is a characteristic curve diagram showing the differential nonlinearity error with respect to the setting code of the embodiment of FIG. 5, and as can be seen from FIG. Has been improved.

As a result, a cascode transistor "c" is provided between a pair of transistors "a" and a constant current source "b" which constitute the lower bit differential circuit 28, and the gate of the cascode transistor "c" is provided. D / A converter 19
By applying the output "Vmain", the linearity can be prevented from deteriorating without increasing the circuit scale.

In order to use the “tap method”, the CMO
Although it is appropriate to use the S process, the differential circuit need not be limited to the CMOS process.

[0080]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. By separating the high-order bit conversion circuit and the low-order bit conversion circuit and using “mutual conductance weighting” as the low-order conversion circuit, a D / A converter with good monotonicity and a small circuit scale can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a D / A converter according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the D / A converter according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a D / A converter for preventing deterioration of linearity.

FIG. 4 is a characteristic curve diagram showing a differential nonlinearity error with respect to a setting code in the embodiment of FIG. 3;

FIG. 5 is a circuit diagram showing an embodiment of a D / A converter for improving linearity.

FIG. 6 is a characteristic curve diagram showing a differential nonlinearity error with respect to a setting code in the embodiment of FIG. 5;

[Explanation of symbols]

1 Reference voltage source 2a, 2b, 2c, 2d Resistance 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 2
7a, 27b, 27c, 27d Switch circuit 4a, 4b NOT circuit 5, 6, 7, 14, 15, 16, 21, 22, 23, 2
4, 25, 26, 28 differential circuit 8, 8a, 8b operational amplifier 9, 10, 17, 18 resistor array 11, 12, 13, 19, 20 D / A converter 50 upper bit conversion circuit 51 lower bit conversion circuit 100, 100a, 100b Analog output signals 101, 102, 103, 104, 105, 106, 1
07, 108, 109, 110 Digital input signal

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] A D / A converter for separating a high-order bit conversion circuit and a low-order bit conversion circuit and adding outputs of the high-order bit conversion circuit and the low-order bit conversion circuit to increase the resolution, wherein a reference voltage source is provided. And a resistor for dividing the output voltage of this reference voltage source.
Based on anti-array and digital input signal of upper bit
Selecting and outputting the voltage divided by the resistor array;
Upper bit conversion circuit comprising one switch circuit
And the output voltage of the upper bit conversion circuit is applied to one input terminal.
The first differential circuit to be applied and the mutual
Transconductance is weighted for conductance
A plurality of second differential circuits, one of which is grounded;
The two current outputs of the first and second differential circuits are respectively
Analog output connected to inverting input terminal and non-inverting input terminal
And outputs an analog output signal of the
Operational amplifier fed back to the other input terminal of one differential circuit
Based on the lower-order digital input signal.
2 A second circuit for applying a reference voltage to the other input terminal of the differential circuit
And a lower bit conversion circuit comprising: