JP4600730B2 - IC tester - Google Patents

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JP4600730B2
JP4600730B2 JP2004169309A JP2004169309A JP4600730B2 JP 4600730 B2 JP4600730 B2 JP 4600730B2 JP 2004169309 A JP2004169309 A JP 2004169309A JP 2004169309 A JP2004169309 A JP 2004169309A JP 4600730 B2 JP4600730 B2 JP 4600730B2
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dividing resistor
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converter
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勇 小浦
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Yokogawa Electric Corp
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    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
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Description

本発明は、複数の基準電圧に基づいて、多階調電圧を出力する液晶駆動ドライバを試験するＩＣテスタに関し、精度よく試験が行えるＩＣテスタに関するものである。   The present invention relates to an IC tester that tests a liquid crystal drive driver that outputs a multi-gradation voltage based on a plurality of reference voltages, and to an IC tester that can perform a test with high accuracy.

液晶駆動ドライバは、複数の基準電圧に対して、複数ピンから多段階（多諧調）の比電圧を出力し、液晶ディスプレイの駆動を行っている。このような液晶駆動ドライバを試験するＩＣテスタは、例えば、特許文献１等に記載されている。以下図２を用いて説明する。   The liquid crystal drive driver drives a liquid crystal display by outputting a multi-level (multi-tone) specific voltage from a plurality of pins with respect to a plurality of reference voltages. An IC tester for testing such a liquid crystal drive driver is described in, for example, Patent Document 1 and the like. This will be described below with reference to FIG.

特開平６−３４７１７号公報JP-A-6-34717

図２において、電圧発生部Ｍは、液晶駆動ドライバ（以下ＤＵＴ）の基準電圧ピンのチャネルごとに設けられ、基準電圧を発生する。そして、電圧発生部Ｍは、Ｄ／Ａコンバータ１，２、バッファ３，４、加算部５、アンプ６から構成される。Ｄ／Ａコンバータ１は、制御バスＣＢに接続し、上位ビットを入力し、電圧Ｖ１を基準として、電圧を発生する。Ｄ／Ａコンバータ２は、制御バスＣＢに接続し、下位ビットを入力し、内部電圧Ｖ２を基準として、電圧を発生する。バッファ３は、Ｄ／Ａコンバータ１の出力を入力する。バッファ４は、Ｄ／Ａコンバータ２の出力を入力する。加算部５は、バッファ３，４の出力を加算する。アンプ６は、加算部５の出力を増幅して、ＤＵＴの基準電圧として出力する。   In FIG. 2, a voltage generator M is provided for each channel of a reference voltage pin of a liquid crystal driver (hereinafter referred to as DUT), and generates a reference voltage. The voltage generator M includes D / A converters 1 and 2, buffers 3 and 4, an adder 5, and an amplifier 6. The D / A converter 1 is connected to the control bus CB, receives upper bits, and generates a voltage with reference to the voltage V1. The D / A converter 2 is connected to the control bus CB, receives lower bits, and generates a voltage with reference to the internal voltage V2. The buffer 3 inputs the output of the D / A converter 1. The buffer 4 inputs the output of the D / A converter 2. The adder 5 adds the outputs of the buffers 3 and 4. The amplifier 6 amplifies the output of the adding unit 5 and outputs the amplified output as a DUT reference voltage.

このような装置の動作を以下に説明する。図示しない制御部から制御バスＣＢを介して、電圧データがＤ／Ａコンバータ１，２に入力される。Ｄ／Ａコンバータ１は、上位ビットの電圧データの電圧を、バッファ３を介して、出力する。また、Ｄ／Ａコンバータ２は、下位ビットの電圧データの電圧を、バッファ４を介して、出力する。そして、加算部５が、バッファ３，４の出力を入力し、アンプ６で増幅して、ＤＵＴの基準電圧として、出力する。そして、ＤＵＴは、図示しないデジタル信号発生部からデジタル信号を入力し、基準電圧に基づいて、多階調電圧を出力し、この出力に基づいて、良否の判定が行なわれる。   The operation of such an apparatus will be described below. Voltage data is input to the D / A converters 1 and 2 via a control bus CB from a control unit (not shown). The D / A converter 1 outputs the voltage of the upper bit voltage data via the buffer 3. Further, the D / A converter 2 outputs the voltage of the voltage data of the lower bits via the buffer 4. Then, the adder 5 receives the outputs of the buffers 3 and 4, amplifies them by the amplifier 6, and outputs them as a DUT reference voltage. The DUT receives a digital signal from a digital signal generator (not shown), outputs a multi-gradation voltage based on the reference voltage, and the quality is determined based on this output.

液晶駆動ドライバの基準電圧は、近年の多階調化に伴い、例えば、１８レベルというように、多数レベルが必要である。しかし、Ｄ／Ａコンバータ１，２を用いているので、電圧発生部Ｍのチャンネル間で誤差が生じ、精度よく試験を行うことができないという問題点があった。   The reference voltage of the liquid crystal drive driver requires a large number of levels such as 18 levels with the recent increase in the number of gradations. However, since the D / A converters 1 and 2 are used, an error occurs between the channels of the voltage generation unit M, and there is a problem that the test cannot be performed with high accuracy.

そこで、本発明の目的は、精度よく試験が行えるＩＣテスタを実現することにある。   Accordingly, an object of the present invention is to realize an IC tester capable of performing a test with high accuracy.

このような課題を達成するために、本発明のうち請求項１記載の発明は、
複数の基準電圧ピンの基準電圧に基づいて、多階調電圧を出力する液晶駆動ドライバを試験するＩＣテスタにおいて、
分圧により、複数の電圧を発生する１つの分圧抵抗部と、
前記基準電圧ピンのチャネルごとに設けられ、前記分圧抵抗部の電圧を電圧データの上位ビットにより選択し、出力する複数のマルチプレクサと、
前記基準電圧ピンのチャネルごとに設けられ、前記分圧抵抗部の電圧を基準として、前記電圧データの下位ビットの電圧を発生する複数のＤ／Ａコンバータと、
前記基準電圧ピンのチャネルごとに設けられ、前記Ｄ／Ａコンバータの出力と前記マルチプレクサの出力とを加算し、前記液晶駆動ドライバの基準電圧を出力する複数の加算部と
を備えたことを特徴とするものである。
請求項２記載の発明は、請求項１記載の発明において、
分圧抵抗部は、リファレンス電圧からグランド間を直列に接続された複数の抵抗からなることを特徴とするものである。
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In an IC tester for testing a liquid crystal drive driver that outputs a multi-gradation voltage based on a reference voltage of a plurality of reference voltage pins ,
One voltage dividing resistor that generates a plurality of voltages by voltage division; and
A plurality of multiplexers provided for each channel of the reference voltage pin, for selecting and outputting the voltage of the voltage- dividing resistor unit by upper bits of voltage data;
A plurality of D / A converters provided for each channel of the reference voltage pin and generating a voltage of a lower bit of the voltage data on the basis of the voltage of the voltage dividing resistor unit;
Provided for each channel of the reference voltage pin, comprising a plurality of adders for adding the output of the D / A converter and the output of the multiplexer and outputting the reference voltage of the liquid crystal driver. To do.
The invention according to claim 2 is the invention according to claim 1,
The voltage dividing resistor portion is composed of a plurality of resistors connected in series between the reference voltage and the ground.

本発明によれば、分圧抵抗部の分圧をマルチプレクサが選択し、液晶駆動ドライバの基準電圧とするので、液晶駆動ドライバのピン間の誤差を抑制できる。また、温度ドリフトによる影響は液晶駆動ドライバの基準電圧ピンのすべてに共通するので、電圧比を出力する液晶駆動ドライバにおいては、相対精度が問題となるので、無視することができる。すなわち、精度よく試験を行うことができる。 According to the present invention, since the multiplexer selects the divided voltage of the voltage dividing resistor unit and uses it as the reference voltage of the liquid crystal drive driver, an error between the pins of the liquid crystal drive driver can be suppressed. In addition, since the influence due to the temperature drift is common to all the reference voltage pins of the liquid crystal drive driver, the relative accuracy is a problem in the liquid crystal drive driver that outputs the voltage ratio, and can be ignored. That is, the test can be performed with high accuracy.

また、Ｄ／Ａコンバータが、分圧抵抗部の分圧を基準として、下位ビットの電圧データの電圧を出力し、加算部によりの出力と加算して、液晶駆動ドライバに出力するので、相対精度を維持しつつ、高分解能の出力を精度よく得ることができる。 Also , since the D / A converter outputs the voltage of the lower-order bit voltage data based on the voltage division of the voltage dividing resistor unit, adds it to the output from the adder unit, and outputs it to the liquid crystal drive driver. While maintaining the above, high-resolution output can be obtained with high accuracy.

以下本発明を図面を用いて詳細に説明する。図１は本発明の一実施例を示した構成図である。ここで、図２と同一のものは同一符号を付し説明を省略する。   Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those in FIG.

図１において、分圧抵抗部７は、分圧により、複数の電圧を発生し、抵抗Ｒ１〜Ｒ８からなる。抵抗Ｒ１〜Ｒ８は、リファレンス電圧ＶＲからグランド間を直列に接続され、リファレンス電圧とグランド間の電圧を分圧し、電圧バスＢが各接続点に接続される。マルチプレクサ８は、Ｄ／Ａコンバータ１の代わりに設けられ、制御バスＣＢに接続し、上位ビットを入力し、分圧抵抗部７の電圧を電圧バスＢを介して選択し、バッファ３に出力する。Ｄ／Ａコンバータ９は、制御バスＣＢに接続し、下位ビットを入力し、電圧バスＢを介して、分圧抵抗部７の電圧の１つ、抵抗Ｒ１，Ｒ２の接続点の電位を基準として、電圧をバッファ４に出力する。   In FIG. 1, the voltage dividing resistor unit 7 generates a plurality of voltages by voltage division and includes resistors R1 to R8. The resistors R1 to R8 are connected in series between the ground from the reference voltage VR, divide the voltage between the reference voltage and the ground, and the voltage bus B is connected to each connection point. The multiplexer 8 is provided in place of the D / A converter 1, is connected to the control bus CB, receives the upper bits, selects the voltage of the voltage dividing resistor unit 7 via the voltage bus B, and outputs it to the buffer 3. . The D / A converter 9 is connected to the control bus CB, inputs a lower bit, and is connected to one of the voltages of the voltage dividing resistor 7 and the potential at the connection point of the resistors R1 and R2 via the voltage bus B. The voltage is output to the buffer 4.

そして、バックプレーンボードＢＰはプリント基板で、制御バスＣＢ、電圧バスＢが設けられ、制御バスＣＢを図示しない制御部に接続させる。リファレンス電圧ボードＲＢはプリント基板で、バックプレーンボードＢＰに取り外し可能に接続され、分圧抵抗部７を搭載する。複数の電圧発生ボードＶＢはプリント基板で、バックプレーンボードＢＰに取り外し可能に接続され、複数の電圧発生部Ｍを搭載する。   The backplane board BP is a printed circuit board, provided with a control bus CB and a voltage bus B, and connects the control bus CB to a control unit (not shown). The reference voltage board RB is a printed circuit board, is detachably connected to the backplane board BP, and has the voltage dividing resistor portion 7 mounted thereon. The plurality of voltage generation boards VB are printed circuit boards, are detachably connected to the backplane board BP, and have a plurality of voltage generation units M mounted thereon.

このような装置の動作を以下に説明する。図示しない制御部から制御バスＣＢを介して、電圧データがマルチプレクサ８、Ｄ／Ａコンバータ９に入力される。マルチプレクサ８は、上位ビットの電圧データにより、電圧バスＢを介して、分圧抵抗部６の分圧を選択し、バッファ３を介して、出力する。また、Ｄ／Ａコンバータ９は、下位ビットの電圧データの電圧を、バッファ４を介して、出力する。そして、加算部５が、バッファ３，４の出力を入力し、アンプ６で増幅して、ＤＵＴの基準電圧として、出力する。そして、ＤＵＴは、図示しないデジタル信号発生部からデジタル信号を入力し、基準電圧に基づいて、多階調電圧を出力し、この出力に基づいて、良否の判定が行なわれる。   The operation of such an apparatus will be described below. Voltage data is input to the multiplexer 8 and the D / A converter 9 from a control unit (not shown) via the control bus CB. The multiplexer 8 selects the divided voltage of the voltage dividing resistor unit 6 through the voltage bus B according to the voltage data of the upper bits, and outputs it through the buffer 3. Further, the D / A converter 9 outputs the voltage of the voltage data of the lower bits via the buffer 4. Then, the adder 5 receives the outputs of the buffers 3 and 4, amplifies them by the amplifier 6, and outputs them as a DUT reference voltage. The DUT receives a digital signal from a digital signal generator (not shown), outputs a multi-gradation voltage based on the reference voltage, and the quality is determined based on this output.

このように、分圧抵抗部７の分圧をマルチプレクサ８が選択し、ＤＵＴの基準電圧とするので、ＤＵＴのピン間の誤差を抑制できる。また、温度ドリフトによる影響はＤＵＴの基準電圧ピンのすべてに共通するので、電圧比を出力するＤＵＴにおいては、相対精度が問題となるので、無視することができる。すなわち、精度よく試験を行うことができる。   Thus, since the multiplexer 8 selects the divided voltage of the voltage dividing resistor unit 7 and uses it as the reference voltage of the DUT, an error between the pins of the DUT can be suppressed. Further, since the influence due to the temperature drift is common to all the reference voltage pins of the DUT, the relative accuracy becomes a problem in the DUT that outputs the voltage ratio, and can be ignored. That is, the test can be performed with high accuracy.

また、下位ビットの電位を抵抗分圧により分配せずに、Ｄ／Ａコンバータ９により下位ビットの電位を出力する構成にしたので、下位電位の分配時の配線によるノイズ等の影響を受けることがない。これにより、Ｄ／Ａコンバータ９が、分圧抵抗部７の分圧を基準として、下位ビットの電圧データの電圧を出力し、加算部５によりアンプ３の出力と加算して、ＤＵＴに出力するので、相対精度を維持しつつ、高分解能の出力を精度よく得ることができる。   Further, since the lower bit potential is output by the D / A converter 9 without distributing the lower bit potential by resistance voltage division, the lower bit potential may be affected by noise or the like due to wiring during the lower potential distribution. Absent. Thereby, the D / A converter 9 outputs the voltage of the lower-order bit voltage data with reference to the divided voltage of the voltage dividing resistor unit 7, adds the output of the amplifier 3 with the adder unit 5, and outputs it to the DUT. Therefore, high-resolution output can be obtained with high accuracy while maintaining relative accuracy.

そして、リファレンス電圧ボードＲＢ、電圧発生ボードＶＢをバックプレーンボードＢＰで取り外し可能に構成したので、各ボードの取り替えを容易に行える。   Since the reference voltage board RB and the voltage generation board VB are configured to be removable by the backplane board BP, each board can be easily replaced.

なお、本発明はこれに限定されるものではなく、バッファ３，４を設けた構成を示したが、マルチプレクサ８、Ｄ／Ａコンバータ９が直接加算部５に出力する構成でもよい。   The present invention is not limited to this, and a configuration in which the buffers 3 and 4 are provided is shown. However, a configuration in which the multiplexer 8 and the D / A converter 9 directly output to the adder 5 may be used.

また、Ｄ／Ａコンバータ９は、抵抗Ｒ１，Ｒ２の接続点の電位を基準として、電圧を出力する構成を示したが、分圧抵抗部７の他の電位を用いてもよい。この場合、加算部５までに減衰を行う減衰器を設けたり、バッファ４の代わりに、減衰するアンプを設けたり、あるいは、加算部５で、Ｄ／Ａコンバータ９の出力を減衰して、加算する構成にしてもよい。   The D / A converter 9 is configured to output a voltage with reference to the potential at the connection point of the resistors R1 and R2, but another potential of the voltage dividing resistor unit 7 may be used. In this case, an attenuator for attenuating is provided up to the adding unit 5, an amplifying amplifier is provided instead of the buffer 4, or the output of the D / A converter 9 is attenuated by the adding unit 5 and added. You may make it the structure to carry out.

また、下位ビットのデータを出力するＤ／Ａコンバータ９の代わりに、分圧抵抗部７、マルチプレクサ８と同様に、１つの分圧抵抗部と複数のマルチプレクサを設ける構成でもよい。   Further, instead of the D / A converter 9 that outputs lower-bit data, a configuration in which one voltage dividing resistor unit and a plurality of multiplexers are provided in the same manner as the voltage dividing resistor unit 7 and the multiplexer 8 may be employed.

また、加算部５、アンプ６は、抵抗とオペアンプからなる加算回路により構成してもよい。また、加算部５が、アンプ６を設けずに、増幅を行う構成にしてもよい。   Further, the adding unit 5 and the amplifier 6 may be configured by an adding circuit including a resistor and an operational amplifier. Further, the adder 5 may be configured to perform amplification without providing the amplifier 6.

また、Ｄ／Ａコンバータ９、バッファ４、加算部５、アンプ６を設けた構成を示したが、マルチプレクサ８、バッファ３により、ＤＵＴに基準電圧を出力する構成でもよい。   In addition, although a configuration in which the D / A converter 9, the buffer 4, the adder 5, and the amplifier 6 are provided is shown, a configuration in which the reference voltage is output to the DUT by the multiplexer 8 and the buffer 3 may be used.

本発明の一実施例を示した構成図である。It is the block diagram which showed one Example of this invention. 従来のＩＣテスタの構成を示した図である。It is the figure which showed the structure of the conventional IC tester.

符号の説明Explanation of symbols

５ 加算部
６ アンプ
７ 分圧抵抗部
８ マルチプレクサ
９ Ｄ／Ａコンバータ
Ｂ 電圧バス
ＢＰ バックプレーン
ＲＢ リファンレス電圧ボード
ＶＢ 電圧発生ボード
5 Adder 6 Amplifier 7 Voltage Divider Resistor 8 Multiplexer 9 D / A Converter B Voltage Bus BP Backplane RB Referless Voltage Board VB Voltage Generator Board

Claims (2)

複数の基準電圧ピンの基準電圧に基づいて、多階調電圧を出力する液晶駆動ドライバを試験するＩＣテスタにおいて、
分圧により、複数の電圧を発生する１つの分圧抵抗部と、
前記基準電圧ピンのチャネルごとに設けられ、前記分圧抵抗部の電圧を電圧データの上位ビットにより選択し、出力する複数のマルチプレクサと、
前記基準電圧ピンのチャネルごとに設けられ、前記分圧抵抗部の電圧を基準として、前記電圧データの下位ビットの電圧を発生する複数のＤ／Ａコンバータと、
前記基準電圧ピンのチャネルごとに設けられ、前記Ｄ／Ａコンバータの出力と前記マルチプレクサの出力とを加算し、前記液晶駆動ドライバの基準電圧を出力する複数の加算部と
を備えたことを特徴とするＩＣテスタ。 In an IC tester for testing a liquid crystal drive driver that outputs a multi-gradation voltage based on a reference voltage of a plurality of reference voltage pins ,
One voltage dividing resistor that generates a plurality of voltages by voltage division; and
A plurality of multiplexers provided for each channel of the reference voltage pin, for selecting and outputting the voltage of the voltage- dividing resistor unit by upper bits of voltage data;
A plurality of D / A converters provided for each channel of the reference voltage pin and generating a voltage of a lower bit of the voltage data on the basis of the voltage of the voltage dividing resistor unit;
Provided for each channel of the reference voltage pin, comprising a plurality of adders for adding the output of the D / A converter and the output of the multiplexer and outputting the reference voltage of the liquid crystal driver. IC tester. 分圧抵抗部は、リファレンス電圧からグランド間を直列に接続された複数の抵抗からなることを特徴とする請求項１記載のＩＣテスタ。   2. The IC tester according to claim 1, wherein the voltage dividing resistor portion includes a plurality of resistors connected in series between a reference voltage and a ground.
JP2004169309A 2004-06-08 2004-06-08 IC tester Expired - Fee Related JP4600730B2 (en)

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CN106908971B (en) * 2017-04-28 2019-02-01 南京中电熊猫平板显示科技有限公司 The binding blocking apparatus and its binding hold-up interception method of liquid crystal display panel
KR102374712B1 (en) * 2017-07-03 2022-03-17 삼성전자주식회사 Test interface board having transmission line to merge signals, test system using the same, and test system

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