JPH10142277A - Signal generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operability of inspection and evaluation of a liquid crystal display panel and reduce equipment cost by providing a timing pulse generating circuit or the like for setting the duty ratio, cycle, pulse width and delay time of pulse signals. SOLUTION: A timing pulse generating circuit 22 sets the duty ratio, cycle and amplitude of a first pulse signal, and the pulse width of a second pulse signal and its rising delay time to the first pulse signal. A level data originating circuit 27 sets the voltage level of the first and second pulse signals and a direct current signal, and a data pulse generating circuit 23 synthesizes the output of the timing pulse generating circuit 22 and level data originating circuit 27. Digital-to-analog converters 24, 28 convert the output of the data pulse generating circuit 28 and level data originating circuit 27 respectively into analog signals, and an analog adder 25 adds them. A power amplifier 26 amplifies the output of the adder 25 and outputs it. Basic signals are thus generated individually on low levels, amplified and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator for outputting a drive signal necessary for lighting a liquid crystal display panel when inspecting a display defect, uneven brightness and withstand voltage of a liquid crystal display panel, and evaluating a luminance characteristic.

[0002]

2. Description of the Related Art FIG. 6 is a schematic diagram showing a part of a circuit of a liquid crystal display panel, FIG. 7 is an explanatory diagram of a driving signal for a liquid crystal display panel test, and FIG. 8 is a conventional signal used for testing a liquid crystal display panel. It is a block diagram of a generator.

In FIG. 6, a TFT (thin film transistor) type liquid crystal display panel 1 has a plurality of gate bus lines 2 and a plurality of data bus lines 3 intersecting via an insulating film (not shown), and is disposed near the intersection. TFT4
Has a gate electrode connected to the gate bus line 2, a drain electrode connected to the data bus line 3, and a source electrode connected to the common electrode 6 via the liquid crystal 5.

FIG. 7 shows an inspection of the liquid crystal display panel 1 for defects such as display defects, uneven brightness and withstand voltage, and evaluation of brightness characteristics.
The first pulse signal (data signal) D, the second pulse signal (gate signal) G, and the DC signal (common signal) as shown in FIG.
Apply C.

[0005] The data signal D having a duty ratio of 1 has a cycle of 1 / fd when the frequency of the rectangular pulse is fd, and its amplitude is ± Vd with respect to the center potential Vm. The difference from the potential Vc of the signal C is
It is set to a predetermined value, for example, ± 10V.

In the gate signal G, a rectangular wave having a width Tw and a pulse whose period is 1/2 of that of the data signal D is the data signal D.
The pulse rises slowly for a predetermined time, for example, 0 to 19 ms, and falls quickly. When the high level VgON, the gate of the TFT 4 is turned on, and when the low level VgOFF, the TFT is turned off.
The gate of No. 4 is turned off.

The common signal C is set at a predetermined potential difference, for example, ± 35 V with respect to the pulse center potential Vm of the data signal D. The data signal D, the gate signal G, and the common signal C need to be set in accordance with various liquid crystal display panels 1 having different specifications and their inspection and evaluation purposes.

For this reason, the pulse period 1 of the data signal D
/ Fd, the center potential Vm of the amplitude, the pulse amplitude ± Vd with respect to the center potential Vm, and the ON potential VgO of the gate signal G.
N, the OFF potential VgOFF, the pulse width Tw, and the potential Vc of the common signal C and the difference (Vc−Vm) between the central potential Vm and the potential Vc need to be selectively set in a certain range.

In FIG. 8, a conventional liquid crystal display panel lighting signal generator 7 used for inspection of the liquid crystal display panel 1 and the like is shown.
Used a commercially available pulse generator 8, a synthesizer 9, a DC power supply 10, a DC power supply 11, and a control unit 12, respectively.

The pulse generator 8 has a gate potential Vg
The synthesizer 9 to which the DC power supply 10 is connected transmits the data signal D, and the DC power supply 11 transmits the common signal C.

[0011]

In a signal generator used for inspection of a liquid crystal display panel or the like, it is necessary to set a potential to be driven depending on the type and purpose of the target liquid crystal display panel. For example, when performing a withstand voltage test (gate negative) withstand voltage test (gate positive) normal display test on a certain liquid crystal display panel, even if the potential of the gate signal G is the same,
The potentials of the data signal D and the common signal C are different.

That is, in the above tests, the amplitude center value of the data signal D is 25 V, -25 V, and 0 V at 0 V, and the amplitude (± Vd) with respect to the amplitude center value Vm is varied from 0 to 10 V. Further, the common potential C is 15 to 35 V, and the common potential C is -35 to -1.
At 5 V, the voltage is changed to -10 to +10 V.

Therefore, the data signal D is applied to the signal generator.
And the gate signal G and the common signal C can be set to desired conditions, and the conditions can be easily set and a stable output must be obtained.

However, the conventional signal generator 7 connected and configured with a commercially available general-purpose device such as a pulse generator 8
When setting and changing the data signal D, the gate signal G, and the common signal C, the operability is poor, the steepness of the rising edge of the pulse is likely to be impaired due to mismatching of component devices, and the equipment cost is increased. was there.

[0015]

SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problems by providing a first pulse signal having a duty ratio of 1 and a period and amplitude of a predetermined rectangular wave; The rise is later than the pulse signal by a predetermined time,
A second pulse signal whose fall is fast and the period of the rectangular pulse is １ ／ of the period of the first pulse signal;
A signal generator for transmitting a DC signal having a predetermined difference level with respect to a center level of an amplitude of the first pulse signal, wherein a duty ratio, a cycle and an amplitude of the first pulse signal,
And a timing pulse generating circuit for setting the pulse width of the pulse signal and the delay time of the rise with respect to the first pulse signal, and setting the voltage levels of the first pulse signal, the second pulse signal, and the DC signal. A level data generation circuit, an output signal of the timing pulse generation circuit and an output signal from each of the level data generation circuit, and a data pulse generation circuit for outputting a composite digital signal thereof; A first D / A converter for converting the converted digital signal into an analog signal, a second D / A converter for converting the digital signal output from the level data generation circuit into an analog signal,
And an analog adder for synthesizing the output of the second DA converter, and a power amplifier for amplifying and outputting the output of the analog adder.

The above-described signal generator of the present invention is configured to individually generate, at a low level, a basic signal based on the settings of the amplitude, cycle, relative delay time, and the like of a plurality of signals, and amplify the signal. Therefore, a pulse signal of a high speed and a high voltage can be easily obtained, and a change including a polarity of an offset level (Vm, Vc−Vm) between signals required for operation is easily performed, so that operability is improved, and In addition, equipment costs can be kept low.

[0017]

FIG. 1 is a block diagram showing a configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of a data signal generation process in the device of FIG. 1. FIG. 3 is a diagram showing a data signal generation process of FIG. FIG. 4 is an explanatory diagram of a signal waveform in the apparatus of FIG. 1, and FIG. 5 is an explanatory diagram of a signal waveform in the process of generating a gate signal in FIG.

In FIG. 1, a signal generator 21 includes a timing pulse generator 22, a data pulse generator 23,
It comprises a first DA converter 24, an analog adder 25, a power amplifier 26, a level data creation circuit 27, and a second DA converter 28.

In the timing pulse generation circuit 22 to which the pulse conditions of the data signal D and the gate signal G which are related in time are inputted, the input value without the level value, that is, the pulse period 1 / of the data signal D having the duty ratio 1 is used. When fd (frequency fd), the pulse width Tw of the gate signal G, and the delay time Td of the rise of the gate signal G with respect to the rise of the data signal D are set, a digital pulse of the set value is output to the data pulse generation circuit 23. . In addition,
The pulse cycle of the gate signal G is の of the pulse cycle of the data signal D, and is set simultaneously with the setting of the pulse cycle of the data signal D.

In the level data generating circuit 27, the required potential levels of the data signal D, the gate signal G and the common signal C, and the difference between the amplitude center value Vm level of the pulse of the data signal D and the potential Vc level of the common signal C are determined. (Vc-V
m), the set values of which are 1 / A of the required output when the gain of the power amplifier 26 is A (=
a), that is, + aVd and -aVd for the data signal D
AVm and aVm, and aVgON and aVg
OFF and the common signal C are aVc, and the digital signals are output.

The output from the timing pulse generation circuit 22 and the output from the level data generation circuit 27 are input to the data pulse generation circuit 23.
4, the D / A converter 24 converts the input digital signal into an analog signal, and converts it into an analog adder 25.
Output to

The D / A converter 28 to which the output from the level data creation circuit 27 is input converts the input digital signal to an analog signal, and outputs the analog signal to the analog adder 25. The analog adder 25 adds the analog signals input from the D / A converters 24 and 28 and outputs the added signal to the power amplifier 26. The power amplifier 26 amplifies the signal to a practical level and outputs data having a predetermined time relationship. The signal D, the gate signal G, and the common signal C are output, and the liquid crystal display panel to which the signals are input is turned on.

Next, the generation of the data signal and the gate signal will be described in detail with reference to FIGS. 2, the data pulse generation circuit 23 includes a timing pulse generation circuit 2
2 to the AC signal having the frequency fd of the data signal D, that is, FIG.
As shown in (a), a rectangular wave signal having a frequency fd in which a high level portion H and a low level portion L alternate with the same pulse width, a.Vd data (high level value) from the level data generation circuit 27, and -a. Vd data (low level value) is input. Where a is 1 / A when the gain of the power amplifier 26 is A.
It is.

Then, as shown in FIG. 3B, the data pulse generating circuit 23 converts the data having a high level value of a.Vd and a low level value of -a.Vd into a rectangular wave signal of a predetermined frequency fd. The signals are alternately output in synchronization with each other, and the input digital signal is converted into an analog signal from the DA converter 24 to which the signal is input, and as shown in FIG. ) And low level value (-aVd)
Is output to the analog adder 25.

On the other hand, the digital data of the center value of the amplitude of the data signal D, that is, a · V
The D / A converter 24 to which the digital data of m is inputted is converted into an analog signal, and a signal as shown in FIG. 3D, that is, an analog signal of a · Vm level with respect to 0 level is supplied to the analog adder 25. Input.

Then, from the analog adder 25, FIG.
As shown in (e), a signal whose high level value is a · Vd and whose low level value is −a · Vd is output with respect to the a · Vm level, and the power amplifier 26 that receives the signal outputs a signal centered on the Vm level. As a value, a data signal D having a high level value of Vd and a low level value of -Vd is output.

In FIG. 4, data pulse generating circuit 23
As shown in FIG. 5A, the timing pulse generating circuit 22 generates a pulse signal having a width Tw at a predetermined period, that is, a half period of the pulse period (1 / fd) of the data signal D as shown in FIG.
As shown in (a), the width T is defined by the high level portion H and the low level portion L.
w square wave pulse signal and level data creation circuit 27
VgON data (high level value) and aV
g0FF data (low level value) is input.

Then, as shown in FIG. 5B, the data pulse generating circuit 23 synchronizes the data in which the high level value is a.VgON and the low level value is a.VgOFF with the rectangular wave pulse signal having the width Tw. , And alternately output to the DA converter 24.

Then, the DA converter 24 converts the digital signal input from the data pulse generating circuit 23 into an analog signal, and outputs a high level value (a.VgON) with respect to the signal as shown in FIG. ) And low level values (a
(VgOFF), a signal having a predetermined potential is output, and a gate signal G amplified to a practical potential is output from the power amplifier 26 to which the signal is input.

[0030]

As described above, the signal generator according to the present invention individually generates low-level basic signals based on the settings of the amplitude, cycle, relative delay time, etc. of the pulses of a plurality of signals. A high-speed and high-voltage pulse signal can be easily obtained, and the change including the polarity of the offset level (Vm, Vc−Vm) between the signals required for operation is facilitated, so that the operability is improved. It is possible to improve and reduce the equipment cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a data signal generation process in the device of FIG. 1;

FIG. 3 is an explanatory diagram of signal waveforms in the course of data signal generation in FIG. 2;

FIG. 4 is an explanatory diagram of a process of generating a gate signal in the apparatus of FIG. 1;

FIG. 5 is an explanatory diagram of signal waveforms in the course of gate signal generation in FIG. 4;

FIG. 6 is a schematic view showing a part of a circuit of a liquid crystal display panel.

FIG. 7 is an explanatory diagram of a driving signal for a liquid crystal display panel test.

FIG. 8 is a block diagram of a conventional signal generator used for inspection of a liquid crystal display panel and the like.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal display panel 2 gate bus line 3 data bus line 4 TFT 5 liquid crystal 6 common electrode 22 timing pulse generation circuit 23 data pulse generation circuit 24, 28 DA converter 25 analog adder 26 power amplifier 27 level data generation circuit C common signal D Data signal G Gate signal

Claims (1)

[Claims] 1. A first pulse signal having a duty ratio of 1 and a predetermined period and amplitude of a rectangular wave, a first pulse signal whose rise is later than that of the first pulse signal by a predetermined time, whose fall is earlier, and which has a rectangular wave pulse. A signal generator for transmitting a second pulse signal whose period is half the period of the first pulse signal and a DC signal having a predetermined difference level with respect to a center level of the amplitude of the first pulse signal. A timing pulse generation circuit for setting a duty ratio, a cycle, and an amplitude of the first pulse signal, a pulse width of the second pulse signal, and a delay time of rising of the first pulse signal; A level data generation circuit for setting voltage levels of the first pulse signal, the second pulse signal, and the DC signal; and an output signal of the timing pulse generation circuit and the level data generation circuit. A data pulse generating circuit for receiving an output signal therefrom and outputting a composite digital signal thereof; a first DA converter for converting a digital signal output from the data pulse generating circuit into an analog signal; A second DA converter that converts a digital signal output from the circuit into an analog signal; an analog adder that combines the outputs of the first and second DA converters; and amplifies the output of the analog adder. A signal generator, comprising: a power amplifier for outputting.