JPH1031201A - Liquid crystal display device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to display an image with high contrast and less cross talk while using a circuit element of a low power consumption type by shifting polarity inversion timing between a counter electrode signal and a reference voltage signal by a prescribed time. SOLUTION: A timing control circuit 7 outputs a scan pulse signal (a) controlling the output timing of a scan signal (b) from a scan side drive circuit 4, a latch pulse signal (d) controlling the output timing of a display data signal (e) from a signal side drive circuit 5, a polarity inversion signal (i) controlling polarity inversion timing of the reference voltage signal (c) outputted from an analog signal generation circuit 6 and the polarity inversion signal (j) controlling the polarity inversion timing of the counter electrode signal (f). At this time, since the polarity inversion timing between the reference voltage signal (c) and counter electrode signal (f) outputted from the analog signal generation circuit 6 is shifted by a prescribed time, the required maximum output current of the analog signal generation circuit 6 is reduced when the counter electrode signal (f) is raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal display device, particularly to an active matrix type liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a line-common inversion driving circuit of an active matrix type liquid crystal display device disclosed in, for example, Japanese Patent Application Laid-Open No. 4-107525.
In the figure, reference numeral 1 denotes an active matrix type liquid crystal display panel (hereinafter, referred to as a "liquid crystal display panel"), a substrate 2 on which a switching element array of M rows and N columns is formed, and a counter substrate 3 on which a counter electrode is formed. And a liquid crystal is sealed between them. Reference numeral 4 denotes a scanning-side driving circuit that outputs a scanning signal b to M rows of signal lines, and 5 denotes a display data signal e to N columns of signal lines.
The signal-side drive circuit 6 outputs an analog potential signal g to be output to the scan-side drive circuit 4, a reference voltage signal c to be output to the signal-side drive circuit 5, and a counter electrode signal f to be output to the counter electrode. Analog signal generation circuit. Reference numeral 7 denotes a scanning pulse signal a for controlling the output timing of the scanning signal b output from the scanning side driving circuit 4, a latch pulse signal d for controlling the output timing of the display data signal e output from the signal side driving circuit 5, and A timing control circuit for outputting a polarity inversion signal h for controlling the polarity inversion timing of the reference voltage signal c and the counter electrode signal f output from the analog signal generation circuit 6.

FIG. 7 is a diagram showing an equivalent circuit of the liquid crystal display panel 1. A substrate 2 has M rows of scanning lines G _{1 to} G _M , N columns of signal lines S _{1 to SN,} and a scanning line G _1. To G _M and signal lines S _{1 to} S
A switching element T ₁₁ -T _MN such as a TFT formed at the intersection of _N and a pixel electrode D _{11 also} formed at the intersection.
To D _MN , the source electrodes of the switching elements T _{11 to} T _MN are on the signal lines S _{1 to} S _N , and the gate electrode is on the scanning line G.
_{1 to} G _M , the drain electrodes are connected to the pixel electrodes D _{11 to} D _MN , respectively, and the liquid crystal LC is sandwiched between the pixel electrodes D _{11 to} D _MN and the counter electrode E to form the pixels D _{11 to} D _MN. Each of the storage capacitors Cs _{11 to} Cs _MN is formed.

Next, the operation of the conventional line / common inversion drive circuit will be described with reference to the timing chart of FIG. For the scanning lines G _{1 to} G _M , the level is regulated by the analog potential g from the scanning side drive circuit 4 and the output timing is controlled by the scanning pulse signal a (FIG. 8A) (FIG. 8A). (B)) are sequentially applied, and the signal lines S _{1 to} S _N
The reference voltage signal c (from FIG. 8)
(C)) regulates the voltage level, and applies the display data signal e (FIG. 8 (e)) whose output timing is controlled by the latch pulse signal d (FIG. 8 (d)). Switching elements T ₁₁ through T _MN, the display scanning signal b becomes a period (one horizontal scanning period) on the state of Hi data signals e
Is applied to the pixel electrodes D _{11 to} D _MN , and the counter electrode E is supplied to the counter electrode E from the analog signal generation circuit 6 (FIG. 8F).
Is applied, the potentials of the pixel electrodes D _{11 to} D _{MN at} the time of the falling of the scanning signal b are changed to the holding capacitances Cs _{11 to} Cs ₁₁ .
It is held in the _MN for one frame period. The polarity inversion signal h (FIG. 8)
In (h)), since the polarity of the reference voltage signal c and the polarity of the counter electrode signal f are inverted by the time τ from the scanning pulse signal a, the horizontal scanning is delayed by the time τ from the rising timing of the scanning signal b. Inverts simultaneously for each period.

As described above, in the conventional line / common inversion driving circuit, the latch pulse signal d and the polarity inversion signal h
Is delayed by the time τ from the scanning pulse signal a, and the rising timing of the display data signal e and the counter electrode signal f is delayed by the time τ from the scanning signal b. This delay time τ is equal to the holding capacity Cs _{11 to} Cs _MN
The charging time is set so as not to be short, and the influence of the delay of the scanning signal b due to the transmission line can be ignored.

[0006]

In the conventional line-common inversion driving circuit, the polarity inversion of the reference voltage signal c and the counter electrode signal f is simultaneously performed, so that the power consumption at the time of the polarity inversion increases. Therefore, if the output capacitance of the analog signal generation circuit that outputs the reference voltage signal c and the counter electrode signal f is insufficient, the waveform of the counter electrode signal f at the time of polarity inversion is disturbed,
There has been a problem that display defects such as a decrease in contrast and crosstalk occur.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an active matrix using a low-power-consumption type analog signal generating circuit which does not cause a display defect such as a decrease in contrast or crosstalk. And a method of driving the same.

[0008]

According to a driving method of a liquid crystal display device according to the present invention, a scanning signal is sequentially applied to a plurality of scanning lines of an active matrix type liquid crystal display panel, and one horizontal scanning period is applied to the plurality of signal lines. Drive of a liquid crystal display device in which a display data signal whose voltage level is defined by a reference voltage signal whose polarity is inverted every time is applied, and a counter electrode signal whose polarity is inverted every horizontal scanning period is applied to the counter electrode. In the method, the polarity inversion timing of the counter electrode signal and the polarity inversion timing of the reference voltage signal are shifted by a predetermined time.

Further, the polarity inversion timing of the reference voltage signal is earlier than the polarity inversion timing of the counter electrode signal. Further, the polarity inversion timing of the counter electrode signal is earlier than the polarity inversion timing of the reference voltage signal.

Further, the liquid crystal display device according to the present invention comprises a scanning side driving circuit for sequentially applying a scanning signal to a plurality of scanning lines of an active matrix type liquid crystal display panel, and one horizontal scanning to a plurality of signal lines of the liquid crystal display panel. A signal-side drive circuit that applies a display data signal whose voltage level is defined by a reference voltage signal whose polarity is inverted every cycle, and a counter electrode signal whose polarity is inverted every horizontal scanning cycle to the counter electrode of the liquid crystal display panel An analog signal generation circuit for applying and outputting a reference voltage signal; and a reference voltage polarity inversion signal and a counter electrode for controlling the analog signal generation circuit so that the polarity inversion timings of the reference voltage signal and the counter electrode signal are different. And a timing control circuit for outputting a polarity inversion signal.

Further, a delay circuit is provided in the timing control circuit, and the reference voltage polarity inversion signal generated by the timing control circuit is delayed by the delay circuit to obtain a counter electrode polarity inversion signal. Also, the reference electrode polarity inversion signal generated by the timing control circuit is delayed by a delay circuit to obtain a reference voltage polarity inversion signal.

[0012]

Embodiments of the present invention will be specifically described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing a line / common inversion drive circuit of the active matrix type liquid crystal display device according to the first embodiment. In the figure, reference numeral 1 denotes a liquid crystal display panel, in which liquid crystal is sealed between a substrate 2 on which a switching element array of M rows and N columns is formed and a counter substrate 3 on which a counter electrode is formed. Reference numeral 4 denotes a scanning side driving circuit that outputs a scanning signal b to M row signal lines, 5 denotes a signal side driving circuit that outputs a display data signal e to N column signal lines, and 6 denotes an analog signal that is output to the scanning side driving circuit 4. An analog signal generating circuit for generating a potential signal g, a reference voltage signal c to be output to the signal side driving circuit 5, and an opposing electrode signal f to be output to the opposing electrode E. Reference numeral 7 denotes a scanning output from the scanning side driving circuit 4. A scanning pulse signal a for controlling the output timing of the signal b, a latch pulse signal d for controlling the output timing of the display data signal e output from the signal side driving circuit 5, and a reference voltage output from the analog signal generating circuit 6 This timing control circuit outputs a polarity inversion signal i for controlling the polarity inversion timing of the signal c and a polarity inversion signal j for controlling the polarity inversion timing of the counter electrode signal f. The configuration of the liquid crystal display panel 1 is the same as that of FIG.

FIG. 2 is a timing chart of the line / common inversion driving circuit of the first embodiment. FIG. 2A shows a scanning pulse signal a output from the timing control circuit 7 to the scanning side driving circuit 4, and FIG. FIG. 2B shows a scanning signal b output from the scanning side drive circuit 4 to the M scanning lines G _{1 to} G _M , and FIG.
Is a reference voltage signal c supplied from the analog signal generation circuit 6 to the signal side drive circuit 5 and defining the voltage level of the display data signal output from the signal side drive circuit 5, FIG.
Is a latch pulse signal d supplied from the timing control circuit 7 to the signal side drive circuit 5 and controlling the output timing of the display data signal e output from the signal side drive circuit 5;
It is behind the scanning pulse signal a by the time τ1. FIG.
(E) the signal lines S ₁ of N columns from the signal side driving circuit 5 to S _N
2 (f) is a counter electrode signal f output from the analog signal generation circuit 6 to the counter electrode E, and FIG. 2 (i) is a timing control circuit 7 from the timing control circuit 7 to the analog signal generation circuit 6. Given, analog signal generation circuit 6
Is a reference voltage polarity inversion signal i for controlling the timing of inverting the polarity of the reference voltage signal c output every one horizontal scanning period. FIG. 2 (j) shows the timing signal supplied from the timing control circuit 7 to the analog signal generation circuit 6,
Is a counter electrode polarity inversion signal j that controls the timing of inverting the polarity of the counter electrode signal f output from the scan pulse every one horizontal scanning period. Is τ1 ≧ τ2> τ3
Is set to the length.

Next, the operation will be described. Scan lines G _{1 to} G _M
2, the level is regulated by the analog potential g from the scanning side driving circuit 4 and the scanning pulse signal a (FIG.
The scanning signal b (FIG. 2B) whose output timing is controlled by (a)) is sequentially applied, and the reference voltage signal c (FIG. 2) is applied to the signal lines S _{1 to SN} from the signal side driving circuit 5.
The display data signal e (FIG. 2E) whose voltage level is defined by (c)) and whose output timing is controlled by the latch pulse signal d (FIG. 2D) is applied. Switching elements T ₁₁ through T _MN, the scanning signal b is a display data signal e is applied to the pixel electrode D ₁₁ to D _MN becomes period (one horizontal scanning period) on the state of H-level, the counter electrode E
Is applied with the counter electrode signal f (FIG. 2 (f)) from the analog signal generation circuit 6, the potential of the pixel electrodes D _{11 to} D _{MN at} the time of the falling edge of the scanning signal b is changed to the holding capacitance C
It is held for one frame by s _{11 to} Cs _MN .

The reference voltage signal c output from the analog signal generation circuit 6 is controlled by the reference voltage polarity inversion signal i and is delayed by a time τ3 from the rising timing of the scanning signal b. Under the control of the electrode polarity inversion signal j, it is delayed from the scanning pulse signal a by the time τ2, and there is a time difference of τ2-τ3, so that the required maximum output current of the analog signal generating circuit 6 becomes small.

FIG. 3 shows a reference voltage signal c according to the first embodiment.
And the signal waveform of the common electrode signal f, and the polarity inversion timing of the reference voltage signal c and the common electrode signal f is represented by τ2−τ3.
Due to this, the current supply from the analog signal generation circuit 6 is sufficient, and the waveform distortion at the time of the rising of the counter electrode signal f is reduced. Further, the influence on the potential fluctuation of the counter electrode E due to the capacitive coupling between the signal lines S _{1 to} S _N and the counter electrode E is reduced. Thereby, a sufficient voltage is applied to the liquid crystal LC, so that a display image with a high contrast ratio and a display image with little crosstalk can be obtained.

Embodiment 2 FIG. In the first embodiment, the reference voltage polarity reversal signal i and the counter electrode polarity reversal signal j are generated from the timing control circuit 7, but the delay circuit 8 is provided as shown in FIG. The reference voltage polarity inversion signal i is distributed and passed through the delay circuit 8, and is delayed by the time (τ2−τ3) to generate an analog signal as the counter electrode polarity inversion signal j delayed by the time τ3 from the rising timing of the scanning signal b. The signal may be input to the circuit 6.

Embodiment 3 FIG. 5 is a signal timing chart according to the third embodiment of the present invention. In the third embodiment, the delay time from the rising of the scanning signal b to the rising of the latch pulse signal d is τ1, the delay time of the polarity inversion timing of the counter electrode signal f from the rising of the scanning signal b is τ2, Reference voltage signal c from rising
The latch pulse signal d, the reference voltage polarity inversion signal i, and the counter electrode polarity inversion are set such that the delay time of the polarity inversion timing of is τ3, and the delay times τ1, τ2, τ3 satisfy the relationship of τ1 ≧ τ3> τ2. The delay time τ1 of the signal j,
τ2 and τ3 are set.

According to the third embodiment, the delay time .tau.2 from the rising of the scanning signal b of the common electrode signal f is set short, so that the time from when the polarity of the common electrode signal f is inverted to the falling of the scanning signal b is set. The time gets longer. For this reason, the potential of the counter electrode signal f at the time of the falling of the scanning signal b becomes sufficiently close to a desired value, and a sufficient voltage can be applied to the liquid crystal LC, so that a display image with a high contrast ratio can be obtained. .

In the first to third embodiments, the polarity inversion timing of the reference voltage signal c output from the analog signal generation circuit 6 and the polarity inversion of the common electrode signal f is shifted by a predetermined time. The required maximum output current of the analog signal generation circuit 6 becomes smaller. Therefore, a display image having a high contrast ratio and little crosstalk can be obtained by using a low power consumption type analog signal generation circuit.

[0021]

Since the present invention is configured as described above, it has the following effects.

In the method of driving the liquid crystal display device according to the present invention, the polarity inversion timing of the counter electrode signal and the polarity inversion timing of the reference voltage signal supplied to the signal side drive circuit are shifted by a predetermined time, so that the polarity inversion of the counter electrode signal is performed. In this case, the required output current of the analog signal generation circuit becomes smaller. Therefore, an image with high contrast and little crosstalk can be displayed by using a low power consumption type circuit element.

Further, since the polarity reversal timing of the counter electrode signal is earlier than the polarity reversal timing of the reference voltage signal, the time from the polarity reversal of the counter electrode to the fall of the scanning signal can be lengthened, which is sufficient for the liquid crystal. Since a holding voltage can be applied, an image having a high contrast ratio can be displayed.

A liquid crystal display device according to the present invention comprises: a reference voltage polarity inversion signal for controlling a polarity inversion timing of a reference voltage signal for defining a voltage level of a display data signal applied to a signal line of a liquid crystal display panel; A timing control circuit is provided to output the counter electrode polarity reversal signal for controlling the polarity reversal timing of the counter electrode signal applied to the counter electrode as different polarity reversal timing signals. The required output current of the generator is reduced. Therefore, a liquid crystal display device that can display an image with high contrast and low crosstalk by using a low power consumption type circuit element can be obtained.

Further, a delay circuit is provided in the timing control circuit, and one of the reference voltage polarity inversion signal and the counter electrode polarity inversion signal generated by the timing control circuit is delayed by the delay circuit, and the other polarity inversion signal is generated. As a result, the circuit size of the timing control circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an active matrix liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart of the line-common inversion drive circuit according to the first embodiment;

FIG. 3 is a diagram showing waveforms of a reference voltage signal and a counter electrode signal according to the first embodiment.

FIG. 4 is a block diagram of a timing control circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart of the line-common inversion drive circuit according to the third embodiment of the present invention;

FIG. 6 is a block diagram of a conventional active matrix type liquid crystal display device.

FIG. 7 is a diagram showing a configuration of an active matrix type liquid crystal display panel.

FIG. 8 is a timing chart of a line / common inversion drive circuit of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 active matrix type liquid crystal display panel, 2 substrate, 3 opposing substrate, 4 scan side drive circuit, 5 signal side drive circuit, 6 analog signal generation circuit, 7 timing control circuit, a scan pulse signal, b scan signal, c reference voltage Signal, d latch pulse signal, e display data signal, f counter electrode signal, i reference voltage polarity inversion signal,
j Counter electrode polarity inversion signal.

Claims (6)

[Claims] 1. A scanning signal is sequentially applied to a plurality of scanning lines of an active matrix type liquid crystal display panel, and a voltage level is defined by a reference voltage signal whose polarity is inverted every horizontal scanning period to the plurality of signal lines. A method of driving a liquid crystal display device, wherein a display data signal is applied, and a counter electrode signal whose polarity is inverted every horizontal scanning period is applied to the counter electrode, wherein the polarity inversion timing of the counter electrode signal and the reference voltage A method for driving a liquid crystal display device, wherein the liquid crystal display device is driven by shifting a polarity inversion timing of a signal by a predetermined time. 2. The timing of inverting the polarity of a reference voltage signal,
2. The method according to claim 1, wherein the timing is earlier than the polarity inversion timing of the counter electrode signal. 3. The polarity inversion timing of the counter electrode signal is
2. The method according to claim 1, wherein the timing is earlier than the polarity inversion timing of the reference voltage signal. 4. A scanning-side drive circuit for sequentially applying a scanning signal to a plurality of scanning lines of an active matrix type liquid crystal display panel, and a reference in which the polarity is inverted to the plurality of signal lines of the liquid crystal display panel every horizontal scanning period. A signal-side drive circuit for applying a display data signal whose voltage level is defined by a voltage signal; a counter electrode signal whose polarity is inverted every horizontal scanning period to a counter electrode of the liquid crystal display panel; An analog signal generation circuit that outputs a signal, and a reference voltage polarity inversion signal and a counter electrode polarity inversion signal that control the polarity inversion timing of the reference voltage signal and the counter electrode signal to be different from each other. A liquid crystal display device comprising a timing control circuit for outputting. 5. A delay circuit is provided in a timing control circuit,
5. The liquid crystal display device according to claim 4, wherein a reference voltage polarity inversion signal generated by said timing control circuit is delayed by a delay circuit to obtain a counter electrode polarity inversion signal. 6. A delay circuit is provided in a timing control circuit,
5. The liquid crystal display device according to claim 4, wherein the counter electrode polarity inversion signal generated by the timing control circuit is delayed by a delay circuit to obtain a reference voltage polarity inversion signal.