CN109147636B

CN109147636B - Display device and gate driving array control circuit therein

Info

Publication number: CN109147636B
Application number: CN201810149185.0A
Authority: CN
Inventors: 陈健忠; 黄心圣
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2017-06-17
Filing date: 2018-02-13
Publication date: 2021-11-02
Anticipated expiration: 2038-02-13
Also published as: CN109147636A; TWI650745B; TW201905880A

Abstract

The invention provides a display device and a grid driving array control circuit therein. The display device includes: the time sequence control circuit is used for generating a picture synchronization signal; the gate driving array control circuit is coupled to the timing control circuit, and includes: a scan signal management circuit for generating a scan signal management signal according to the frame synchronization signal, a default panel parameter and an operation frequency signal; the scanning signal management circuit comprises a storage unit, a control unit and a display unit, wherein the storage unit is used for storing default panel parameters; and a level shift circuit for generating a scan control signal according to the scan signal management signal to control the gate driving array of the display panel circuit, wherein the gate driving array generates a gate driving signal according to the scan control signal to control the vertical scanning operation of the display panel circuit.

Description

Display device and gate driving array control circuit therein

Technical Field

The present invention relates to a display device, and more particularly, to a display device having fewer signal lines. The invention also relates to a gate drive array control circuit for use in a display device.

Background

Prior applications related to the present application are: US9595219B2, US7471286B2 and US9013468B 2.

In fig. 1, a display device (display device 1) in the prior art is disclosed in US9595219B2, wherein a timing controller (Tcon)110 controls a level shifter (level shifter)130 to generate scan signal management signals (such as CLK, VST, VRST, etc. signals shown in the figure) for controlling a gate driving array (GOA)140, thereby generating gate driving signals GL for controlling the vertical scanning operation of a display panel unit 100A. The display panel 100 includes a plurality of display panel units 100A arranged in a two-dimensional array of a plurality of horizontal columns (rows) and a plurality of vertical rows (columns); the vertical scanning operation is a scanning operation for selecting different columns in the display panel unit 100 in order along the vertical direction.

The prior art shown in fig. 1 has a disadvantage that the output signal of the timing controller 110 substantially corresponds to the scan signal management signal in a one-to-one relationship, and therefore, the number of signal lines between the timing controller 110 and the level shifter 130 is greatly increased in higher resolution display panel applications, which increases the cost and the difficulty of circuit design. In addition, such a display device architecture is usually applied to a single type of display panel with fixed default panel parameters, and if the architecture is applied to a plurality of types of display panels, the cost of the timing controller 110 is greatly increased.

Compared with the prior art shown in fig. 1, the display panel has high elasticity, can be applied to display panels of various forms, and can reduce the cost of the whole display equipment.

Disclosure of Invention

The present invention is directed to overcoming the disadvantages and drawbacks of the prior art, and providing a display device and a gate driving array control circuit thereof, which have high flexibility, can be applied to various types of display panels, and can reduce the cost of the entire display device.

In order to achieve the above object of the invention, in one of its viewpoints, the present invention provides a display device comprising: a time sequence control circuit for generating a picture synchronization signal; and a gate driver array (GOA) control circuit, coupled to the timing control circuit, comprising: a scanning signal management circuit for generating a scanning signal management signal according to the frame synchronization signal, a default panel parameter and an operation frequency signal; the scanning signal management circuit comprises a storage unit for storing the default panel parameters; and a level shift circuit for generating a scan control signal according to the scan signal management signal to control a gate driving array of a display panel circuit, wherein the gate driving array generates a gate driving signal according to the scan control signal to control a vertical scan operation of the display panel circuit.

In a preferred embodiment, the scan signal management circuit further comprises an oscillator for generating the operation frequency signal.

In a preferred embodiment, the timing control circuit provides the operating frequency signal.

In a preferred embodiment, the operating frequency signal is not provided externally from the GOA control circuit.

In a preferred embodiment, the operation clock signal is synchronized with the frame synchronization signal.

In a preferred embodiment, the operation clock signal is synchronized or not synchronized with a vertical scan clock of the display panel circuit.

In a preferred embodiment, the default panel parameter is one of: (1) a fixed value; (2) a selectable fixed value; and (3) an adjustable value, wherein the default panel parameter is written into the storage unit by a user at a setup stage.

In a preferred embodiment, the scan control signal comprises at least one of: (1) a GOA phase control signal for controlling the phase and waveform of the gate driving signal; (2) a endurance control signal for controlling a endurance operation of the gate driving signal; and (3) a shutdown signal for controlling a shutdown operation of the gate driving signal.

In a preferred embodiment, the default panel parameters include at least one of: (1) a phase number of the GOA phase control signal; (2) a phase overlay parameter of the GOA phase control signal; (3) a transient waveform parameter of the GOA phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter.

In a preferred embodiment, the scan signal management circuit further comprises at least one of the following units: a phase number control unit for determining the phase number of the GOA phase control signal; a phase overlay control unit for adjusting the degree of phase overlay (overlay) of the GOA phase control signal; a transient control unit for controlling the transient waveform of the GOA phase control signal; an interval control unit for controlling a horizontal interval time or a vertical interval time; a durability control unit for generating the durability control signal; and a shutdown control unit for generating the shutdown signal.

In a preferred embodiment, the signal lines between the timing control circuit and the GOA control circuit do not include (1) signal lines directly corresponding to the GOA phase control signals, (2) signal lines directly corresponding to the endurance control signals, or (3) signals directly corresponding to the shutdown signals.

Viewed from another perspective, the present invention also provides a gate driver array (GOA) control circuit for a display device, comprising: a time sequence control circuit for generating a picture synchronization signal; the GOA control circuit is coupled with the time sequence control circuit; the GOA control circuit comprises: a scanning signal management circuit for generating a scanning signal management signal according to the frame synchronization signal, a default panel parameter and an operation frequency signal; the scanning signal management circuit comprises a storage unit for storing the default panel parameters; and a level shift circuit for generating a scan control signal according to the scan signal management signal to control a gate driving array of a display panel circuit, wherein the gate driving array generates a gate driving signal according to the scan control signal to control a vertical scan operation of the display panel circuit.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

FIG. 1 shows a block diagram of a prior art display device;

FIG. 2 is a block diagram of a display device according to an embodiment of the present invention;

FIGS. 3A-3C are schematic diagrams showing waveforms of the display device of the present invention;

fig. 4 is a schematic diagram of an embodiment of a GOA control circuit in the display device of the present invention.

FIG. 5 is a block diagram of a display device according to an embodiment of the present invention;

FIG. 6 is a block diagram of a display device according to an embodiment of the present invention;

fig. 7 is a schematic diagram of an embodiment of a GOA control circuit in the display device of the present invention.

Description of the symbols in the drawings

1, 2, 5, 6 display device

10 sequential control circuit

20, 20' GOA control circuit

21 scanning signal management circuit

211 storage unit

22 level shift circuit

23 Oscillator

212 phase number control unit

213 phase overlay control unit

214 instantaneous control unit

215 interval control unit

216 durability control unit

217 shutdown control unit

30 display panel circuit

31 gate drive array

32 display panel unit

CKV _ GOAm GOA phase control signal

CKV _ GOAxP GOA phase control signal

CKV _ GOAxN GOA phase control signal

CLK operating frequency signal

FS picture synchronization signal

GL gate drive signal

LECn durability control signal

POFF shutdown signal

SCS scanning control signal

SSM scan signal management signal

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Referring to fig. 2, the display device 2 according to an embodiment of the present invention includes a timing control circuit 10 and a gate-driver on array (GOA) control circuit 20 (display device 2). The timing control circuit 10 is used for generating a frame synchronization signal FS. The GOA control circuit 20 is coupled to the timing control circuit 10, and includes a scan signal management circuit 21 and a level shift circuit 22. Wherein the scan signal management circuit 21 is used for generating a scan signal management signal SSM according to the frame synchronization signal FS, a default panel parameter and an operation clock signal CLK; the scan signal management circuit 21 includes a storage unit 211 for storing the default panel parameters. The level shift circuit 22 generates a scan control signal SCS according to the scan signal management signal SSM for controlling a gate driving array 31 of a display panel circuit 30 (such as but not limited to a TFT-LCD display panel), wherein the gate driving array 31 generates a gate driving signal GL according to the scan control signal SCS for controlling a vertical scan operation of the display panel circuit 30; specifically, as shown in fig. 2, the gate driving array 31 controls vertical scanning of the display panel unit 32 by the gate driving signal GL to perform development.

The frame synchronization signal FS is a clock signal synchronized with the frame rate of the display panel circuit 30 for synchronously displaying the frames, and in one embodiment, the frequency of the frame synchronization signal FS is the same as the frame rate of the display panel circuit 30.

Referring to fig. 2, in an embodiment, the scan control signal SCS may include at least one of the following: (1) a GOA phase control signal CKV _ GOA for controlling the phase and waveform of the gate driving signal GL of the display panel circuit 30; in one embodiment, the GOA phase control signal CKV _ GOA includes m phases, such as the phase control signals CKV _ GOA1 CKV _ GOAm shown in the figure, where m is a positive integer; (2) a endurance control signal LEC for controlling a endurance operation of the gate driving signal GL; in one embodiment, the endurance control signal LEC includes n encoded or unencoded endurance control signals, such as the endurance control signals LEC 1-LECn shown in the figure, where n is a positive integer; and (3) a power-off signal POFF for controlling a power-off operation of the gate driving signal GL. In one embodiment, the scan signal management signals SSM correspond to the scan control signals SCS one by one.

The display panel circuits of different manufacturers have various parameters, such as, but not limited to, the vertical resolution, the number of phases of the gate driving signals GL, instantaneous waveform requirements of the gate driving signals GL, and the like, and/or signal requirements for endurance operation or shutdown operation of the gate driving signals GL, and the like. The display device of the invention can be flexibly applied to display panel circuits of different manufacturers and different forms. The details of which will be described later.

Referring to fig. 3A-3C, the GOA control circuit (e.g., the GOA control circuit 20) of the present invention can generate the corresponding GOA phase control signal CKV _ GOA according to the above-mentioned different requirements, and further control the gate driving array 31 to generate the corresponding gate driving signal GL, taking fig. 3A as an example, in the present embodiment, the GOA phase control signal includes a pair of complementary GOA phase control signals CKV _ GOAxP and CKV _ GOAxN, and according to the requirements (e.g., the charge sharing control) of the display panel circuit in the present embodiment, the rising edge and the falling edge of the GOA phase control signals CKV _ GOAxP and CKV _ GOAxN need to be divided into a plurality of stages, such as T1-T5 in the figure. Taking fig. 3B as an example, in the present embodiment, the GOA phase control signals include, for example, but not limited to, 6 sets of phases, i.e., CKV _ GOA1 CKV _ GOA6, as shown in the figure, according to the requirements of the display panel circuit in the present embodiment, a phase overlap relationship is required between the GOA phase control signals CKV _ GOA1 CKV _ GOA6, for example, the GOA phase control signals CKV _ GOA1 and CKV _ GOA2 overlap at time points t2-t 5. In addition, as shown in fig. 3B, in the present embodiment, in the display scanning stage, for example, after the time point t1, the rising edge or the falling edge of the GOA phase control signals CKV _ GOA 1-CKV _ GOA6 needs to have a transient waveform of a clipping (clipping) (e.g., the waveform of the GOA phase control signal CKV _ GOA1 at t1-t 2).

Taking fig. 3C as an example, in the present embodiment, the on periods of the GOA phase control signals CKV _ GOA 1-CKV _ GOA6 (e.g., the on period of CKV _ GOA1 is t1-t2) do not need to be overlapped, and in the present embodiment, the instantaneous waveform of the GOA phase control signals does not need to be chamfered.

In addition, the GOA control circuit (e.g., the GOA control circuit 20) of the present invention can generate the corresponding endurance control signal LEC according to the above-mentioned different requirements, so as to prolong the service life of the display panel circuit or the display device. In one embodiment, the endurance control signal LEC may be used to control the timing of the inverse driving of the display panel circuit; in yet another embodiment, the endurance control signal LEC may be used to control the management of the alternate driving of some circuits in the display device.

Similarly, the GOA control circuit (e.g., the GOA control circuit 20) of the present invention can generate a corresponding shutdown signal POFF for controlling the shutdown operation of the display panel circuit according to the aforementioned different requirements.

According to the requirements of the different panel specifications, the default panel parameters stored in the storage unit 211 may include, for example, but not limited to, the vertical or horizontal scanning resolution, the frame rate, the vertical or horizontal scanning interval (blanking) time parameter (such as the number or the time length), the phase number of the vertical scanning line, the phase number of the GOA phase control signal, the phase overlay parameter, the instantaneous waveform parameter of the GOA phase control signal, the endurance control related parameter, the shutdown signal related parameter, and the like, and combinations thereof, for generating the corresponding scan control signal SCS (i.e., the GOA phase control signal, the endurance control signal, the shutdown signal, and the like).

Referring to fig. 4, a GOA control circuit (GOA control circuit 20) in an embodiment of the display device of the present invention is shown, in which the scan signal management circuit 21 further includes at least one of the following units: a phase control unit 212, a phase overlay control unit 213, a transient control unit 214, an interval control unit 215, a endurance control unit 216, and a power-off control unit 217, wherein the control unit generates a corresponding scan signal management signal SSM according to the frame synchronization signal FS, the default panel parameters, and the operation clock signal CLK, so as to control the level shift circuit 22 to generate the scan control signal SCS. Wherein the phase number control unit 212 is configured to determine a phase number of the GOA phase control signal to provide a corresponding GOA phase control signal; the phase overlay control unit 213 is used to adjust the phase overlay (overlay) degree of the GOA phase control signal; the transient control unit 214 is used for controlling the transient waveform of the GOA phase control signal; the interval control unit 215 is used to control the number of horizontal intervals or vertical intervals or the time length; the durability control unit 216 is used for generating a durability control signal; the shutdown control unit 217 is used for generating the shutdown signal.

The display device of the present invention can be applied to one display panel or a plurality of display panels. In one embodiment, the default panel parameter may be a fixed value, an optional fixed value, or an adjustable value. In the embodiment where the default panel parameters are adjustable, the default panel parameters may be written into the storage unit 211 by a user in a setup phase. The setting stage can be, for example, during the production of the display panel, or during the non-display scanning after each power-on. In one embodiment, the default panel parameters can be written into the storage unit 211 by the timing control circuit 10. it should be noted that, unlike the prior art, according to the present invention, the default panel parameters are static parameter values, which only need to be set, for example, in the setup phase, between the timing control circuit and the GOA control circuit, through, for example, but not limited to, I²C, etc. (as shown in fig. 5) to transmit default panel parameters and write in the storage unit 211. contrary to the prior art, there are a huge number of signal lines between the timing controller and the GOA control circuit because the dynamic control signals directly related to the scan control signals and corresponding to the scan control signals in real time. According to the present invention, in an embodiment, only one and only one signal, i.e. the frame synchronization signal FS, may be included between the timing control circuit 10 and the GOA control circuit 20, and the GOA control circuit 20 may generate the aforementioned various scan control signals according to the default panel parameters stored in the storage unit 211. In one embodiment, the transmission signal between the timing control circuit 10 and the GOA control circuit 20 may be composed of only the frame synchronization signal FS and the operation clock signal CLK.

Referring to fig. 6, another embodiment of the display device (display device 6) of the present invention is shown, in which the operating frequency signal CLK of the display device 6 is provided by the timing control circuit 10.

In an embodiment, the operation clock signal CLK may not be provided from the exterior of the GOA control circuit. Referring to fig. 7, a GOA control circuit 20 'of a display device according to an embodiment of the present invention is shown, in which the scan signal management circuit 21 further includes an oscillator 23 for generating the operation clock signal CLK, similar to the GOA control circuit 20 of fig. 4, but the GOA control circuit 20' further includes an oscillator 23 for generating the operation clock signal CLK, in this embodiment, since the operation clock signal CLK is generated in the GOA control circuit 20 ', signal lines between the timing control circuit 10 and the GOA control circuit 20' can be further reduced.

In one embodiment, the clock signal CLK is synchronized with the frame synchronization signal FS, and in a preferred embodiment, the clock signal CLK is synchronized with the falling edge of the frame synchronization signal FS, i.e. at the end of the synchronization signal, which is t1 as shown in FIG. 3C. In addition, in a preferred embodiment, the frequency of the operation clock signal CLK is 5 times or more of the vertical scanning frequency VF of the frame, wherein the vertical scanning frequency VF is the frame update rate (vertical resolution + vertical interval number), so that the scan control signal SCS (e.g. the GOA phase control signal) can have higher waveform resolution, thereby improving the display quality of the display panel circuit.

In one embodiment, the clock signal CLK may be synchronized with the vertical scanning clock VF of the display panel circuit, and in one embodiment, the clock signal CLK may not be synchronized with or related to the vertical scanning clock VF of the display panel circuit.

As can be seen from the foregoing embodiments, according to the present invention, the number of signal lines between the timing control circuit and the GOA control circuit can be greatly reduced, and from one perspective, the signal lines between the timing control circuit and the GOA control circuit do not include (1) a signal line directly corresponding to the GOA phase control signal, (2) a signal line directly corresponding to the endurance control signal, or (3) a signal directly corresponding to the shutdown signal. In one embodiment, the signal lines between the timing control circuit and the GOA control circuit do not include a combination of the above signal lines. The term "directly corresponding to" the GOA phase control signal means that the signal received by the GOA control circuit from the timing control circuit has a one-to-one correspondence relationship with the GOA phase control signal, or a correspondence relationship with the GOA phase control signal without encoding.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. The embodiments described are not limited to separate applications, but may be applied in combination. Moreover, equivalent variations and combinations are conceivable for those skilled in the art, for example, the operation clock signal CLK is selectable, that is, the operation clock signal CLK can be provided internally by the GOA control circuit (such as the aforementioned oscillator) or externally by the GOA control circuit (such as the timing control circuit) by the user. For example, the phrase "performing a process or an operation or generating an output result based on a signal" in the present invention is not limited to the signal itself, and includes, if necessary, performing a voltage-to-current conversion, a current-to-voltage conversion, and/or a ratio conversion on the signal, and then performing a process or an operation based on the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A display device, comprising:

a time sequence control circuit for generating a picture synchronization signal; and

a gate drive array control circuit, coupled to the timing control circuit, comprising:

a scanning signal management circuit for generating a scanning signal management signal according to the frame synchronization signal, a default panel parameter and an operation frequency signal; the scanning signal management circuit comprises a storage unit for storing the default panel parameters; and

a level shift circuit for generating a scan control signal according to the scan signal management signal to control a gate driving array of a display panel circuit, wherein the gate driving array generates a gate driving signal according to the scan control signal to control a vertical scan operation of the display panel circuit:

wherein the scan control signal comprises at least one of: (1) a gate drive array phase control signal for controlling the phase and waveform of the gate drive signal; (2) a endurance control signal for controlling a endurance operation of the gate driving signal; and (3) a shutdown signal for controlling a shutdown operation of the gate driving signal.

2. The display device of claim 1, wherein the scan signal management circuit further comprises an oscillator for generating the operating frequency signal.

3. The display device of claim 1, wherein the timing control circuit provides the operating frequency signal.

4. The display device of claim 1, wherein the operating frequency signal is not provided externally from the gate drive array control circuit.

5. The display device according to any one of claims 2 to 4, wherein the operation frequency signal is synchronized with the picture synchronization signal.

6. The display apparatus according to any one of claims 2 to 4, wherein the operation frequency signal is synchronized or not synchronized with a vertical scanning frequency of the display panel circuit.

7. The display device of claim 1, wherein the default panel parameter is one of: (1) a fixed value; (2) a selectable fixed value; and (3) an adjustable value, wherein the default panel parameter is written into the storage unit by a user at a setup stage.

8. The display device of claim 1, wherein the default panel parameters include at least one of: (1) a phase number of the gate drive array phase control signal; (2) a phase overlay parameter of the gate drive array phase control signal; (3) an instantaneous waveform parameter of the gate drive array phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter.

9. The display device of claim 1, wherein the scan signal management circuit further comprises at least one of:

a phase number control unit for determining the phase number of the gate drive array phase control signal;

a phase overlapping control unit for adjusting the phase overlapping degree of the grid driving array phase control signal;

a transient control unit for controlling the transient waveform of the gate drive array phase control signal;

an interval control unit for controlling a horizontal interval time or a vertical interval time;

a durability control unit for generating the durability control signal; and

a shutdown control unit for generating the shutdown signal.

10. The display device of claim 1, wherein the signal lines between the timing control circuit and the gate drive array control circuit do not include (1) signal lines directly corresponding to gate drive array phase control signals; (2) a signal line directly corresponding to the endurance control signal; or (3) a signal directly corresponding to a shutdown signal.

11. A gate drive array control circuit for a display device, the display device comprising: a time sequence control circuit for generating a picture synchronization signal; the grid driving array control circuit is coupled with the time sequence control circuit; the gate drive array control circuit comprises:

12. The gate drive array control circuit of claim 11, wherein the scan signal management circuit further comprises an oscillator for generating the operating frequency signal.

13. The gate drive array control circuit of claim 11, wherein the timing control circuit provides the operating frequency signal.

14. The gate drive array control circuit of claim 11, wherein the operating frequency signal is not provided externally to the gate drive array control circuit.

15. The gate drive array control circuit of any of claims 12 to 14, wherein the operation frequency signal is synchronized with the frame synchronization signal.

16. The gate drive array control circuit of any of claims 12 to 14, wherein the operating frequency signal is synchronized or not synchronized with a vertical scan frequency of the display panel circuit.

17. The gate drive array control circuit of claim 11, wherein the default panel parameter is one of: (1) a fixed value; (2) a selectable fixed value; and (3) an adjustable value, wherein the default panel parameter is written into the storage unit by a user at a setup stage.

18. The gate drive array control circuit of claim 11, wherein the default panel parameters include at least one of: (1) a phase number of the gate drive array phase control signal; (2) a phase overlay parameter of the gate drive array phase control signal; (3) an instantaneous waveform parameter of the gate drive array phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter.

19. The gate drive array control circuit of claim 11, wherein the scan signal management circuit further comprises at least one of:

a durability control unit for generating the durability control signal; and

a shutdown control unit for generating the shutdown signal.

20. The gate drive array control circuit of claim 11, wherein the signal lines between the timing control circuit and the gate drive array control circuit do not include (1) signal lines directly corresponding to gate drive array phase control signals, (2) signal lines directly corresponding to endurance control signals, or (3) signals directly corresponding to shutdown signals.