JP2009037372A - Constant current circuit and constant voltage circuit - Google Patents

Constant current circuit and constant voltage circuit Download PDF

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JP2009037372A
JP2009037372A JP2007200335A JP2007200335A JP2009037372A JP 2009037372 A JP2009037372 A JP 2009037372A JP 2007200335 A JP2007200335 A JP 2007200335A JP 2007200335 A JP2007200335 A JP 2007200335A JP 2009037372 A JP2009037372 A JP 2009037372A
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voltage
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mosfet
constant
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JP5088031B2 (en
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Tetsuya Kawashima
鉄也 川島
Kohei Yamada
耕平 山田
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a constant current circuit and a constant voltage circuit for simultaneously providing a reference voltage and a reference current. <P>SOLUTION: An output Vref of a reference voltage generating circuit 100 is input to the (-) input terminal of an operational amplifier 102; an output voltage Vout of a reference voltage trimming circuit 103 whose total resistance value is not changed with trimming is input to the (+) input terminal of the operational amplifier 102 and both voltage values are compared. An output of the operational amplifier 102 controls the gate of an output transistor 104 so as to virtually short-circuit two inputs of the operational amplifier 102 to set an output voltage Vref1 at a desired value. If the output voltage Vref1 needs to be adjusted, resistors R1, R2 are trimmed. Since the total resistance value is not changed with the trimming, both the constant voltage and the constant current can be stably obtained. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、定電圧を生成するとともに、発振器、誤差増幅器、コンパレータなどの基準電流(バイアス電流を含む)となる定電流を生成するための定電流・定電圧回路に関する。   The present invention relates to a constant current / constant voltage circuit for generating a constant voltage and generating a constant current that is a reference current (including a bias current) of an oscillator, an error amplifier, a comparator, and the like.

図5は、基準電流生成回路を含み、生成した基準電流(バイアス電流を含む)を発振器、誤差増幅器、コンパレータなどに供給する従来の定電流・定電圧回路の構成を示すブロック図である。図5に示すように従来の定電流・定電圧回路は、基準電圧生成回路1、基準電流生成回路2、出力バッファ3、抵抗4〜6からなる抵抗体を含む基準電圧・基準電流生成部10で構成されている。そして基準電圧・基準電流生成部10からは出力バッファ3から出力される基準電圧Vref1と、抵抗5及び抵抗6の接続点から出力される基準電圧Vref2と、基準電流生成回路2から出力される基準電流ib4及びバイアス電流ib1〜ib3,ib5とが出力され、これらの基準電圧Vref1,Vref2、並びに、これら回路を駆動するための基準電流ib4およびバイアス電流ib1〜ib3,ib5が出力バッファ3、発振器20、誤差増幅器30、コンパレータ40、入力バッファ50に供給される。因みに基準電圧Vref1は入力バッファ50の参照電圧となるものであり、また基準電圧Vref2は誤差増幅器30の参照電圧となるものである。また基準電流ib4は、発振器20を駆動する基準電流となるものであり、バイアス電流ib1は出力バッファ3を、バイアス電流ib2は誤差増幅器30を、バイアス電流ib3は入力バッファ50を、バイアス電流ib5はコンパレータ40を駆動するためのものである。従来の定電流・定電圧回路は、このように基準電圧Vref1,Vref2並びに基準電流ib4およびバイアス電流ib1〜ib3,ib5を生成するために基準電圧生成回路1および基準電流生成回路2が別々に構成されている。そしてこれら基準電圧、基準電流(バイアス電流を含む)は各回路の基準となるため、温度・電源電圧に対する変動がないことが求められている。   FIG. 5 is a block diagram showing a configuration of a conventional constant current / constant voltage circuit that includes a reference current generation circuit and supplies the generated reference current (including a bias current) to an oscillator, an error amplifier, a comparator, and the like. As shown in FIG. 5, the conventional constant current / constant voltage circuit includes a reference voltage / reference current generation unit 10 including a reference voltage generation circuit 1, a reference current generation circuit 2, an output buffer 3, and a resistor including resistors 4-6. It consists of The reference voltage / reference current generation unit 10 outputs the reference voltage Vref1 output from the output buffer 3, the reference voltage Vref2 output from the connection point of the resistors 5 and 6, and the reference output from the reference current generation circuit 2. The current ib4 and the bias currents ib1 to ib3 and ib5 are output. The reference voltages Vref1 and Vref2 and the reference current ib4 and the bias currents ib1 to ib3 and ib5 for driving these circuits are output to the output buffer 3 and the oscillator 20. The error amplifier 30, the comparator 40, and the input buffer 50 are supplied. Incidentally, the reference voltage Vref1 is a reference voltage for the input buffer 50, and the reference voltage Vref2 is a reference voltage for the error amplifier 30. The reference current ib4 is a reference current for driving the oscillator 20. The bias current ib1 is the output buffer 3, the bias current ib2 is the error amplifier 30, the bias current ib3 is the input buffer 50, and the bias current ib5 is This is for driving the comparator 40. In the conventional constant current / constant voltage circuit, the reference voltage generation circuit 1 and the reference current generation circuit 2 are separately configured to generate the reference voltages Vref1 and Vref2, the reference current ib4, and the bias currents ib1 to ib3 and ib5 as described above. Has been. Since these reference voltage and reference current (including bias current) serve as a reference for each circuit, it is required that there is no variation with respect to temperature and power supply voltage.

従来からこれらの条件を満たす基準電圧、基準電流を生成する回路として様々な回路構成が提案されている。例えばデプレションMOSFETを用いた基準電圧生成回路、バイポーラトランジスタの温度特性を利用したバンドギャップリファレンス回路を用いた基準電圧生成回路などの定電流・定電圧回路が当業者に知られている。   Conventionally, various circuit configurations have been proposed as circuits for generating a reference voltage and a reference current that satisfy these conditions. For example, constant current / constant voltage circuits such as a reference voltage generation circuit using a depletion MOSFET and a reference voltage generation circuit using a band gap reference circuit using the temperature characteristics of a bipolar transistor are known to those skilled in the art.

上記以外にも例えば、特開2003‐177830号公報(特許文献1)に示されるような演算増幅器とカレントミラーを組み合わせた基準電流生成回路もある。
さらに特開平05-289758号公報(特許文献2)に示されるような抵抗R1をトリミングすることにより、定電圧となるよう調整された電圧を出力端子5から出力するボルテージレギュレータの例もある。
特開2003−177830号公報(図1,図2,図3) 特開平05−289758号公報(図2)
In addition to the above, there is also a reference current generation circuit in which an operational amplifier and a current mirror are combined as disclosed in JP-A-2003-177830 (Patent Document 1).
Further, there is an example of a voltage regulator that outputs a voltage adjusted to a constant voltage from the output terminal 5 by trimming the resistor R1 as disclosed in Japanese Patent Laid-Open No. 05-289758 (Patent Document 2).
Japanese Patent Laying-Open No. 2003-177830 (FIGS. 1, 2 and 3) JP 05-289758 A (FIG. 2)

図5に示される従来の定電流、定電圧回路では、基準電圧生成回路1の出力Vrefの駆動能力が低く、また電圧範囲も広く自由に設定することは難しいので、次段に出力バッファ3を設けることが必須であり、このため回路構成が複雑となるという問題を有している。   The conventional constant current and constant voltage circuit shown in FIG. 5 has a low driving capability of the output Vref of the reference voltage generation circuit 1 and it is difficult to freely set a wide voltage range. It is essential to provide the circuit configuration, which causes a problem that the circuit configuration becomes complicated.

また特許文献1に開示されている電流源回路は、外付けの抵抗を調整して所望の定電流値を得るものであるが、基準電圧の調整をすることはできない。
また特許文献2に開示されているボルテージレギュレータは、抵抗R1をトリミングすることにより基準電圧を調整することができるが、トリミングにより抵抗値が変化してしまうので、出力端子5の電圧が一定でも抵抗R1,R2に流れる電流が変化してしまうため、定電流を得ることができない。
The current source circuit disclosed in Patent Document 1 adjusts an external resistor to obtain a desired constant current value, but cannot adjust a reference voltage.
In addition, the voltage regulator disclosed in Patent Document 2 can adjust the reference voltage by trimming the resistor R1, but the resistance value is changed by trimming, so that the resistance voltage is constant even when the voltage of the output terminal 5 is constant. Since the current flowing through R1 and R2 changes, a constant current cannot be obtained.

本発明は、従来技術に関する以上の問題を解決し、基準電圧と基準電流を同時に得ることのできる定電流・定電圧回路を提供することを目的とする。   An object of the present invention is to provide a constant current / constant voltage circuit capable of solving the above-described problems related to the prior art and obtaining a reference voltage and a reference current simultaneously.

上記課題を解決するために、本発明の定電流・定電圧回路は、基準電圧生成回路、基準電圧出力バッファおよびトリミングがなされる分圧抵抗を有する定電流・定電圧回路において、前記基準電圧出力バッファの出力は第1のMOSFET(Metal Oxide Semiconductor Field Effect Transistor)のゲートに接続され、該第1のMOSFETのドレインは前記分圧抵抗に接続され、該分圧抵抗はトリミングにより抵抗を調整しても分圧比が変わるのみで抵抗値の総和は同じとなるようにされ、前記第1のMOSFETのドレイン電圧の前記分圧抵抗による分圧および前記基準電圧生成回路の出力が前記基準電圧出力バッファに入力され、さらに前記第1のMOSFETと同じ導電型の第2のMOSFETを前記第1のMOSFETに並列に接続し、前記第2のMOSFETの電流出力および前記第1のMOSFETのドレイン電圧をそれぞれ前記定電流・定電圧回路の定電流出力および定電圧出力とすることを特徴とする。なお、2つ(複数)のMOSFETを並列に接続するもしくは並列接続するとは、それらのMOSFETのゲートとゲート(ゲート同士)、およびソースとソース(ソース同士)を接続することを意味する。   In order to solve the above-described problems, a constant current / constant voltage circuit according to the present invention includes a reference voltage generating circuit, a reference voltage output buffer, and a constant current / constant voltage circuit having a voltage dividing resistor to be trimmed. The output of the buffer is connected to the gate of a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the drain of the first MOSFET is connected to the voltage dividing resistor, and the voltage dividing resistor adjusts the resistance by trimming. The sum of the resistance values is made the same only by changing the voltage dividing ratio, and the voltage dividing by the voltage dividing resistor of the drain voltage of the first MOSFET and the output of the reference voltage generating circuit are supplied to the reference voltage output buffer. And a second MOSFET having the same conductivity type as the first MOSFET is connected in parallel to the first MOSFET, and the current output of the second MOSFET and the drain voltage of the first MOSFET are Characterized by a constant current output and the constant voltage output of respectively the constant current and constant voltage circuit. Note that connecting two (a plurality of) MOSFETs in parallel or connecting them in parallel means connecting the gates and gates (gates) and the sources and sources (sources) of the MOSFETs.

本発明によれば、トリミングを行なってもトリミング回路の総抵抗値は不変なので、プロセスばらつき、温度環境変化等により基準電圧生成回路の基準電圧の変動を救済するトリミングを行なったとしても安定して定電圧と定電流の両方を得ることができる。   According to the present invention, since the total resistance value of the trimming circuit does not change even after trimming, even if trimming is performed to relieve the fluctuation of the reference voltage of the reference voltage generation circuit due to process variation, temperature environment change, etc. Both constant voltage and constant current can be obtained.

また基準電圧生成回路の後段に設ける基準電圧出力バッファを利用して基準電流を生成するため基準電流生成回路を独立して用意する必要なく、回路面積の点で有利となる。   Further, since a reference current is generated using a reference voltage output buffer provided at a subsequent stage of the reference voltage generation circuit, it is not necessary to prepare a reference current generation circuit independently, which is advantageous in terms of circuit area.

以下、本発明を実施するための最良の形態について、図面を参照して詳細に説明する。[実施形態1]
図1は本発明の第1の実施形態に係る定電流・定電圧回路の構成を示す回路ブロック図である。図1の定電流・定電圧回路においては、基準電圧生成回路100と、オペアンプ(OP1)102と、トリミングを行っても総抵抗値が変わらない基準電圧トリミング回路103と、生成された基準電圧Vref1をその出力端子(ドレイン)から取り出す(第1の)出力トランジスタ(QP4)104と、(第1の)出力トランジスタ104に並列接続されて(ソースとドレインが共通接続されて、すなわちカレントミラー回路を構成して)出力トランジスタ104の出力電流をコピーした電流I2を出力してダイオード接続されたトランジスタ(QN3)106に供給する(第2の)出力トランジスタ(QP5)105と、ダイオード接続されたトランジスタ(QN3)106に流れる電流I2をもとに基準電流ib4を生成するカレントミラー回路(QN4)107と、ダイオード接続されたトランジスタ(QN3)106に流れる電流I2をもとに基準電流ib1を生成するカレントミラー回路(QN5)108と、ダイオード接続されたトランジスタ(QN3)106に流れる電流I2をもとに基準電流ib2を生成するカレントミラー回路(QN6)109とで構成されている。なお図には示していないが、電流I2をもとにカレントミラー回路をさらに並列接続することで基準電流ib3,ib5を生成することができる。
Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. [Embodiment 1]
FIG. 1 is a circuit block diagram showing a configuration of a constant current / constant voltage circuit according to a first embodiment of the present invention. In the constant current / constant voltage circuit of FIG. 1, a reference voltage generation circuit 100, an operational amplifier (OP1) 102, a reference voltage trimming circuit 103 whose total resistance does not change even after trimming, and a generated reference voltage Vref1 Is connected in parallel to the (first) output transistor (QP4) 104 and the (first) output transistor 104 (the source and drain are connected in common, ie, the current mirror circuit is connected to the output terminal (drain)). And a (second) output transistor (QP5) 105 that outputs a current I2 that is a copy of the output current of the output transistor 104 and supplies it to the diode-connected transistor (QN3) 106, and a diode-connected transistor ( A current mirror circuit (QN4) 107 that generates a reference current ib4 based on a current I2 flowing through QN3) 106, and a diode A current mirror circuit (QN5) 108 that generates a reference current ib1 based on the current I2 flowing through the connected transistor (QN3) 106, and a reference current based on the current I2 that flows through the diode-connected transistor (QN3) 106 and a current mirror circuit (QN6) 109 for generating ib2. Although not shown in the figure, the reference currents ib3 and ib5 can be generated by further connecting current mirror circuits in parallel based on the current I2.

ここで本発明の実施形態に係る基準電圧トリミング回路について図3を用いて説明する。図3に示すように基準電圧トリミング回路103は、大きくは抵抗R1(130)および抵抗R2(140)を直列接続して構成され、抵抗R1(130)は、抵抗R1a(131),抵抗R1b(132),抵抗R1c(133),抵抗R1d(134)及び抵抗R1e(135)が縦続され、(R1a+R1b+R1c+R1d+R1e)がR1の抵抗値になるようにされ、また抵抗R2(140)は、抵抗R2a(141),抵抗R2b(142),抵抗R2c(143),抵抗R2d(144),抵抗R2e(145)が縦続され、(R2a+R2b+R2c+R2d+R2e)が抵抗R2の抵抗値となるようにされる。そして抵抗R1b(132),抵抗R1c(133),抵抗R1d(134)及び抵抗R1e(135)に対してトリミング用スイッチ151,152,153,154を設け、当該スイッチ151,152,153,154を2段のインバータ171,172、173,174、175,176、177,178を介して入力端子Zb,Zc,Zd,Zeに印加される2値信号で制御する。同様に、抵抗R2b(142),抵抗R2c(143),抵抗R2d(144),抵抗R2e(145)に対してトリミング用スイッチ161,162,163,164を設け、当該スイッチ161,162,163,164を1段のインバータ171、173、175、177を介して入力端子Zb,Zc,Zd,Zeに印加される2値信号で制御する。なお基準電圧トリミング回路103では、トリミング対象となっている抵抗R1(130)および抵抗R2(140)のうち同位置に配置されている抵抗に設けられているスイッチには、1段目インバータと2段目インバータにより異なる2値信号が制御信号として入力されて一方がONで他方がOFFとなるように切り替えることでR1およびR2の抵抗値を変更し、基準電圧トリミング回路の出力電圧Voutを調整する。その場合、それぞれ同位置に配置されている抵抗の抵抗値は同じ値、すなわちR1b=R2b,R1c=R2c,R1d=R2d,R1e=R2eとなるように設定し、トリミング前後において(R1+R2)の抵抗値は常に等しくなるようにされる。   Here, a reference voltage trimming circuit according to an embodiment of the present invention will be described with reference to FIG. As shown in FIG. 3, the reference voltage trimming circuit 103 is mainly configured by connecting a resistor R1 (130) and a resistor R2 (140) in series. The resistor R1 (130) includes a resistor R1a (131) and a resistor R1b ( 132), a resistor R1c (133), a resistor R1d (134), and a resistor R1e (135) are cascaded so that (R1a + R1b + R1c + R1d + R1e) becomes a resistance value of R1, and a resistor R2 ( 140) includes a resistor R2a (141), a resistor R2b (142), a resistor R2c (143), a resistor R2d (144), and a resistor R2e (145), and (R2a + R2b + R2c + R2d + R2e) is a resistor. The resistance value is set to R2. Trimming switches 151, 152, 153, and 154 are provided for the resistor R1b (132), the resistor R1c (133), the resistor R1d (134), and the resistor R1e (135), and the switches 151, 152, 153, and 154 are provided. Control is performed by binary signals applied to the input terminals Zb, Zc, Zd, Ze via the two-stage inverters 171, 172, 173, 174, 175, 176, 177, 178. Similarly, trimming switches 161, 162, 163, and 164 are provided for the resistors R2b (142), R2c (143), R2d (144), and R2e (145), and the switches 161, 162, 163 are provided. 164 is controlled by a binary signal applied to the input terminals Zb, Zc, Zd, Ze via one-stage inverters 171, 173, 175, 177. Note that in the reference voltage trimming circuit 103, the switch provided in the resistor arranged at the same position among the resistors R1 (130) and R2 (140) to be trimmed includes a first-stage inverter and 2 A different binary signal is input as a control signal by the stage inverter, and the resistance value of R1 and R2 is changed by switching so that one is ON and the other is OFF, and the output voltage Vout of the reference voltage trimming circuit is adjusted. . In that case, the resistance values of the resistors arranged at the same position are set to the same value, that is, R1b = R2b, R1c = R2c, R1d = R2d, R1e = R2e, and the resistance of (R1 + R2) before and after trimming The values are always made equal.

図1に示す定電流・定電圧回路の動作を説明する。図1において基準電圧生成回路100は、公知のデプレッションMOSFETを用いた基準電圧生成回路やバンドギャップリファレンス回路等で構成され、温度や電源電圧に対する出力電圧変動が小さいものとなるようにされる。基準電圧生成回路100の出力Vrefはオペアンプ102の−側入力端子に入力され、図3に示した基準電圧トリミング回路103の出力電圧Voutがオペアンプ102の+側入力端子に入力され、両方の電圧値が比較される。そしてオペアンプ102の出力が出力トランジスタ104のゲートを制御することでオペアンプ102の2つの入力が仮想短絡され、出力電圧Vref1を所望の値にする。出力電圧Vref1を調整する必要がある場合には抵抗R1,R2をトリミングする。図3に示す基準電圧トリミング回路103は、トリミング前後においても(R1+R2)は常に等しくなる。したがってプロセスばらつきを調整するトリミングを行なっても抵抗に流れる電流には影響を及ぼさず(電流を変えずに)、定電圧Vref1を得ることができる。また出力トランジスタ104のゲートを制御するオペアンプ102の出力を同じく出力トランジスタ(QP5)105のゲートにも印加する。出力トランジスタ104から定電圧Vref1が得られ、基準電圧トリミング回路103の抵抗値(R1+R2)がトリミングに対し不変であるということは、基準電圧トリミング回路103に流れる電流I1が定電流となっていることを意味している。そのため、ダイオード接続されたトランジスタ(QN3)106に流れる電流I2も定電流となり、定電流源を構成する。なお、出力トランジスタ(QP4)104および出力トランジスタ(QP5)105のチャネル幅Wとチャネル長Lの比(W/L)をそれぞれ(W4/L4)および(W5/L5)とすると、I2=I1×(W5/L5)/(W4/L4)となる。これにより、ダイオード接続のトランジスタ(QN3)106および出力トランジスタ(QP5)105も定電流源を構成する。基準電圧トリミング回路103に流れる電流I1をコピーした定電流I2がダイオード接続されたトランジスタ(QN3)106に流れ、ダイオード接続されたトランジスタ(QN3)106に流れる定電流I2をカレントミラー回路でコピーすることで、定電流ib4,ib1,ib2・・・を生成することができる。つまりトランジスタ(QN4)107,トランジスタ(QN5)108,トランジスタ(QN6)108がそれぞれダイオード接続されたトランジスタ(QN3)106とカレントミラー回路を構成することにより、ダイオード接続されたトランジスタ(QN3)106に流れる電流I2をコピーした電流ib4,ib1,ib2を生成すること
ができる。なお、トランジスタ(QN3)106と組み合わされて(第1の)カレントミラー回路を構成するトランジスタ(QN4)107,(第2の)カレントミラー回路を構成するトランジスタ(QN5)108,(第3の)カレントミラー回路を構成するトランジスタ(QN6)108の寸法比をトランジスタ(QN3)106と同じものにすればib4,ib1,ib2はそれぞれ電流I2と同じものにすることができ、寸法比を変えることでib4,ib1,ib2の電流値を任意に設定することもでき、各カレントミラー回路で生成されたib4,ib1,ib2の電流を図5に示す発振器、誤差増幅器、コンパレータなどを動作させるための基準電流又はバイアス電流として用いることができる。
The operation of the constant current / constant voltage circuit shown in FIG. 1 will be described. In FIG. 1, a reference voltage generation circuit 100 is configured by a reference voltage generation circuit using a known depletion MOSFET, a bandgap reference circuit, or the like, and the output voltage variation with respect to temperature and power supply voltage is small. The output Vref of the reference voltage generation circuit 100 is input to the − side input terminal of the operational amplifier 102, and the output voltage Vout of the reference voltage trimming circuit 103 shown in FIG. 3 is input to the + side input terminal of the operational amplifier 102. Are compared. Then, the output of the operational amplifier 102 controls the gate of the output transistor 104, whereby the two inputs of the operational amplifier 102 are virtually shorted, and the output voltage Vref1 is set to a desired value. When it is necessary to adjust the output voltage Vref1, the resistors R1 and R2 are trimmed. In the reference voltage trimming circuit 103 shown in FIG. 3, (R1 + R2) is always equal before and after trimming. Therefore, even if trimming for adjusting process variations is performed, the constant current Vref1 can be obtained without affecting the current flowing through the resistor (without changing the current). The output of the operational amplifier 102 that controls the gate of the output transistor 104 is also applied to the gate of the output transistor (QP5) 105. The constant voltage Vref1 is obtained from the output transistor 104 and the resistance value (R1 + R2) of the reference voltage trimming circuit 103 is invariable with respect to the trimming. This means that the current I1 flowing through the reference voltage trimming circuit 103 is a constant current. Means. Therefore, the current I2 flowing through the diode-connected transistor (QN3) 106 also becomes a constant current, and constitutes a constant current source. If the ratio (W / L) of the channel width W to the channel length L of the output transistor (QP4) 104 and the output transistor (QP5) 105 is (W4 / L4) and (W5 / L5), respectively, I2 = I1 × (W5 / L5) / (W4 / L4). Thus, the diode-connected transistor (QN3) 106 and the output transistor (QP5) 105 also constitute a constant current source. A constant current I2 copied from the current I1 flowing through the reference voltage trimming circuit 103 flows through the diode-connected transistor (QN3) 106, and the constant current I2 flowing through the diode-connected transistor (QN3) 106 is copied by the current mirror circuit. Thus, the constant currents ib4, ib1, ib2,... Can be generated. That is, the transistor (QN4) 107, the transistor (QN5) 108, and the transistor (QN6) 108 each form a current mirror circuit with the diode-connected transistor (QN3) 106, thereby flowing to the diode-connected transistor (QN3) 106. Currents ib4, ib1, and ib2 obtained by copying the current I2 can be generated. The transistor (QN4) 107 constituting the (first) current mirror circuit in combination with the transistor (QN3) 106, the transistor (QN5) 108 constituting the (second) current mirror circuit, and the (third) If the dimensional ratio of the transistor (QN6) 108 constituting the current mirror circuit is made the same as that of the transistor (QN3) 106, ib4, ib1, and ib2 can be made the same as the current I2, respectively. The current values of ib4, ib1, and ib2 can be arbitrarily set, and the current for ib4, ib1, and ib2 generated by each current mirror circuit is a reference for operating the oscillator, error amplifier, comparator, etc. shown in FIG. It can be used as a current or a bias current.

また、トランジスタ(QN3)106〜トランジスタ(QN6)109を省略して、定電圧Vref1および定電流I2を出力する定電流・定電圧回路としてもよい。この場合、定電流I2は、カレントミラー回路への入力に限らず各種回路の基準電流として用いることができる。
[実施形態2]
図2は本発明の第2の実施形態に係る定電流・定電圧回路の構成を示す回路ブロック図である。図2の定電流・定電圧回路においては、図1に示した第1の実施形態に係るオペアンプ102に代えて、差動増幅器とこの差動増幅器の出力が入力されるソース接地増幅回路により基準電圧出力バッファを構成したものである。
Alternatively, the transistor (QN3) 106 to the transistor (QN6) 109 may be omitted, and a constant current / constant voltage circuit that outputs the constant voltage Vref1 and the constant current I2 may be used. In this case, the constant current I2 can be used not only as an input to the current mirror circuit but also as a reference current for various circuits.
[Embodiment 2]
FIG. 2 is a circuit block diagram showing a configuration of a constant current / constant voltage circuit according to the second embodiment of the present invention. In the constant current / constant voltage circuit of FIG. 2, a reference is provided by a differential amplifier and a common source amplifier circuit to which an output of the differential amplifier is input, instead of the operational amplifier 102 according to the first embodiment shown in FIG. A voltage output buffer is configured.

図2に示した回路を説明すると、基準電圧生成回路100は、公知のデプレッションMOSFETを用いた基準電圧生成回路やバンドギャップリファレンス回路等で構成され、温度や電源電圧に対する出力電圧変動が小さいものとなるようにされる。この点は図1に説明したのと同様である。基準電圧生成回路100の後段には、一般的に定電圧出力値を所望の電圧値に設定し、且つ図5に示すように後段の発振器、誤差増幅器、コンパレータ等を駆動するために十分な電流供給能力を確保するために、差動増幅器210と(第1の)ソース接地増幅器(以下では、単に‘ソース接地’と呼ぶ)220の2段増幅器からなる基準電圧出力バッファ200と、図1に示したおよびトリミングを行っても総抵抗値が変わらない基準電圧トリミング回路103とが設けられる。図2において基準電圧トリミング回路103は、抵抗R1(130)と抵抗R2(140)とが直列接続され抵抗R1(130)と抵抗R2(140)の接続点から出力を取り出し、これを差動増幅器210の非反転入力端子(IN+)に接続する。一方、基準電圧生成回路100の出力Vrefは差動増幅器210の反転入力端子(IN-)に与える。なお、図中の(第1の)ソース接地220を構成するトランジスタ222のゲート・ドレイン間に接続される抵抗223およびコンデンサ224は増幅器(基準電圧出力バッファ200)の発振を防ぎ、安定動作させるためのものである。   The circuit shown in FIG. 2 will be described. The reference voltage generation circuit 100 includes a known reference voltage generation circuit using a depletion MOSFET, a band gap reference circuit, and the like, and has a small output voltage variation with respect to temperature and power supply voltage. To be. This point is the same as described in FIG. In the subsequent stage of the reference voltage generating circuit 100, a constant voltage output value is generally set to a desired voltage value, and a current sufficient to drive the subsequent oscillator, error amplifier, comparator, etc. as shown in FIG. In order to ensure supply capability, a reference voltage output buffer 200 comprising a two-stage amplifier of a differential amplifier 210 and a (first) common source amplifier (hereinafter simply referred to as “source ground”) 220, and FIG. A reference voltage trimming circuit 103 is provided which does not change the total resistance value even when trimming is performed. In FIG. 2, a reference voltage trimming circuit 103 includes a resistor R1 (130) and a resistor R2 (140) connected in series, and outputs an output from a connection point between the resistor R1 (130) and the resistor R2 (140). Connected to 210 non-inverting input terminal (IN +). On the other hand, the output Vref of the reference voltage generation circuit 100 is given to the inverting input terminal (IN−) of the differential amplifier 210. Note that a resistor 223 and a capacitor 224 connected between the gate and drain of the transistor 222 constituting the (first) source ground 220 in the drawing prevent the amplifier (reference voltage output buffer 200) from oscillating and operate stably. belongs to.

基準電圧出力バッファ200の出力((第1の)ソース接地220の出力)には電圧トリミング回路103が接続され、抵抗R1(130)と抵抗R2(140)の接続点は上述したように差動増幅器210の非反転入力端子(IN+)にフィードバックされる。差動増幅器210の2つの入力間は仮想短絡となっていることから、非反転入力端子電圧と反転入力端子電圧は等しくなり、抵抗R1(130)と抵抗R2(140)の両端電圧(接続点)には反転入力端子にかかる基準電圧Vrefが現れる。このVrefと直列抵抗R1(130)と抵抗R2(140)により基準電圧出力バッファ200の出力電圧Vref1はVref1=Vref×(R1+R2)/R2となり、定電圧が得られる。ここでプロセスばらつきにより基準電圧生成回路100のVrefの値が設計値から外れたものであったとすると、Vref1には所望の電圧値が得られないため、電圧トリミング回路103の抵抗R1,R2を調整してVref1を所望の定電圧となるよう調整する。   The voltage trimming circuit 103 is connected to the output of the reference voltage output buffer 200 (the output of the (first) source ground 220), and the connection point between the resistors R1 (130) and R2 (140) is differential as described above. Feedback is provided to the non-inverting input terminal (IN +) of the amplifier 210. Since the two inputs of the differential amplifier 210 are virtually short-circuited, the non-inverting input terminal voltage and the inverting input terminal voltage are equal, and the voltage across the resistors R1 (130) and R2 (140) (connection point) ) Shows the reference voltage Vref applied to the inverting input terminal. With this Vref, series resistance R1 (130) and resistance R2 (140), the output voltage Vref1 of the reference voltage output buffer 200 becomes Vref1 = Vref × (R1 + R2) / R2, and a constant voltage is obtained. Here, if the value of Vref of the reference voltage generation circuit 100 deviates from the design value due to process variations, a desired voltage value cannot be obtained for Vref1, and thus the resistors R1 and R2 of the voltage trimming circuit 103 are adjusted. Then, adjust Vref1 to a desired constant voltage.

抵抗R1(130)と抵抗R2(140)に流れる電流I1はVref1/(R1+R2)によって決まり、Vref1は電源電圧や温度による依存性は小さいが、抵抗R1,R2は温度特性を持つため、I1はこれらの抵抗の温度特性に依存した温度特性を示す。従い、温度特性の小さい定電流を生成するためには、抵抗R1(130)および抵抗R2(140)として温度依存性のない素子または
温度依存性を打ち消しあう素子の組み合わせを選べばよい。
The current I1 flowing through the resistor R1 (130) and the resistor R2 (140) is determined by Vref1 / (R1 + R2), and Vref1 is less dependent on the power supply voltage and temperature, but the resistors R1 and R2 have temperature characteristics. I1 shows temperature characteristics depending on the temperature characteristics of these resistors. Therefore, in order to generate a constant current having a small temperature characteristic, an element having no temperature dependency or a combination of elements that cancels the temperature dependency may be selected as the resistor R1 (130) and the resistor R2 (140).

また出力電圧Vref1を調整するためには図3で説明したように抵抗R1,R2をトリミングする。このトリミング回路は前述したようにトリミング前後においても総抵抗値(R1+R2)は常に等しくなる。このような構成にすることでプロセスばらつきを調整するトリミングを行なっても抵抗R1,R2に流れる電流I1になんら影響を及ぼさず、定電流源とみなすことができる。これにより図2に示した第2の実施形態に係る定電流・定電圧回路においても特別の定電流源を設けなくても定電圧と定電流を同時に得ることができる。   In order to adjust the output voltage Vref1, the resistors R1 and R2 are trimmed as described in FIG. As described above, the total resistance value (R1 + R2) of this trimming circuit is always equal before and after trimming. With such a configuration, even if trimming for adjusting process variations is performed, the current I1 flowing through the resistors R1 and R2 is not affected at all, and can be regarded as a constant current source. Thereby, even in the constant current / constant voltage circuit according to the second embodiment shown in FIG. 2, a constant voltage and a constant current can be obtained simultaneously without providing a special constant current source.

ここまでの説明において図2に示した定電流・定電圧回路で定電流I1が得られ、電流I1は図2から分かるとおり、図中のMOSFET(QP1)221,MOSFE(QN1)222に流れる電流Ip1,In1の差となっている。また、MOSFET(QP1)221とMOSFET(QP3)202がカレントミラー回路を構成していて、MOSFET(QP1)221に流れる電流Ip1はMOSFET(QP3)202に流れる定電流((電源電圧VDD−MOSFET(QP3)202の閾値電圧)/抵抗Rb201の抵抗値)にほぼ等しい)をコピーした定電流であるから、MOSFE(QN1)222に流れる電流In1も定電流となっていることが分かる。更に、ゲート電圧をそれぞれMOSFET(QP1)221とMOSFET(QN1)222のゲート電圧と等しくし、MOSFETの寸法をそれぞれMOSFET(QP1)221とMOSFET(QN1)222と同じにしたMOSFET(QP2)231,MOSFET(QN2)232からなる第2のソース接地増幅器230を接続すると、第2のソース接地230の各トランジスタ231,232に流れる電流Ip2,In2はそれぞれ電流Ip1,In1と等しくなり、これらも定電流となる。   In the above description, the constant current I1 is obtained by the constant current / constant voltage circuit shown in FIG. 2, and the current I1 is the current flowing through the MOSFET (QP1) 221 and MOSFE (QN1) 222 in FIG. This is the difference between Ip1 and In1. Further, the MOSFET (QP1) 221 and the MOSFET (QP3) 202 constitute a current mirror circuit, and the current Ip1 flowing through the MOSFET (QP1) 221 is a constant current ((power supply voltage VDD−MOSFET ( QP3) is a constant current that is substantially equal to (the threshold voltage of 202) / the resistance value of resistor Rb201), and it can be seen that the current In1 flowing through MOSFE (QN1) 222 is also a constant current. Further, MOSFETs (QP2) 231, 231 having gate voltages equal to the gate voltages of MOSFET (QP1) 221 and MOSFET (QN1) 222, respectively, and the dimensions of the MOSFETs being the same as those of MOSFET (QP1) 221 and MOSFET (QN1) 222, respectively. When the second source grounded amplifier 230 composed of the MOSFET (QN2) 232 is connected, the currents Ip2 and In2 flowing through the transistors 231 and 232 of the second source grounded 230 become equal to the currents Ip1 and In1, respectively. It becomes.

更にトランジスタ(QP2)231とトランジスタ(QN2)232のドレイン端子同士の接続点とGND間にダイオード接続されたMOSFET(QN3)106を接続すると、これに流れる電流I2にはトランジスタ(QP2)231とMOSFET(QN2)232に流れる電流Ip2,In2の差となる電流が流れるため、定電流が得られる。   Further, when a diode-connected MOSFET (QN3) 106 is connected between the connection point between the drain terminals of the transistor (QP2) 231 and the transistor (QN2) 232 and GND, the current I2 flowing therethrough is connected to the transistor (QP2) 231 and the MOSFET. Since a current that is the difference between the currents Ip2 and In2 flowing through (QN2) 232 flows, a constant current can be obtained.

このトランジスタ(QN3)106に流れる電流I2をカレントミラー回路107,108,109・・でコピーすることで、定電流ib4,ib1,ib2,・・・を生成することができる。定電流ib4,ib1,ib2の電流値はトランジスタ(QN3)106に対するトランジスタ(QN4)107,トランジスタ(QN5)108,トランジスタ(QN6)109の寸法比を変えることで任意に設定することができ、これらを図5に示す発振器、誤差増幅器、コンパレータ等を動作させるための基準電流またはバイアス電流として用いることができる。また、MOSFET(QP1)221およびMOSFET(QN1)222に対するMOSFET(QP2)231およびMOSFET(QN2)232の寸法比を調整することにより、定電流ib4,ib1,ib2の電流値を調整することもできる。なお、電源電圧VDDが変動しても電流I2,定電流ib4,ib1,ib2が変動しないようにするために、MOSFET(QP1)221に対するMOSFET(QP2)231の寸法比とMOSFET(QN1)222に対するMOSFET(QN2)232寸法比を等しくしておくとよい。   The current I2 flowing through the transistor (QN3) 106 is copied by the current mirror circuits 107, 108, 109... To generate constant currents ib4, ib1, ib2,. The current values of the constant currents ib4, ib1, and ib2 can be arbitrarily set by changing the dimensional ratio of the transistor (QN4) 107, the transistor (QN5) 108, and the transistor (QN6) 109 with respect to the transistor (QN3) 106. Can be used as a reference current or bias current for operating the oscillator, error amplifier, comparator, etc. shown in FIG. The current values of the constant currents ib4, ib1, and ib2 can also be adjusted by adjusting the dimensional ratio of the MOSFET (QP2) 231 and the MOSFET (QN2) 232 to the MOSFET (QP1) 221 and the MOSFET (QN1) 222. . In order to prevent the current I2, the constant currents ib4, ib1, and ib2 from fluctuating even when the power supply voltage VDD fluctuates, the dimensional ratio of the MOSFET (QP2) 231 to the MOSFET (QP1) 221 and the MOSFET (QN1) 222 The dimensional ratio of MOSFET (QN2) 232 should be equal.

図2に示した定電流・定電圧回路においては第2のソース接地230を含めた基準電圧出力バッファ200にて基準電流を生成するため、基準電圧出力バッファ200自体を駆動するための基準電流ib(これは図2に示すように、差動増幅器200,第1のソース接地220および第2のソース接地230のバイアス電流を決定する電流である)については、別途に基準電流ibを生成する回路が必要となる。しかし基準電流ibは基準電圧出力バッファ200を動作させるための精度があれば十分であることから、図2の左端に示すような抵抗Rb201を用いた簡易定電流源でよい。この基準電流ibの電源電圧、温度に対する変動を抑えたい場合の簡便な電流源回路として、例えば図4に示す回路を用いることもできる。すなわち図4は本発明の第2の実施形態に係る基準電圧出力バッファの基準電流を生成する電流源回路であり、NPNトランジスタ(QB1)301のベース・エミッタ間
電圧VBE(=ダイオード順方向電圧)を抵抗R3(302)に印加して得られる電流VBE/R3を、MOSFET(QN7)303を通じてMOSFET(QP3)304(図2に示したMOSFET(QP3)202に同じ)に流すようにしたものである。このような簡便な定電流源を用いれば回路規模を大幅に大きくすることなく、抵抗Rb201を使う場合よりも電源電圧変動に対する電流変動を小さくすることができる。
In the constant current / constant voltage circuit shown in FIG. 2, the reference current is generated by the reference voltage output buffer 200 including the second source ground 230, and therefore the reference current ib for driving the reference voltage output buffer 200 itself. (This is a current that determines the bias current of the differential amplifier 200, the first source ground 220, and the second source ground 230, as shown in FIG. 2.) A circuit that separately generates a reference current ib Is required. However, since the reference current ib need only be accurate to operate the reference voltage output buffer 200, a simple constant current source using a resistor Rb201 as shown at the left end of FIG. For example, the circuit shown in FIG. 4 can be used as a simple current source circuit when it is desired to suppress fluctuations of the reference current ib with respect to the power supply voltage and temperature. That is, FIG. 4 shows a current source circuit for generating a reference current of the reference voltage output buffer according to the second embodiment of the present invention. The base-emitter voltage VBE (= diode forward voltage) of the NPN transistor (QB1) 301 is shown in FIG. Is applied to the resistor R3 (302), and the current VBE / R3 obtained through the MOSFET (QN7) 303 is passed through the MOSFET (QP3) 304 (same as the MOSFET (QP3) 202 shown in FIG. 2). is there. If such a simple constant current source is used, the current fluctuation with respect to the power supply voltage fluctuation can be made smaller than when the resistor Rb 201 is used without significantly increasing the circuit scale.

本発明の第1の実施形態に係る定電流・定電圧回路の構成を示す回路ブロック図である。1 is a circuit block diagram showing a configuration of a constant current / constant voltage circuit according to a first embodiment of the present invention. 本発明の第2の実施形態に係る定電流・定電圧回路の構成を示す回路ブロック図である。It is a circuit block diagram which shows the structure of the constant current and constant voltage circuit which concerns on the 2nd Embodiment of this invention. 本発明の実施形態に係る定電流・定電圧回路に用いる基準電圧トリミング回路を示す図である。It is a figure which shows the reference voltage trimming circuit used for the constant current and constant voltage circuit which concerns on embodiment of this invention. 本発明の第2の実施形態に係る基準電圧出力バッファの基準電流を生成する電流源回路を示す図である。It is a figure which shows the current source circuit which produces | generates the reference current of the reference voltage output buffer which concerns on the 2nd Embodiment of this invention. 従来の定電流・定電圧回路の構成を示すブロック図である。It is a block diagram which shows the structure of the conventional constant current and constant voltage circuit.

符号の説明Explanation of symbols

100 基準電圧生成回路
102 オペアンプ(OP1)
103 トリミング回路
104 (第1の)出力トランジスタ
105 (第2の)出力トランジスタ
106 ダイオード接続トランジスタ
107 (第1の)カレントミラー回路
108 (第2の)カレントミラー回路
109 (第3の)カレントミラー回路
200 基準電圧出力バッファ
210 差動増幅器
220 (第1の)ソース接地増幅器
230 (第2の)ソース接地増幅器
301 NPNトランジスタ
302 抵抗
303 MOSFET
304 MOSFET
100 Reference voltage generator
102 Operational amplifier (OP1)
103 Trimming circuit
104 (first) output transistor
105 (second) output transistor
106 Diode-connected transistor
107 (First) current mirror circuit
108 (second) current mirror circuit
109 (Third) current mirror circuit
200 Reference voltage output buffer
210 Differential Amplifier
220 (First) Common Source Amplifier
230 (second) common source amplifier
301 NPN transistor
302 resistance
303 MOSFET
304 MOSFET

Claims (8)

基準電圧生成回路、基準電圧出力バッファおよびトリミングがなされる分圧抵抗を有する定電流・定電圧回路において、前記基準電圧出力バッファの出力は第1のMOSFETのゲートに接続され、該第1のMOSFETのドレインは前記分圧抵抗に接続され、該分圧抵抗はトリミングにより抵抗を調整しても分圧比が変わるのみで抵抗値の総和は同じとなるようにされ、前記第1のMOSFETのドレイン電圧の前記分圧抵抗による分圧および前記基準電圧生成回路の出力が前記基準電圧出力バッファに入力され、さらに前記第1のMOSFETと同じ導電型の第2のMOSFETを前記第1のMOSFETに並列に接続し、前記第2のMOSFETの電流出力および前記第1のMOSFETのドレイン電圧をそれぞれ前記定電流・定電圧回路の定電流出力および定電圧出力とすることを特徴とする定電流・定電圧回路。   In a constant current / constant voltage circuit having a reference voltage generation circuit, a reference voltage output buffer, and a voltage dividing resistor to be trimmed, an output of the reference voltage output buffer is connected to a gate of a first MOSFET, and the first MOSFET The drain of the first MOSFET is connected to the voltage dividing resistor, and even if the resistance of the voltage dividing resistor is adjusted by trimming, only the voltage dividing ratio is changed and the sum of the resistance values is made the same. The voltage divided by the voltage dividing resistor and the output of the reference voltage generation circuit are input to the reference voltage output buffer, and a second MOSFET having the same conductivity type as that of the first MOSFET is connected in parallel to the first MOSFET. And connecting the current output of the second MOSFET and the drain voltage of the first MOSFET to a constant current output and a constant voltage output of the constant current / constant voltage circuit, respectively. Pressure circuit. 基準電圧生成回路、基準電圧出力バッファおよびトリミングがなされる分圧抵抗を有する定電流・定電圧回路において、前記基準電圧出力バッファの出力は第1のMOSFETのゲートに接続され、該第1のMOSFETのドレインは前記分圧抵抗に接続され、該分圧抵抗はトリミングにより抵抗を調整しても分圧比が変わるのみで抵抗値の総和は同じとなるようにされ、前記第1のMOSFETのドレイン電圧の前記分圧抵抗による分圧および前記基準電圧生成回路の出力が前記基準電圧出力バッファに入力され、さらに前記第1のMOSFETと同じ導電型の第2のMOSFETを前記第1のMOSFETに並列に接続し、該第2のMOSFETの出力にダイオード接続された前記第1のMOSFETとは別の導電型の第3のMOSFETを接続し、該第3のMOSFETにカレントミラー回路を接続し、該カレントミラーの電流出力および前記第1のMOSFETのドレイン電圧をそれぞれ前記定電流・定電圧回路の定電流出力および定電圧出力とすることを特徴とする定電流・定電圧回路。   In a constant current / constant voltage circuit having a reference voltage generation circuit, a reference voltage output buffer, and a voltage dividing resistor to be trimmed, an output of the reference voltage output buffer is connected to a gate of a first MOSFET, and the first MOSFET The drain of the first MOSFET is connected to the voltage dividing resistor, and even if the resistance of the voltage dividing resistor is adjusted by trimming, only the voltage dividing ratio is changed and the sum of the resistance values is made the same. The voltage divided by the voltage dividing resistor and the output of the reference voltage generation circuit are input to the reference voltage output buffer, and a second MOSFET having the same conductivity type as that of the first MOSFET is connected in parallel to the first MOSFET. A third MOSFET having a conductivity type different from that of the first MOSFET diode-connected to the output of the second MOSFET, a current mirror circuit connected to the third MOSFET, and the current MOSFET Mirror Constant current and constant voltage circuit, characterized in that the flow output and the drain voltage of the first MOSFET and the constant current output and the constant voltage output of each of the constant current and constant voltage circuit. 前記第3のMOSFETに複数のカレントミラー回路を並列接続したことを特徴とする請求項1または2に記載の定電流・定電圧回路。   3. The constant current / constant voltage circuit according to claim 1, wherein a plurality of current mirror circuits are connected in parallel to the third MOSFET. 前記トリミングにより抵抗を調整しても分圧比が変わるのみで抵抗値の総和は同じとなる分圧抵抗は、複数の抵抗の直列接続からなる第1の抵抗群と、該第1の抵抗群と同数且つ対応する抵抗の値が同じにされた抵抗の直列接続からなる第2の抵抗群とが直列接続されてなり、トリミング対象の抵抗にはその両端を短絡可能にするMOSFETを各々設け、前記第1の抵抗群と前記第2の抵抗群の対応する2つの抵抗にそれぞれ設けられた2つの前記MOSFETのゲートに異なる2値信号が入力されるようにし、前記対応する2つの抵抗の一方のみがトリミングされるよう構成したことを特徴とする請求項1ないし3のいずれか1項に記載の定電流・定電圧回路。   Even if the resistance is adjusted by the trimming, only the voltage dividing ratio is changed and the total sum of the resistance values is the same. The voltage dividing resistors include a first resistor group composed of a plurality of resistors connected in series, and the first resistor group. A second resistor group consisting of a series connection of resistors having the same number and corresponding resistance values are connected in series, and each of the trimming resistors is provided with a MOSFET capable of short-circuiting both ends thereof, Different binary signals are input to the gates of the two MOSFETs respectively provided in the two corresponding resistors of the first resistor group and the second resistor group, and only one of the corresponding two resistors is input. 4. The constant current / constant voltage circuit according to claim 1, wherein the constant current / voltage circuit is trimmed. 基準電圧生成回路、基準電圧出力バッファおよび該基準電圧出力バッファの出力電圧を分圧する分圧抵抗を有し、該分圧回路による分圧および前記基準電圧生成回路の出力が前記基準電圧出力バッファに入力され、前記基準電圧出力バッファは、相補関係にある2つのMOSFETを直列接続して構成される第1の出力段と、該第1の出力段に並列接続され相補関係にある2つのMOSFETを直列接続して構成される第2の出力段を備え、前記分圧回路は前記第1の出力段に接続され、前記第2の出力段を構成する前記2つのMOSFETの接続点にカレントミラー回路を接続してなる定電流・定電圧回路。   A reference voltage generation circuit, a reference voltage output buffer, and a voltage dividing resistor for dividing the output voltage of the reference voltage output buffer; and the voltage division by the voltage dividing circuit and the output of the reference voltage generation circuit are stored in the reference voltage output buffer The reference voltage output buffer includes a first output stage configured by connecting two complementary MOSFETs in series, and two complementary MOSFETs connected in parallel to the first output stage. A second output stage configured in series; the voltage divider circuit is connected to the first output stage; and a current mirror circuit at a connection point of the two MOSFETs constituting the second output stage Constant current / constant voltage circuit. 前記基準電圧出力バッファは差動増幅回路を有し、該差動増幅回路と前記第1の出力段が2段増幅回路を構成し、前記第1および第2の出力段がソース接地増幅回路であることを特徴とする請求項5記載の定電流・定電圧回路。   The reference voltage output buffer includes a differential amplifier circuit, the differential amplifier circuit and the first output stage constitute a two-stage amplifier circuit, and the first and second output stages are source-grounded amplifier circuits. 6. The constant current / constant voltage circuit according to claim 5, wherein: 前記基準電圧出力バッファの出力電圧を分圧する前記分圧抵抗は、プロセスばらつき等による出力電圧変動を抵抗値の分圧比調節により抑えるトリミング回路を含み、且つトリ
ミングにより抵抗を調整しても分圧比が変わるのみで抵抗値の総和は同じとなるよう構成した請求項5または6記載の定電流・定電圧回路。
The voltage dividing resistor that divides the output voltage of the reference voltage output buffer includes a trimming circuit that suppresses output voltage fluctuations due to process variations and the like by adjusting the voltage dividing ratio of the resistance value, and the voltage dividing ratio is maintained even if the resistance is adjusted by trimming. 7. The constant current / constant voltage circuit according to claim 5, wherein the total sum of resistance values is the same only by changing.
前記分圧抵抗は、複数の抵抗の直列接続からなる第1の抵抗群と、該第1の抵抗群と同数且つ対応する抵抗の値が同じにされた抵抗の直列接続からなる第2の抵抗群とが直列接続されてなり、トリミング対象の抵抗にはその両端を短絡可能にするMOSFETを各々設け、前記第1の抵抗群と前記第2の抵抗群の対応する2つの抵抗にそれぞれ設けられた2つのMOSFETのゲートに異なる2値信号が入力されるようにし、前記対応する2つの抵抗の一方のみがトリミングされるよう構成したことを特徴とする請求項5ないし7のいずれか1項に記載の定電流・定電圧回路。   The voltage dividing resistor includes a first resistor group composed of a plurality of resistors connected in series, and a second resistor composed of a series connection of resistors having the same number and corresponding resistance values as the first resistor group. The resistors to be trimmed are respectively provided with MOSFETs that can short-circuit both ends of the resistors, and are provided for the corresponding two resistors of the first resistor group and the second resistor group, respectively. 8. The method according to claim 5, wherein different binary signals are inputted to the gates of the two MOSFETs, and only one of the corresponding two resistors is trimmed. The constant current / constant voltage circuit described.
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