JP2007094800A - Reference voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress channel-length-modulation effect and substrate effect of a depression-type NMOS transistor that is a reference current source, and to allow operation at low power supply voltage. <P>SOLUTION: In the depression-type NMOS transistor 1 that is the reference current source, the gate, the source and the back gate thereof are connected to the ground, while the drain is connected to a first bias output terminal 51a of a bias circuit 51, an input terminal 52a of a current mirror circuit 52, and an inverting input terminal of an operational amplifier 53. In a first enhancement-type NMOS transistor 11, the source and the back gate thereof are connected to the ground, the gate is connected to the output terminal of the operational amplifier 53, the drain is connected to a second bias output terminal 51b of the bias circuit 51, the output terminal 52b of the current mirror circuit 52, and a non-inverting input terminal of the operational amplifier 53, so that a reference voltage VREF can be obtained as output of the operational amplifier 53. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a reference voltage generation circuit using a MOS transistor, and more particularly to a circuit for improving operational characteristics such as suppression of fluctuations in output voltage accompanying fluctuations in power supply voltage.

Conventionally, as this type of circuit, for example, the circuit shown in FIG.
Hereinafter, this conventional circuit will be described with reference to FIG.
First, the schematic circuit configuration of this conventional reference voltage generating circuit will be described. An operational amplifier 61 functioning as a differential amplifier, a depletion type NMOS transistor MD11 (hereinafter referred to as “transistor MD11”), and an enhancement type NMOS The transistor MN1 (hereinafter referred to as “transistor MN11”) is configured as a main component.
The transistor MD11 has its gate and back gate connected to the ground, while the drain is supplied with the power supply voltage VDD via the resistor R12, and the connection point between the drain and the resistor R12 is the operational amplifier 61. Is connected to the inverting input terminal.

The transistor MN11 has a back gate connected to the ground, and a drain to which the power supply voltage VDD is applied via the resistor 11.
Further, the sources of the transistor MD11 and the transistor MN11 are connected to each other, and a constant current source 62 that outputs a constant current Ibias2 is connected between the connection point and the ground.
The gate of the transistor MN11 is connected together with the output terminal of the operational amplifier 61 and is connected to the output terminal 63 of the reference voltage VREF.

In such a configuration, the output current Ibias2 of the constant current source 62 is shunted as the respective drain currents of the transistor MD11 and the transistor MN11. The resistors R11 and R12 have the same resistance value.
Under such a premise, for example, when the drain current of the transistor MD11 is larger than the drain current of the transistor MN11, the drain voltage of the transistor MN11 becomes higher than the drain voltage of the transistor MD11. As a result, the output voltage of the operational amplifier 61 increases. At the same time, the gate voltage of the transistor MN11 rises and the drain current increases. Therefore, the drain current of the transistor MD11 decreases, and the drain currents of the transistors MN11 and MD11 are balanced.

  On the other hand, when the drain current of the transistor MD11 is smaller than the drain current of the transistor MN11, the drain voltage of the transistor MN11 becomes lower than the drain voltage of the transistor MD11, the output voltage of the operational amplifier 61 decreases, and at the same time the gate voltage of the transistor MN11. As a result, the drain current decreases. Therefore, the drain current of the transistor MD11 increases, and the drain currents of the transistor MN11 and the transistor MD11 are balanced.

  Such an operation is performed as a small signal, and the inverting input terminal and the non-inverting input terminal of the operational amplifier 61 are virtually short-circuited. That is, in other words, the gate voltage of the transistor MN11 is controlled so that the drain voltage of the transistor MD11 and the drain voltage of the transistor MN11 are equal, the drain currents of the transistors MD11 and MN11 are also equal, and stable operation is achieved. The output voltage of the amplifier 61 is output as a stable reference voltage VREF.

  Here, the reference voltage VREF can be expressed as Equation 1 below.

VREF = VTEN−VTDn + (Ibias2 / 2) ^1/2 {(1 / (KE) ^1/2 + 1 / (KD) ^1/2 )} Equation 1

  KE = (μEn · Cox / 2) (W / L) MN11 Equation 2

  KD = (μDn · Cox / 2) (W / L) MD11 Equation 3

  Here, VTEn, μEn, (W / L) MN11 are the threshold voltage, mobility, and size of the transistor MN11, respectively, and VTDn, μDn, (W / L) MD11 are the threshold voltage, mobility, of the transistor MD11, respectively. Is the size. Cox is a capacity per unit area of the gate oxide film, and VTDn <0.

  According to the previous Non-Patent Document 1, in Equation 1, the temperature characteristic of the threshold voltage difference (VTEn−VTDn) in the previous term has a negative temperature gradient. 3 is related to mobility and has a positive temperature gradient, so the negative temperature gradient in the previous term can be canceled out, and the temperature coefficient of the reference voltage is dominated by temperature change of mobility. It is clear that the temperature is positive in the low temperature region, close to zero at room temperature, and negative in the high temperature region where the temperature change of the threshold is dominant.

As a conventional circuit, a circuit as shown in FIG. 7 has also been proposed (see Patent Document 1).
The conventional circuit will be described below with reference to FIG.
The reference voltage generation circuit includes two enhancement type PMOS transistors MP11 and MP12 (hereinafter referred to as “transistor MP11” and “transistor MP12”, respectively) constituting a current mirror, and a depletion type NMOS transistor MD12 that functions as a constant current source. (Hereinafter referred to as “transistor MD12”) and enhancement type NMOS transistors MN12 and NM13 (hereinafter referred to as “transistor MN12” and “transistor NM13”, respectively) constituting the output stage, as two main components. The voltages VREF1 and VREF2 are configured to be obtained.

In such a configuration, the current supplied to the transistor MP11 by the transistor MD12 also flows to the transistor MP12 by the current mirror operation.
When the gate voltage of the transistor MN12 is low and the drain current is smaller than the current flowing through the transistor MP12, the gate voltage of the transistor MN13 increases, the gate-source voltage increases, the source current increases, and at the same time, the resistor The current flowing into 14 will increase.

On the contrary, when the gate voltage of the transistor MN12 is high and the drain current is higher than the current flowing through the transistor MP12, the gate voltage of the transistor MN13 decreases, the current flowing through the resistor 14 decreases, and the gate voltage of the transistor MN12 decreases. And the drain current decreases.
Therefore, the transistor MN12 operates so that the gate voltage is determined so that the drain current is the same as the drain current of the transistor MP12. In this state, the gate voltage of the transistor MN12 becomes the voltage value of the reference voltage VREF1.
At the same time, the voltage value of the reference voltage VREF2 is determined by the drain (source) current of the transistor MN13 and the resistor 13 in this case.

  In Patent Document 1, the reference voltage can be determined based on the threshold voltage of a depletion type NMOS transistor and the threshold voltage of an enhancement type NMOS transistor having good temperature characteristics in relation to the above circuit. It has been shown that flat characteristics can be obtained with respect to changes.

R.A.Blauschild, P.A.Tucci, R.S.Muller and R.G.Meyer, “A new NMOS temperature-stable voltage reference”, IEEE J. Solid-State Circuits, vol. SC-13, pp.767-777, Dec.1978 Japanese Patent No. 3519958

  By the way, the current characteristics in the saturation region of the depletion type or enhancement type NMOS transistor are expressed by the following equations (4) and (5).

ID = (μn · Cox / 2) (W / L) (VGS−VTHn) ² (1−λVDS) Equation 4

VTHn = VTHn0 + γ {(VSB + 2ΦF) ^1/2 − (2ΦF) ^1/2 } Equation 5

  Where ID is the drain current, μn is the mobility of the NMOS transistor, Cox is the capacitance per unit area of the gate oxide film, W is the channel width, L is the channel length, VGS is the gate voltage to the source, VTHn is the threshold voltage, λ is a channel length modulation coefficient, VTHn0 is a threshold voltage when the source voltage is 0 V with respect to the substrate, that is, a so-called substrate zero bias, γ is a substrate effect coefficient, VSB is a source voltage with respect to the substrate, and ΦF is a Fermi level .

  Further, the source voltage of the transistor MD11 in the conventional circuit shown in FIG.

VS (MD11) = VREF−VGS (MN11) = VREF − {(Ibias2 / 2KE) ^1/2 + VTHn} Expression 6

  That is, the source voltage of the transistor MD11 is a voltage lower than the reference voltage VREF by the gate-source voltage VGS of the enhancement type NMOS transistor. Therefore, in the depletion type transistor MD11, the source voltage becomes higher than the gate voltage. The source-to-source voltage becomes negative, and the source voltage becomes higher than the substrate voltage, and the threshold voltage VTHn increases due to the substrate effect in Equation 5 described above. Thus, when the gate-source voltage VGS (MD11) is negative and the threshold voltage VTHn increases, the threshold current VTHDn of the depletion type NMOS transistor is negative. When the source voltage VGS (MD11) = 0, it becomes smaller than the drain current at the time of substrate zero bias. Therefore, when a process having a large substrate effect is used, in the conventional circuit shown in FIG. 6, the drain current of the depletion type transistor MD11 is difficult to flow and is not equal to the drain current of the transistor MN11. As a result, the problem arises that an appropriate reference voltage cannot be obtained.

  On the other hand, in the conventional circuit shown in FIG. 7, the back gate of the transistor MD12, which is a reference current source, is connected to the source, so that there is no influence of the substrate effect as described above. However, in the current mirror circuit composed of the transistors MP11 and MP12, since the gate and drain of the transistor MP11 are connected, the drain-source voltage becomes almost constant with respect to a slight current change, and the power supply voltage VDD is When the voltage changes, the drain-source voltage fluctuates in the transistor MD12, and the drain current changes due to the channel length modulation effect as shown in Equation 1 above.

  Such a change in the drain current also changes the drain current of the transistor MN12 that generates the reference voltage due to the mirroring of the current in the current mirror circuit, resulting in a change in the reference voltage. For this reason, the circuit configuration shown in FIG. 7 has a problem that the reference voltage is easily affected by the power supply voltage fluctuation due to the channel length modulation effect of the transistor MD12.

  The present invention has been made in view of the above circumstances, and a depletion type NMOS transistor serving as a reference current source is not affected by the substrate effect and the channel length modulation effect, and operates at a low power supply voltage, and has temperature characteristics. A reference voltage generation circuit capable of generating a good reference voltage is provided.

In order to achieve the above object of the present invention, a reference voltage generating circuit according to the present invention includes:
A depletion type NMOS transistor provided to act as a reference current source and an enhancement type NMOS transistor provided so that the current of the depletion type NMOS transistor is supplied through a current mirror circuit are equalized by a bias circuit. A reference voltage generation circuit configured to output a difference between both drain voltages as a reference voltage.
The depletion type NMOS transistor has a gate, a source, and a back gate connected to a first power supply, and a drain that is one of a first bias output terminal of the bias circuit, an input terminal of the current mirror circuit, and an operational amplifier. Connected to the input terminals of
The enhancement type NMOS transistor has a source and a back gate connected to a first power supply, a gate connected to an output terminal of the operational amplifier, a drain connected to a second bias output terminal of the bias circuit, and the current It is connected to the output terminal of the mirror circuit and the other input terminal of the operational amplifier, respectively, so that a reference voltage can be output to the output terminal of the operational amplifier.
In such a configuration, two resistors are connected in series between the output terminal of the operational amplifier and the first power supply, and the connection point between the two resistors is connected to the gate of the enhancement type NMOS transistor. It is also suitable.
In addition, it is preferable that a passive element or an active element is connected between at least one drain of the depletion type NMOS transistor and the enhancement type NMOS transistor and the first power supply.
The current mirror circuit includes second and third enhancement type NMOS transistors. The second and third enhancement type NMOS transistors have gates connected to each other, and sources are both first. Connected to the power supply
The drain and gate of the second enhancement type NMOS transistor are connected to each other, and the connection point is an input terminal.
It is also preferable that the drain of the third enhancement type NMOS transistor is an output terminal.
Further, the bias circuit includes first and second enhancement type PMOS transistors, and the first and second enhancement type PMOS transistors have gates connected to each other and a bias voltage applied thereto. On the other hand, the second power supply voltage is applied to each of the sources, the drain of the first enhancement type PMOS transistor is used as the first bias output terminal, and the drain of the second enhancement type PMOS transistor is used as the second bias. A bias output terminal is also suitable.

According to the present invention, since the back gate of the depletion type NMOS transistor is connected to the source, there is no substrate effect, and the amplifier that controls the gate of the enhancement type NMOS also serves as a buffer to output the reference voltage. The effect that the impedance can be reduced is achieved.
Further, in the configuration in which the output voltage of the operational amplifier is divided by resistance and the divided voltage is applied to the gate of the first enhancement type PMOS transistor, the reference voltage output is set to a desired magnitude by the resistor. Can be set.
Further, in a configuration in which a passive element or an active element is connected between at least one drain of the depletion type NMOS transistor and the enhancement type NMOS transistor and the first power supply, the depletion type NMOS transistor and the enhancement type NMOS transistor The operating point at the drain of the operational amplifier, that is, the operating point at the two input terminals of the operational amplifier can be stabilized, thereby improving the stability of the entire circuit. In addition, depending on the element connected between at least one drain of the depletion type NMOS transistor and the enhancement type NMOS transistor and the first power supply, the drain voltage of the depletion type NMOS transistor is almost equal regardless of the second power supply voltage. Therefore, the channel length modulation effect can be eliminated from the drain current of the depletion type NMOS transistor.
In the case where the current mirror circuit is configured using the second and third enhancement type NMOS transistors, the second enhancement type NMOS transistor is diode-connected, and the drain-source voltage of the depletion type NMOS transistor. Is the gate-source voltage of the second enhancement type NMOS transistor, and since the drain current of the second enhancement type NMOS transistor is substantially constant, the drain-source voltage of the depletion type NMOS transistor is also constant. Therefore, the channel length modulation effect of the drain current of the depletion type NMOS transistor can be eliminated. In addition, by using a current mirror circuit having a simple circuit configuration, the circuit of the portion formed by the depletion type NMOS transistor and the first enhancement type NMOS transistor can be simplified.
Further, in the case where the bias circuit is configured using the first and second enhancement type PMOS transistors, the minimum voltage between the second power source and the first and second bias output terminals of the bias circuit is Since this is the minimum saturation voltage of the PMOS transistor, the second power supply can be lowered.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the reference voltage generation circuit according to the embodiment of the present invention will be described with reference to FIG.
The reference voltage generation circuit in the first configuration example includes a first depletion type NMOS transistor (denoted as “MD1” in FIG. 1 and hereinafter referred to as “first depletion NMOS”) 1, Enhancement type NMOS transistor (referred to as “MN1” in FIG. 1 and hereinafter referred to as “first enhancement NMOS”) 11, and a bias current to the first depletion NMOS 1 and the first enhancement NMOS 11 The bias circuit 51, the current mirror circuit 52, and the operational amplifier (indicated as “OP” in FIG. 1) 53 are configured as main components.

Hereinafter, a specific circuit connection will be described. First, the first depletion NMOS 1 has its gate, source, and back gate all connected to the ground as the first power supply, while its drain is the first depletion of the bias circuit 51. 1 is connected to a bias output terminal (denoted as “BIAS1” in FIG. 1) 51 a, an input terminal (denoted as “IN” in FIG. 1) 52 a and an inverting input terminal of an operational amplifier 53. Connected to.
In the first enhancement NMOS 11, the source and the back gate are both connected to the ground, and the gate is connected to the reference voltage output terminal 35 together with the output terminal of the operational amplifier 53. Further, the drain of the first enhancement NMOS 11 is connected to a second bias output terminal (indicated as “BIAS2” in FIG. 1) 51b of the bias circuit 51, and a non-inverting input terminal of the operational amplifier 53 and a current mirror. The circuit 52 is connected to an output terminal (indicated as “OUT” in FIG. 1) 52b. The current mirror circuit 52 has a current mirror circuit power supply terminal 52c connected to the ground.

In the bias circuit 51, a power supply voltage VDD (second power supply voltage) is applied to the power supply terminal 51c for the bias circuit, and the required bias current is output to the first and second bias output terminals 51a and 51b, respectively. It has been configured.
The operational amplifier 53 constitutes a differential amplifier by being connected as described above.

Next, the operation in the above configuration will be described.
First, the bias current Ib having the same current value is output from the first and second bias output terminals 51a and 51b of the bias circuit 51, the input current of the input terminal 52a of the current mirror circuit 52, and the output terminal 52b Assume that the output currents are equal and the magnitude is Ic.
Under this assumption, the drain current IMD1 of the first depletion NMOS 1 and the drain current IMN1 of the first enhancement NMOS 11 are expressed as follows.

  IMD1 = Ib-Ic Equation 7

  IMN1 = Ib-Ic Equation 8

That is, it can be understood that the drain current IMD1 of the first depletion NMOS 1 and the drain current IMN1 of the first enhancement NMOS 11 are equal.
Here, if the drain current IMD1 and the drain current IMN1 are not equal, the following operation is performed.
First, when the drain current IMN1 is smaller than the drain current IMD1, the following inequality is established on the first enhancement NMOS 11 side.

  Ib> IMN1 + Ic Formula 9

  Therefore, the drain voltage of the first enhancement NMOS 11 is higher than the drain voltage of the first depletion NMOS 1, that is, the voltage at the non-inverting input terminal of the operational amplifier 53 is higher than that of the inverting input terminal. The output voltage of the operational amplifier 53 increases, the gate voltage of the first enhancement NMOS 11 also increases, and the drain current IMN1 increases.

  Conversely, when the drain current IMN1 is larger than the drain current IMD1, the following inequality is established on the first enhancement NMOS 11 side.

  Ib <IMN1 + Ic Equation 10

Therefore, the drain voltage of the first enhancement NMOS 11 is lower than the drain voltage of the first depletion NMOS 1, that is, the voltage at the non-inverting input terminal is lower than the inverting input terminal of the operational amplifier 53. The output voltage decreases, the gate voltage of the first enhancement NMOS 11 also decreases, and the drain current IMN1 decreases.
The operation as described above is performed in a small signal, and the drain current IMN1 becomes equal to the drain current IMD1, so that the operation is stabilized. The reference voltage VREF can be obtained as the output of the operational amplifier 53 when the stable operation state is reached, and the magnitude thereof can be obtained as follows.

  First, the drain current IMD1 of the first depletion NMOS 1 is as follows.

IMD1 = KD · VTDn ² Equation 11

  KD = (μDn · Cox / 2) (W / L) MD1 Equation 12

  The drain current IMN1 of the first enhancement NMOS 11 is as follows.

IMN1 = KE · (VREF−VTEn) ² Equation 13

  KE = (μEn · Cox / 2) (W / L) MN1 Equation 14

  Then, the reference voltage VREF is obtained as follows from the equations 11 and 13.

VREF = VTEN + (KD / KE) ^1/2 · | VTDn |

Here, VTEn, μEn, and (W / L) MN1 are the threshold voltage, mobility, and size of the first enhancement NMOS 11, respectively. VTDn, μDn, and (W / L) MD1 are the first depletion NMOS1, respectively. Threshold voltage, mobility, and size. Cox is a capacity per unit area of the gate oxide film, and VTDn <0.
From this equation 15, it can be said that the reference voltage VREF is substantially the sum of the threshold voltages of the first enhancement NMOS 11 and the first depletion NMOS 1.

  From equations 12 and 14, it is understood that the temperature characteristic of the reference voltage VREF can be reduced by adjusting the ratio KD / KE in equation 15 according to the respective transistor sizes. it can.

Next, a second configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
This second configuration example is different from the first configuration example described above in that the output voltage of the operational amplifier 53 is divided by resistance and applied to the gate of the first enhancement NMOS 11. The part is the same as in the first configuration example.
That is, first and second resistors (represented as “R1” and “R2” in FIG. 1) 31 and 32 are connected in series between the output terminal of the operational amplifier 53 and the ground, respectively. The connection point between the first resistor 31 and the second resistor 32 is connected to the gate of the first enhancement NMOS 11.

  In such a configuration, the basic circuit operation is the same as that of the first configuration example described above, and the reference voltage VREF is expressed by the following Expression 16. R1 and R2 are the resistance values of the first and second resistors 31 and 32, respectively, for convenience.

VREF = (1 + R1 / R2) {VTen + (KD / KE) ¹ / 2.multidot. | VTDn |} Equation 16

Next, a third configuration example will be described with reference to FIG.
The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.
In this third configuration example, the input operating point is further stabilized by adding a diode as a passive element.
Hereinafter, a specific circuit configuration will be described. First, the first diode 5 (denoted as “D1” in FIG. 3) has an anode at the drain of the first depletion NMOS 1 and a cathode at the ground. Connected and provided. The second diode 6 (denoted as “D2” in FIG. 3) is provided with its anode connected to the drain of the first enhancement NMOS 11 and its cathode connected to the ground.
When the drain current of the first depletion NMOS 1 and the drain current of the first enhancement NMOS 11 are made equal, the first and second diodes 5 and 6 have the same shape.

In such a configuration, the drain voltages of the first depletion NMOS 1 and the first enhancement NMOS 11 are around 0.6 V due to the first and second diodes 5 and 6 as passive elements. The operating point is stabilized, and as a result, the stability of the circuit is improved.
Except for this point, the basic operation of the circuit is the same as that of the first configuration example described above, and a detailed description thereof will be omitted here.

Next, a fourth configuration example will be described with reference to FIG.
The same constituent elements as those shown in any of FIGS. 1 to 3 are denoted by the same reference numerals, detailed description thereof is omitted, and different points are mainly described below. To do.
In this fourth configuration example, the first and second diodes 5 and 6 in the third configuration example shown in FIG. 3 are applied to the second configuration example shown in FIG. FIG. 4 shows a specific circuit configuration example of the bias circuit 51 and the current mirror circuit 52.
The first and second resistors 31 and 32 and the first and second diodes 5 and 6 are as described in the configuration example shown in FIG. 2 and FIG. Is omitted.

The bias circuit 51 in this configuration example includes first and second enhancement type PMOS transistors (indicated as “MP1” and “MP2” in FIG. 4, respectively), and hereinafter referred to as “first enhancement PMOS”, “ (Referred to as “second enhancement PMOS”) 21 and 22 as main components.
That is, the sources of the first enhancement PMOS 21 and the second enhancement PMOS 22 are both connected to the bias circuit power supply terminal 51c, while the drain of the first enhancement PMOS 21 is connected to the first bias output terminal 51a. The drain of the enhancement PMOS 22 is connected to the second bias output terminal 51b.
The gates of the first enhancement PMOS 21 and the second enhancement PMOS 22 are connected to each other, and a constant voltage source 8 that outputs a constant voltage Vbias is connected between the connection point and the bias circuit power supply terminal 51c. It is connected.

On the other hand, the current mirror circuit 52 includes second and third enhancement type NMOS transistors (referred to as “MN2” and “MN3” in FIG. 4 respectively), and hereinafter referred to as “second enhancement NMOS”, “second enhancement type”, respectively. 3) (referred to as "3 enhancement NMOS").
That is, the gates of the second and third enhancement NMOSs 12 and 13 are connected to each other and to the drain of the second enhancement NMOS 12, while the sources are both connected to the ground. The drain of the second enhancement NMOS 12 is connected to the input terminal 52a, and the drain of the third enhancement NMOS 13 is connected to the output terminal 52b.
Then, in order to make the drain current of the second enhancement NMOS 12 and the drain current of the third enhancement NMOS 13 equal, both the transistor sizes may be made the same.

In such a configuration, the drain-source voltage of the first depletion NMOS 1 is equal to the gate-source voltage VGS (MN2) of the second enhancement NMOS 12, which is a so-called diode connection, and therefore the change of the power supply voltage VDD. It becomes difficult to be affected by. In addition to the circuit configuration described above, the current mirror circuit 52 includes a configuration referred to as Wilson or cascode. Of course, a circuit configuration using these may be used.
The bias circuit 51 is also suitable as a cascode-type circuit configuration in addition to the circuit configuration described above.
The basic circuit operation in the fourth configuration example is as described with reference to FIGS. 1 to 3, and therefore detailed description thereof is omitted here.

Next, a fifth configuration example will be described with reference to FIG.
The same constituent elements as those shown in any of FIGS. 1 to 4 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below. To do.
The fifth configuration example is based on the circuit configuration shown in FIG. 4 and further shows a specific circuit configuration example of the operational amplifier 53. In FIG. 5, the first and second bias output terminals 51a and 51b of the bias circuit 51, the power supply terminal 51c for the bias circuit, the input / output terminals 52a and 52b of the current mirror circuit 52, and the current are shown for simplicity of illustration. The mirror circuit power supply terminal 52c is omitted.

  Specifically, first, in the fifth configuration example, two enhancement type NMOS transistors (hereinafter referred to as “NMOS transistors”) 5A and 5B connected in a diode form are used in the configuration example of FIG. The first and second diodes 5 and 6 shown in FIG. That is, the drains and gates of the NMOS transistors 5A and 5B as active elements are connected to each other, the drain of the NMOS transistor 5A is the drain of the first depletion NMOS1, and the drain of the NMOS transistor 5B is the first enhancement. The NMOS 11 is connected to the drain thereof, while the respective sources are connected to the ground.

The constant voltage source 8 is composed of an eighth enhancement type PMOS transistor (referred to as “MP8” in FIG. 5 and hereinafter referred to as “eighth enhancement PMOS”) 28 and a constant current source 9. It has become.
That is, the power supply voltage VDD is applied to the source of the eighth enhancement PMOS 28, while the gate and drain are connected, and the constant current source 9 that outputs the bias current Ibias1 is connected to the drain. The gate is connected to the gates of the first and second enhancement PMOSs 21 and 22.

The operational amplifier 53 includes third and fourth enhancement type PMOS transistors constituting the input stage (referred to as “MP3” and “MP4” in FIG. 5 respectively) and hereinafter referred to as “third enhancement PMOS”, “ (Referred to as “fourth enhancement PMOS”) 23, 24, and seventh and ninth enhancement type NMOS transistors constituting the output stage (in FIG. 5, “MN7” and “MN9”, respectively, (Referred to as “seventh enhancement type NMOS”, “9th enhancement type NMOS”) 17, 19 and the like.
Since the circuit configuration of the operational amplifier 53 shown in FIG. 5 is already known and well known, the circuit configuration will be schematically described below centering on the input stage and the output stage.

  The input stage of the operational amplifier 53 is a differential amplifier circuit configured around the third and fourth enhancement PMOSs 23 and 24, and the gate of the third enhancement PMOS 23 is the first inverting input terminal as the first inverting input terminal. The drain of the depletion NMOS 1 and the gate of the fourth enhancement PMOS 24 are connected to the drain of the first enhancement NMOS 11 as a non-inverting input terminal.

On the other hand, the output stage of the operational amplifier 53 is provided with an output circuit having a totem pole configuration composed of the seventh and ninth enhancement NMOSs 17 and 19, and the seventh enhancement NMOS 17 and the ninth enhancement NMOS 19 are provided. The mutual connection point is the output terminal of the operational amplifier 53.
The operational amplifier 53 is supplied with a bias current from the eighth enhancement PMOS 28.

Although not described individually, the transistors denoted as “MN4”, “NM5”, “MN6”, and “MN8” in FIG. 5 are enhancement type NMOS transistors, and are referred to as “MP5”, “ The transistors labeled “MP6” and “MP7” are both enhancement type PMOS transistors.
The circuit operation of the fifth configuration example is the same as that already described with reference to FIGS. 1 to 4, and therefore detailed description thereof is omitted here.

  The circuit configuration example of the operational amplifier 53 described above is merely an example, and of course, the circuit configuration is not limited to this circuit configuration, and other known circuit configurations may be used.

It is a block diagram which shows the 1st structural example of the reference voltage circuit in embodiment of this invention. It is a block diagram which shows the 2nd structural example of the reference voltage circuit in embodiment of this invention. It is a block diagram which shows the 3rd structural example of the reference voltage circuit in embodiment of this invention. It is a block diagram which shows the 4th structural example of the reference voltage circuit in embodiment of this invention. It is a block diagram which shows the 5th structural example of the reference voltage circuit in embodiment of this invention. It is a block diagram which shows one structural example of a conventional circuit. It is a block diagram which shows the other structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st depletion type NMOS transistor 11 ... 1st enhancement type NMOS transistor 51 ... Bias circuit 52 ... Current mirror circuit 53 ... Operational amplifier

Claims (5)

A depletion type NMOS transistor provided to act as a reference current source and an enhancement type NMOS transistor provided so that the current of the depletion type NMOS transistor is supplied through a current mirror circuit are equalized by a bias circuit. A reference voltage generation circuit configured to output a difference between both drain voltages as a reference voltage.
The depletion type NMOS transistor has a gate, a source, and a back gate connected to a first power supply, and a drain that is one of a first bias output terminal of the bias circuit, an input terminal of the current mirror circuit, and an operational amplifier. Connected to the input terminals of
The enhancement type NMOS transistor has a source and a back gate connected to a first power supply, a gate connected to an output terminal of the operational amplifier, a drain connected to a second bias output terminal of the bias circuit, and the current A reference voltage generation circuit connected to an output terminal of a mirror circuit and the other input terminal of the operational amplifier, respectively, and capable of outputting a reference voltage to the output terminal of the operational amplifier.   Two resistors are connected in series between an output terminal of the operational amplifier and a first power supply, and a connection point between the two resistors is connected to a gate of an enhancement type NMOS transistor. The reference voltage generating circuit according to claim 1.   3. The reference according to claim 1, wherein a passive element or an active element is connected between at least one drain of the depletion type NMOS transistor and the enhancement type NMOS transistor and the first power supply. Voltage generation circuit. The current mirror circuit includes second and third enhancement type NMOS transistors. The second and third enhancement type NMOS transistors have gates connected to each other, and sources are both connected to a first power source. Connected to
The drain and gate of the second enhancement type NMOS transistor are connected to each other, and the connection point is an input terminal.
4. The reference voltage generating circuit according to claim 1, wherein the drain of the third enhancement type NMOS transistor is an output terminal.   The bias circuit includes first and second enhancement type PMOS transistors. The first and second enhancement type PMOS transistors have gates connected to each other and a bias voltage applied thereto. A second power supply voltage is applied to each of the sources, the drain of the first enhancement type PMOS transistor serves as a first bias output terminal, and the drain of the second enhancement type PMOS transistor serves as a second bias output. 5. The reference voltage generating circuit according to claim 1, wherein the reference voltage generating circuit is a terminal.

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