JP4859389B2 - Differential amplifier circuit - Google Patents
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本発明は、常にマッチングしたバイアス電流で動作するようにして同相入力電圧範囲を広くした差動増幅回路に関するものである。 The present invention relates to a differential amplifier circuit in which a common-mode input voltage range is widened by always operating with a matched bias current.
図３に従来の差動増幅回路の基本的な回路構成を示す。差動増幅回路本体部分は、差動接続されたＰＭＯＳトランジスタＭＰ２１，ＭＰ２２、そのトランジスタＭＰ２１，ＭＰ２２のソースに共通接続されたＰＭＯＳトランジスタＭＰ２３、トランジスタＭＰ２１のドレインにドレインが接続されたＮＭＯＳトランジスタＭＮ２１、およびトランジスタＭＰ２２のドレインにドレインが接続されたＮＭＯＳトランジスタＭＮ２２からなる。 FIG. 3 shows a basic circuit configuration of a conventional differential amplifier circuit. The differential amplifier circuit main body includes differentially connected PMOS transistors MP21 and MP22, a PMOS transistor MP23 commonly connected to the sources of the transistors MP21 and MP22, an NMOS transistor MN21 having a drain connected to the drain of the transistor MP21, and It comprises an NMOS transistor MN22 having a drain connected to the drain of the transistor MP22.
ＰＭＯＳトランジスタＭＰ２４はＰＭＯＳトランジスタＭＰ２３，ＭＰ２５と第１のカレントミラー回路を構成するトランジスタであり、基準電源回路２１から供給される電流を基準電流としている。
The PMOS transistor MP24 is a transistor that forms a first current mirror circuit with the PMOS transistors MP23 and MP25, and uses a current supplied from the reference
ＮＭＯＳトランジスタＭＮ２３はＮＭＯＳトランジスタＭＮ２１，ＭＮ２２と第２のカレントミラー回路構成するトランジスタであり、前記トランジスタＭＰ２５から供給される電流を基準電流としている。 The NMOS transistor MN23 constitutes a second current mirror circuit with the NMOS transistors MN21 and MN22, and the current supplied from the transistor MP25 is used as a reference current.
この差動増幅回路では、トランジスタＭＮ２１，ＭＮ２２，ＭＰ２３，ＭＰ２５の電流をそれぞれＩ２１，Ｉ２２，Ｉ２３，Ｉ２５とすると、
Ｉ２３＝２×Ｉ２５、Ｉ２１＝Ｉ２２＝Ｉ２５
となるように、トランジスタＭＮ２１，ＭＮ２２，ＭＰ２３，ＭＰ２５のＷ／Ｌ（ゲート幅／ゲート長）を設定することにより、
Ｉ２１：Ｉ２２：Ｉ２３＝１：１：２
の関係が得られるようにしている。
In this differential amplifier circuit, if the currents of the transistors MN21, MN22, MP23, and MP25 are I21, I22, I23, and I25, respectively,
I23 = 2 × I25, I21 = I22 = I25
By setting the W / L (gate width / gate length) of the transistors MN21, MN22, MP23, and MP25 so that
I21: I22: I23 = 1: 1: 2
The relationship is obtained.
ところが、上記した回路構成では、入力端子ＩＮ１，ＩＮ２に印加する入力電圧Ｖin(+)、Vin(-)が同相で変動するとき、ノードＮ２１の電圧が変動し、ノードＮ２２の固定の電圧との関係が変動する。このため、Ｉ２３＝２×Ｉ２５の関係が崩れてしまい、Ｉ２５＝Ｉ２１＝Ｉ２２の関係も崩れ、Ｉ２１：Ｉ２２：Ｉ２３＝１：１：２の関係が崩れてしまう。 However, in the circuit configuration described above, when the input voltages Vin (+) and Vin (−) applied to the input terminals IN1 and IN2 fluctuate in the same phase, the voltage at the node N21 fluctuates, and the fixed voltage at the node N22 Relationships fluctuate. For this reason, the relationship of I23 = 2 × I25 is broken, the relationship of I25 = I21 = I22 is also broken, and the relationship of I21: I22: I23 = 1: 1: 2 is broken.
この結果、図４の差電流−同相入力電圧特性に破線で示すように、入力端子ＩＮ１，ＩＮ２に同相の電圧を入力してこれを増大させた（同相入力電圧増大）とき、Ｉ２３−２×Ｉ２５＝ΔＩとし、Ｉ２３＝Ｉrefとすると、ΔI／Irefの値が低下する。また、図５のオフセット電圧−同相入力電圧特性に破線で示すように、同相入力電圧が増大したとき、オフセット電圧Ｖos（＝Ｖout(+)−Vout(-)）も大きくなる。これらは、同相入力電圧を電源電圧ＶＤＤに近づけるほどより顕著となる。以上の結果、同相入力電圧範囲が非常に狭くなるという問題が起こる。なお、図４および図５のＶ(sat)は差動回路の共通電流源トランジスタ（図３ではＭＰ２３）の飽和電圧である。 As a result, as shown by the broken line in the differential current-common-mode input voltage characteristic of FIG. 4, when a common-mode voltage is input to the input terminals IN1 and IN2 and is increased (increase in common-mode input voltage), I23-2 × When I25 = ΔI and I23 = Iref, the value of ΔI / Iref decreases. Further, as indicated by a broken line in the offset voltage-common-mode input voltage characteristic of FIG. 5, when the common-mode input voltage increases, the offset voltage Vos (= Vout (+) − Vout (−)) also increases. These become more prominent as the common-mode input voltage approaches the power supply voltage VDD. As a result, the common mode input voltage range becomes very narrow. 4 and 5 is the saturation voltage of the common current source transistor (MP23 in FIG. 3) of the differential circuit.
本発明の目的は、同相入力電圧が大きく変動しても上記したような問題が発生しないようにした差動増幅回路を提供することである。 An object of the present invention is to provide a differential amplifier circuit in which the above-described problem does not occur even when the common-mode input voltage varies greatly.
上記課題を解決するために、本発明の差動増幅回路は、ゲートがそれぞれ第１および第２の入力端子に接続される差動接続ＭＯＳトランジスタの共通ソースに第１の電流源を接続し、該差動接続ＭＯＳトランジスタの各々のドレインにそれぞれ第２および第３の電流源を接続し、前記差動接続ＭＯＳトランジスタの各々のドレインにそれぞれ第１および第２の出力端子を接続し、前記第２および第３の電流源の電流が前記第１の電流源の電流の１／２に設定されるべき差動増幅回路において、前記差動接続ＭＯＳトランジスタと同一極性の補償用ＭＯＳトランジスタを設け、該補償用トランジスタのゲートを前記第１又は第２の入力端子に接続し、ソースを前記第１の電流源の１／２の電流の第４の電流源に接続し、ドレインを前記第２および第３の電流源を出力側にもつカレントミラー回路の基準側に接続したことを特徴とする。 In order to solve the above-described problem, a differential amplifier circuit according to the present invention has a first current source connected to a common source of differentially connected MOS transistors whose gates are connected to first and second input terminals, respectively. Second and third current sources are connected to the drains of the differential connection MOS transistors, respectively, and first and second output terminals are connected to the drains of the differential connection MOS transistors, respectively. In the differential amplifier circuit in which the current of the second and third current sources is to be set to ½ of the current of the first current source, a compensation MOS transistor having the same polarity as the differential connection MOS transistor is provided, A gate of the compensation transistor is connected to the first or second input terminal, a source is connected to a fourth current source having a half current of the first current source, and a drain is connected to the second input terminal. Yo Characterized by being connected to the reference side of the current mirror circuit having a third current source to the output side.
ここで、前記補償用ＭＯＳトランジスタは、前記差動接続ＭＯＳトランジスタと同一特性であることが望ましい。 Here, it is desirable that the compensation MOS transistor has the same characteristics as the differential connection MOS transistor.
また、本発明の差動増幅回路は、ゲートが第１および第２の入力端子にそれぞれ接続されソースが共通接続されドレインが第１および第２の出力端子にそれぞれ接続された第１および第２のＭＯＳトランジスタと、該第１および第２のＭＯＳトランジスタのソースに出力側の第３のＭＯＳトランジスタが接続された第１のカレントミラー回路と、該第１のカレントミラー回路の出力側の第４のＭＯＳトランジスタの電流が基準側の第５のＭＯＳトランジスタに供給され前記第１および第２のＭＯＳトランジスタのドレインにそれぞれ出力側の第６および第７のＭＯＳトランジスタが接続された第２のカレントミラー回路とを具備し、前記第４，第６および第７のＭＯＳトランジスタの電流が同一で且つ前記第３のＭＯＳトランジスタの電流の１／２になるように設定されるべき差動増幅回路において、前記第１および第２のＭＯＳトランジスタと同一極性の補償用ＭＯＳトランジスタを設け、該補償用ＭＯＳトランジスタのゲートを前記第１又は第２の入力端子に接続し、ソースを前記第４のＭＯＳトランジスタのドレインに接続し、ドレインを前記第５のトランジスタのドレインに接続したことを特徴とするよう構成することが望ましい。 In the differential amplifier circuit of the present invention, the first and second gates are connected to the first and second input terminals, the sources are commonly connected, and the drains are connected to the first and second output terminals, respectively. A first current mirror circuit in which the output third MOS transistor is connected to the sources of the first and second MOS transistors, and a fourth current mirror circuit on the output side of the first current mirror circuit. Current of the first MOS transistor is supplied to the fifth MOS transistor on the reference side, and the sixth and seventh MOS transistors on the output side are connected to the drains of the first and second MOS transistors, respectively. A circuit, wherein the currents of the fourth, sixth and seventh MOS transistors are the same and the current of the third MOS transistor In the differential amplifier circuit to be set to / 2, a compensation MOS transistor having the same polarity as the first and second MOS transistors is provided, and the gate of the compensation MOS transistor is connected to the first or second MOS transistor. It is desirable that the source terminal is connected to the drain of the fourth MOS transistor, and the drain is connected to the drain of the fifth transistor.
また、前記補償用ＭＯＳトランジスタは、前記第１および第２のＭＯＳトランジスタと同一特性であることが望ましい。 The compensation MOS transistor preferably has the same characteristics as the first and second MOS transistors.
さらに、前記各ＭＯＳトランジスタをバイポーラトランジスタに置き換え、前記ゲートをベースに置き換え、ソースをエミッタに置き換え、ドレインをコレクタに置き換えることもできる。 Further, each MOS transistor can be replaced with a bipolar transistor, the gate can be replaced with a base, the source can be replaced with an emitter, and the drain can be replaced with a collector.
本発明の差動増幅回路によれば、同相入力電圧の変動によって差動接続トランジスタの共通ソース又はエミッタの電位が変動するとき、補償用トランジスタのソース又はエミッタの電位も同様に同じ方向に変動するので、第１の電流源と第４の電流源の電流の比率関係２：１を保持することが可能となるため、第２および第３の電流源の電流を常時第１の電流源の電流の１／２に保持させることが可能となり、同相入力電圧範囲を広くすることが可能となる。 According to the differential amplifier circuit of the present invention, when the potential of the common source or emitter of the differential connection transistor varies due to the variation of the common-mode input voltage, the potential of the source or emitter of the compensation transistor also varies in the same direction. Therefore, since it becomes possible to maintain the current ratio of 2: 1 between the first current source and the fourth current source, the currents of the second and third current sources are always used as the currents of the first current source. Therefore, the common-mode input voltage range can be widened.
図１に本発明の実施例の差動増幅回路の回路構成を示す。差動増幅回路本体部分は、差動接続されたＰＭＯＳトランジスタＭＰ１，ＭＰ２、そのトランジスタＭＰ１，ＭＰ２のソースに共通接続されたＰＭＯＳトランジスタＭＰ３、トランジスタＭＰ１のドレインにドレインが接続されたＮＭＯＳトランジスタＭＮ１、およびトランジスタＭＰ２のドレインにドレインが接続されたＮＭＯＳトランジスタＭＮ２からなる。ここで、トランジスタＭＰ１，ＭＰ２が差動接続ＭＯＳトランジスタを、トランジスタＭＰ３が第１の電流源を、トランジスタＭＮ１，ＭＮ２が第２および第３の電流源を構成する。 FIG. 1 shows a circuit configuration of a differential amplifier circuit according to an embodiment of the present invention. The differential amplifier circuit main body includes differentially connected PMOS transistors MP1 and MP2, a PMOS transistor MP3 commonly connected to the sources of the transistors MP1 and MP2, an NMOS transistor MN1 having a drain connected to the drain of the transistor MP1, and It comprises an NMOS transistor MN2 whose drain is connected to the drain of the transistor MP2. Here, the transistors MP1 and MP2 constitute a differential connection MOS transistor, the transistor MP3 constitutes a first current source, and the transistors MN1 and MN2 constitute second and third current sources.
ＰＭＯＳトランジスタＭＰ４はＰＭＯＳトランジスタＭＰ３，ＭＰ５と第１のカレントミラー回路構成するトランジスタであり、基準電源回路１から供給される電流を基準電流としている。ＮＭＯＳトランジスタＭＮ３はＮＭＯＳトランジスタＭＮ１，ＭＮ２と第２のカレントミラー回路を構成するトランジスタである。ここで、トランジスタＭＰ４が第５の電流源を構成する。
The PMOS transistor MP4 is a transistor constituting a first current mirror circuit with the PMOS transistors MP3 and MP5, and uses a current supplied from the reference
ドレインとソースが共通接続されたＰＭＯＳトランジスタＭＰ６，ＭＰ７は、トランジスタＭＰ５のドレインとトランジスタＭＮ３のドレインの間に接続され、かつゲートが入力端子ＩＮ１，ＩＮ２に接続されている。このトランジスタＭＰ６，ＭＰ７はトランジスタＭＰ１，ＭＰ２と同じ特性である。ここで、トランジスタＭＰ６，ＭＰ７が補償用ＭＯＳトランジスタを構成する。 The PMOS transistors MP6 and MP7 whose drain and source are commonly connected are connected between the drain of the transistor MP5 and the drain of the transistor MN3, and the gates are connected to the input terminals IN1 and IN2. The transistors MP6 and MP7 have the same characteristics as the transistors MP1 and MP2. Here, the transistors MP6 and MP7 constitute a compensation MOS transistor.
この差動増幅回路では、トランジスタＭＮ１，ＭＮ２，ＭＰ３，ＭＰ５の電流をそれぞれＩ１，Ｉ２，Ｉ３，Ｉ５とするとき、
Ｉ３＝２×Ｉ５、Ｉ１＝Ｉ２＝Ｉ５
となるように、トランジスタＭＮ１，ＭＮ２，ＭＰ３，ＭＰ５のＷ／Ｌ（ゲート幅／ゲート長）を設定することにより、
Ｉ１：Ｉ２：Ｉ３＝１：１：２
の関係が得られるようにする。
In this differential amplifier circuit, when the currents of the transistors MN1, MN2, MP3, and MP5 are I1, I2, I3, and I5, respectively,
I3 = 2 × I5, I1 = I2 = I5
By setting W / L (gate width / gate length) of transistors MN1, MN2, MP3, and MP5 so that
I1: I2: I3 = 1: 1: 2
So that the relationship can be obtained.
この差動増幅回路では、平衡時（同相入力時）において、トランジスタＭＰ６，ＭＰ７はトランジスタＭＰ１，ＭＰ２と同一動作点で動作する。よって、入力電圧Ｖin(+)、Ｖin(-)が同相で変動するとき、ノードＮ１とＮ２の電位は同じように変動する。これにより、Ｉ３＝２×Ｉ５の関係が保持され、Ｉ５＝Ｉ１＝Ｉ２の関係も保持される。このため、Ｉ１：Ｉ２：Ｉ３＝１：１：２の関係が保持され、同相入力電圧範囲を高い電圧まで実現することが可能となる。 In this differential amplifier circuit, the transistors MP6 and MP7 operate at the same operating point as the transistors MP1 and MP2 during equilibrium (in-phase input). Therefore, when the input voltages Vin (+) and Vin (−) fluctuate in phase, the potentials of the nodes N1 and N2 fluctuate in the same way. Thereby, the relationship of I3 = 2 × I5 is maintained, and the relationship of I5 = I1 = I2 is also maintained. Therefore, the relationship of I1: I2: I3 = 1: 1: 2 is maintained, and the common-mode input voltage range can be realized up to a high voltage.
図４の差電流−同相入力電圧特性に本実施例の差動増幅回路の特性を実線で示す。破線で示す図３の従来回路の特性に比べて、差電流ΔＩ（Ｉ３−２×Ｉ５）は同相入力電圧が電源電圧ＶＤＤに近づいても、その増大が抑圧されている。Ｉ３＝Ｉrefである。また、図５のオフセット電圧−同相入力電圧特性に本実施例の差動増幅回路の特性を実線で示す。破線で示す図３の従来回路の特性に比べて、同様にオフセット電圧Ｖosの増大が抑圧されている。以上のように、本実施例の差動増幅回路によれば、広い同相入力電圧の範囲に亘って差電流ΔＩおよびオフセット電圧Ｖosともに良好な特性を示し、同相入力電圧範囲が拡大することがわかる。 The characteristic of the differential amplifier circuit of the present embodiment is shown by a solid line in the difference current-in-phase input voltage characteristic of FIG. Compared to the characteristic of the conventional circuit of FIG. 3 indicated by a broken line, the difference current ΔI (I3-2 × I5) is suppressed from increasing even when the common-mode input voltage approaches the power supply voltage VDD. I3 = Iref. Further, the characteristic of the differential amplifier circuit of the present embodiment is shown by a solid line in the offset voltage-common-mode input voltage characteristic of FIG. Compared to the characteristic of the conventional circuit of FIG. 3 indicated by the broken line, the increase of the offset voltage Vos is similarly suppressed. As described above, according to the differential amplifier circuit of the present embodiment, both the differential current ΔI and the offset voltage Vos exhibit good characteristics over a wide range of the common-mode input voltage, and the common-mode input voltage range is expanded. .
図２は図１の差動増幅回路の変形例を示す回路図であり、図１の回路のＰＭＯＳトランジスタとＮＭＯＳトランジスタを入れ替えたものである。この場合は、差動接続回路にＮＭＯＳトランジスタを使用しているので、同相入力電圧が低くなる領域で前記と同様な同相入力電圧範囲拡大の効果を得ることができる。 FIG. 2 is a circuit diagram showing a modification of the differential amplifier circuit of FIG. 1, in which the PMOS transistor and NMOS transistor of the circuit of FIG. 1 are replaced. In this case, since the NMOS transistor is used in the differential connection circuit, the same effect of expanding the common-mode input voltage range as described above can be obtained in a region where the common-mode input voltage is low.
なお、以上の説明では、補償用トランジスタとして、回路バランスを考慮して、図１では並列接続のＰＭＯＳトランジスタＭＰ６，ＭＰ７を使用し、図２では並列接続のＮＭＯＳトランジスタＭＮ１６，ＭＮ１７を使用したが、これらは１個のＰＭＯＳあるいはＮＭＯＳのトランジスタとし、そのゲートは入力端子ＩＮ１又はＩＮ２に接続してもよい。 In the above description, in consideration of circuit balance, PMOS transistors MP6 and MP7 connected in parallel are used in FIG. 1 and NMOS transistors MN16 and MN17 connected in parallel are used in FIG. These may be one PMOS or NMOS transistor, and the gate thereof may be connected to the input terminal IN1 or IN2.
また、以上説明した実施例ではＭＯＳトランジスタを使用したが、バイポーラトランジスタを使用しても同様の作用効果を得ることができる。この場合、ゲートがベースに、ソースがエミッタに、ドレインがコレクタに置き換わる。 In the embodiment described above, a MOS transistor is used, but the same effect can be obtained even if a bipolar transistor is used. In this case, the gate replaces the base, the source replaces the emitter, and the drain replaces the collector.
ＭＰ１〜ＭＰ７，ＭＰ１１〜ＭＰ１３，ＭＰ２１〜ＭＰ２５：ＰＭＯＳトランジスタ
ＭＮ１〜ＭＮ３，ＭＮ１１〜ＭＮ１７，ＭＮ２１〜ＭＮ２３：ＮＭＯＳトランジスタ
１，１１，２１：基準電源回路
MP1 to MP7, MP11 to MP13, MP21 to MP25: PMOS transistors MN1 to MN3, MN11 to MN17, MN21 to MN23:
Claims (5)
前記差動接続ＭＯＳトランジスタと同一極性の補償用ＭＯＳトランジスタを設け、該補償用トランジスタのゲートを前記第１又は第２の入力端子に接続し、ソースを前記第１の電流源の１／２の電流の第４の電流源に接続し、ドレインを前記第２および第３の電流源を出力側にもつカレントミラー回路の基準側に接続したことを特徴とする差動増幅回路。 The first current source is connected to the common source of the differential connection MOS transistors whose gates are connected to the first and second input terminals, respectively, and the second and third are respectively connected to the drains of the differential connection MOS transistors. Are connected to the respective drains of the differentially connected MOS transistors, and the currents of the second and third current sources are connected to the drains of the differentially connected MOS transistors, respectively. In the differential amplifier circuit to be set to 1/2 of the current,
A compensation MOS transistor having the same polarity as that of the differential connection MOS transistor is provided, a gate of the compensation transistor is connected to the first or second input terminal, and a source is ½ of the first current source. A differential amplifier circuit, characterized in that a fourth current source of current is connected and a drain is connected to a reference side of a current mirror circuit having the second and third current sources on the output side.
前記補償用ＭＯＳトランジスタは、前記差動接続ＭＯＳトランジスタと同一特性であることを特徴とする差動増幅回路。 The differential amplifier circuit according to claim 1,
The differential MOS circuit according to claim 1, wherein the compensation MOS transistor has the same characteristics as the differential connection MOS transistor.
前記第１および第２のＭＯＳトランジスタと同一極性の補償用ＭＯＳトランジスタを設け、該補償用ＭＯＳトランジスタのゲートを前記第１又は第２の入力端子に接続し、ソースを前記第４のＭＯＳトランジスタのドレインに接続し、ドレインを前記第５のトランジスタのドレインに接続したことを特徴とする差動増幅回路。 First and second MOS transistors, each having a gate connected to the first and second input terminals, a source connected in common, and a drain connected to the first and second output terminals, respectively; A first current mirror circuit in which a third MOS transistor on the output side is connected to the source of the first MOS transistor, and a current in the fourth MOS transistor on the output side of the first current mirror circuit is the fifth current on the reference side. And a second current mirror circuit connected to the drains of the first and second MOS transistors and the sixth and seventh MOS transistors on the output side, respectively. The currents of the sixth and seventh MOS transistors should be the same and should be set to be 1/2 of the current of the third MOS transistor. In the differential amplifier circuit,
A compensation MOS transistor having the same polarity as that of the first and second MOS transistors is provided, a gate of the compensation MOS transistor is connected to the first or second input terminal, and a source is connected to the fourth MOS transistor. A differential amplifier circuit comprising: a drain connected to the drain; and the drain connected to the drain of the fifth transistor.
前記補償用ＭＯＳトランジスタは、前記第１および第２のＭＯＳトランジスタと同一特性であることを特徴とする差動増幅回路。 The differential amplifier circuit according to claim 3,
The differential MOS circuit according to claim 1, wherein the compensation MOS transistor has the same characteristics as the first and second MOS transistors.
前記各ＭＯＳトランジスタをバイポーラトランジスタに置き換え、前記ゲートをベースに置き換え、ソースをエミッタに置き換え、ドレインをコレクタに置き換えたことを特徴とする差動増幅回路。 The differential amplifier circuit according to claim 1, 2, 3, or 4,
A differential amplifier circuit, wherein each MOS transistor is replaced with a bipolar transistor, the gate is replaced with a base, the source is replaced with an emitter, and the drain is replaced with a collector.
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| JP2005136294A JP4859389B2 (en) | 2005-05-09 | 2005-05-09 | Differential amplifier circuit |
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| JP2005136294A JP4859389B2 (en) | 2005-05-09 | 2005-05-09 | Differential amplifier circuit |
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| JP4859389B2 true JP4859389B2 (en) | 2012-01-25 |
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| JP5406113B2 (en) * | 2010-05-07 | 2014-02-05 | セイコーインスツル株式会社 | Differential amplifier circuit |
| JP7388892B2 (en) * | 2019-11-21 | 2023-11-29 | 日清紡マイクロデバイス株式会社 | operational amplifier |
| JP7468889B2 (en) * | 2020-03-31 | 2024-04-16 | ザインエレクトロニクス株式会社 | Fully Differential Amplifier |
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| JPS5851606A (en) * | 1981-09-22 | 1983-03-26 | Nec Corp | Bias circuit for differential amplifier |
| US4887048A (en) * | 1988-01-21 | 1989-12-12 | Texas Instruments Incorporated | Differential amplifier having extended common mode input voltage range |
| JPH05252020A (en) * | 1992-03-06 | 1993-09-28 | Fujitsu Ltd | Cmos drive circuit |
| JPH06310951A (en) * | 1993-04-21 | 1994-11-04 | Olympus Optical Co Ltd | Differential amplifier circuit |
| JPH07106875A (en) * | 1993-09-30 | 1995-04-21 | Nec Corp | Semiconductor integrated circuit |
| JP2001185964A (en) * | 1999-12-22 | 2001-07-06 | Hitachi Ltd | Current mirror circuit and operational amplifier |
| JP4099079B2 (en) * | 2003-02-12 | 2008-06-11 | 日本電信電話株式会社 | Bias generation circuit |
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