JPH06120832A - D/a converter - Google Patents

Abstract

PURPOSE:To decrease the number of resistances and switches, to reduce the chip area, and also to improve the accuracy of the D/A conversion on a D/A converter of a resistance string system. CONSTITUTION:A 1st D/A conversion part 5 converts more significant M bits, and a 2nd D/A conversion part 6 converts less significant N bits respectively. The part 5 consists of 2M pieces of resistances and switches S1-S19, and the part 6 consists of the resistances R/4 obtained by dividing a unit resistance R of the part 5 into 2N pieces and 2N pieces of switches S20-S23 connected to the taps respectively. The output of the part 5 is charged and held by a capacity element 7 via a switch 12. Then the output result of the part 6 is superposed on the output of the part 5 held by the element 7 and outputted from a buffer amplifier 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog converter, and more particularly to a resistor string type digital-analog converter (hereinafter referred to as a D / A converter).

[0002]

2. Description of the Related Art Conventionally, a resistor string type D / A converter has been widely known as a D / A converter suitable for monolithization. The characteristic of this type of D / A converter is that it has a simple structure and that it is easy to secure monotonic increase.

FIG. 4 is a block diagram of a D / A converter showing such a conventional example. As shown in FIG. 4, the D / A converter, D ₀ and ~D digital input terminal 1 of the _N-1, decoding based data from the input terminals 1 to the latch signal of the data latch signal terminal 2 Dekoto Circuit 3 and 2 ^N
A D / A converter 5a having a tree-shaped switch that operates according to the number of unit resistors and the output of the decoding circuit 3, and a buffer amplifier 8 that receives the output of the D / A converter 5a.
Have and. These 2 ^N unit resistors (R) are connected in series between the high-level reference voltage (V _REF ) terminal 9 and the low-level voltage (GND) terminal 10, and the output of the buffer amplifier 8 is fed back to the inverting input terminal. It

If the D / A converter has 8 bits,
2 ⁸ = 256 unit resistors are connected in series, and it is configured by 510 switches that select the voltage of each tap.

FIG. 5 is a block diagram of another conventional D / A converter. As shown in FIG. 5, this D / A converter has a digital input terminal 1 and a decoding circuit 3 as in the above-described example, and the configuration of the D / A converter 5b is changed. According to this, the number of switches can be reduced to about half. That is, the resistor strings in which unit resistors (R) are connected in series and the switches for selecting the voltage of each tap are arranged in a matrix. A switch selection signal is generated from the data code circuit 3 in response to a digital input signal from the input terminal 1, and a desired tap is selected.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Although the A converter can reduce the number of switches, it has a drawback that the number of unit resistors cannot be reduced. That is, the conventional D / A converter has an N-bit D / A
When performing A conversion, 2 ^N unit resistors are required and a switch for selecting the same number of taps is required. This results in a significant increase in chip area as the number of bits increases, making it difficult to improve conversion accuracy.

An object of the present invention is to reduce the number of such unit resistances and switches to reduce the chip area and to realize a highly accurate D / A conversion.
To provide a converter.

[0008]

A D / A converter according to the present invention selects a first resistor string in which unit resistors are connected in series and each tap of the first resistor string to select a first analog output. A first digital-analog converter having a plurality of first switch means for generating a voltage, and a second resistor obtained by further dividing a unit resistor adjacent to the lower power supply terminal of the first resistor string. A plurality of second taps for selecting a column and each tap of the second resistor row to obtain a second analog output voltage.
Second digital-analog converter, a capacitor holding the analog output voltage of the first digital-analog converter, the voltage held in the capacitor, and the second digital -Gain 1 that outputs an analog voltage that superimposes the output voltage of the analog converter
Buffer amplifier, and the upper bit and the lower bit are configured to be converted by the first and second digital-analog converters, respectively.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of a D / A converter showing an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a first resistor string in which unit resistors R are connected in series and each tap of the first resistor string are selected and a first analog output voltage V is selected.
A first D / A converter 5 having a plurality of switches S _{1 to} S ₁₉ as first switch means for generating 01.
And a second resistor string obtained by further dividing the unit resistor R adjacent to the lower power supply terminal of the first resistor string and each tap of the second resistor string, and selecting the second analog output voltage V
And a second D / A conversion unit 6 having a plurality of switches S _{20 to} S ₂₃ as second switch means for obtaining 02. Further, in the present embodiment, in addition to these two D / A converters 5 and 6, a digital input terminal (D _{0 to} D ₅ ) 1 for controlling these two D / A converters 5 and 6, A first decoding circuit 3 and a second decoding circuit 4 that drive each of them separately, a capacitive element 7 that holds the analog output voltage V01 of the first D / A conversion section 5, and a capacitive element 7 that holds the analog output voltage V01. And a buffer amplifier 8 having a gain of 1 which outputs an analog voltage V01 + V02 in which the output voltage of the second D / A converter 6 is superimposed. As a result, the upper bits D _{0 to} D ₃ are converted by the first D / A converter 5, and the lower bits D ₄ and D ₅ are converted by the second D / A converter 6.

In such a 6-bit D / A converter,
First D / A converter 5 for converting upper 4 bits and lower 2
The second D / A conversion unit 6 for converting bits is a high reference voltage (V _REF ) terminal 9 and a low reference voltage (GND) terminal 1.
It is connected in series with 0. In addition, the buffer amplifier 8
The output terminal 11 of becomes the output terminal of the D / A converter, and
-14 are switches.

FIG. 2 is a timing chart of signals and switches for explaining the circuit operation in FIG. As shown in FIG. 2, first, the upper bit digital data (D _{0 to} D ₃ ) input to the digital input terminal 1 is synchronized with the falling edge of the data latch signal (DL inversion) from the data latch signal terminal 2. It is latched by the first decoding circuit 3. The first decoding circuit 3 latches data and, at the same time, sends a switch control signal for controlling the switch S ₁ to the switch S ₁₉ . At this time, the switch S12 and the switch 13 are in the ON state and the switch 14 is in the O state.
Since it is in the FF state, the capacitive element 7 is charged with the output voltage VO1 of the first D / A conversion unit 5. Further, the analog output of the buffer amplifier 8 at this time is set to VO1 as the capacitive element 7 is charged.

On the other hand, lower bit digital data (
_D4 and _D5 are latched by the second decoding circuit 4 in synchronization with the falling _edge of the data latch signal (DL inversion). The second decoding circuit 4 latches the data and at the same time,
A switch control signal is sent so as to turn on any one of the switches S ₂₀ to S ₂₃ . As a result, the analog output voltage VO2 corresponding to the digital input data is output to the output of the second D / A conversion unit 6.

Next, the switches 12 and 13 are turned off in synchronization with the rising edge of the data latch signal (DL inversion).
Then, the switch 14 is turned on. As a result, the output voltage VO1 of the first D / A conversion unit 5 is held in the capacitive element 7, and at the same time, the output voltage VO2 of the second D / A conversion unit 6 is held.
Are connected in series to one electrode of the capacitive element 7. As a result, a voltage of VO1 + VO2 is generated on the other electrode of the capacitive element 7, and this voltage is output to the output terminal 11 via the buffer amplifier 8.

As described above, the analog output voltage VO1 + V corresponding to the digital input data (D _{0 to} D ₅ )
O2 can be output.

Now, this embodiment will be compared with two conventional examples. First, when a 6-bit D / A converter is configured by the circuit of the first conventional example (FIG. 4), 64 unit resistances,
126 switches are required, and the circuit of the second conventional example (FIG. 5) has 64 unit resistors and 7 switches.
You need two. On the other hand, according to the present example, as is apparent from FIG. 1, it is possible to configure the unit resistance with 16 units (of which one unit is divided into 4 units) and the switches with 27 units.

3 (a) and 3 (b) are a circuit diagram and a timing diagram of signals and the like around a buffer amplifier in a D / A converter for explaining another embodiment of the present invention. When configuring a D / A converter with high accuracy, for example, 8 bits or more, the offset voltage of the buffer amplifier 8 affects the accuracy in the embodiment of FIG. For example, the reference voltage (V
_{When REF} ) is 5 V, 1 LSB = 19.5 mV in the 8-bit D / A converter. However, M
The input offset voltage of the differential amplifier manufactured by the OS process is about 10 mV, which cannot be ignored in a D / A converter of 8 bits or more.

Therefore, as shown in FIG. 3A, in this embodiment, the input terminal of the buffer amplifier 8 is provided with the capacitance element 23 for holding the offset voltage. This is to sample the input offset voltage of the buffer amplifier 8 with the capacitor 23 while the output voltage VO1 of the first D / A converter 5 is sampled with the capacitor 7.

Further, as shown in FIG. 3B, the switches 20 and 21 are set to O when sampling to the capacitance element 23.
N, the switch 22 is OFF. Next, switch 22
Is turned on and the switches 20 and 21 are turned off, the capacitance element 23 is connected between the inverting input terminals of the buffer amplifier 8. As a result, the input offset voltage of the buffer amplifier 8 can be canceled. That is, upper bit +
When outputting the conversion result of the lower bit, the voltage of the inverting input terminal of the buffer amplifier 8 can be represented by VO1 + VO2-VI0. Here, VI0 represents the input offset voltage of the buffer amplifier 8. Here, the capacitive element 23
Since VIO is held in the output terminal 11,
A value of VO1 + VO2 + VIO-VIO = VO1 + VO2 is output, and a highly accurate conversion result can be obtained.

[0019]

As described above, the D / A converter of the present invention is provided with two conversion units, and the upper M bits are set to the first D / A.
The A conversion unit converts the lower N bits to the second D /
By converting the A converter, 2 ^M number the number of unit resistors, that the number of switches roughly (2 ^M +2 ^N) can be configured in number, it is possible to reduce the number of unit resistors and switches effective. Since this can greatly reduce the number of resistors and switches as compared with the conventional example, the chip area is also reduced to about 1/2 ^N.

Furthermore, the present invention has the effect that highly accurate D / A conversion can be achieved by compensating for the offset voltage of the Bop-A amplifier.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a D / A converter showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals and switches for explaining the circuit operation in FIG.

FIG. 3 is a diagram showing timings of circuits and signals around a buffer amplifier in a D / A converter for explaining another embodiment of the present invention.

FIG. 4 is a circuit diagram of a D / A converter showing a conventional example.

FIG. 5 is a circuit diagram of a D / A converter showing another conventional example.

[Explanation of symbols]

1 Digital Input Terminal 2 Data Latch Signal Terminal 3, 4 Decoding Circuit 5 First D / A Converter 6 Second D / A Converter 7, 23 Capacitive Element 8 Buffer Amplifier 9 High Reference Voltage Terminal 10 Low Reference Voltage Terminal 11 Output terminals of buffer amplifier 12 to 14, S _{1 to} S ₂₃ switches

Claims (2)

[Claims] 1. A plurality of first switch means for selecting a first resistor string in which unit resistors are connected in series and each tap of the first resistor string to generate a first analog output voltage. A first digital-to-analog converter section, a second resistor string obtained by further dividing a unit resistor adjacent to the lower power supply terminal of the first resistor string, and each tap of the second resistor string are selected. A second digital circuit comprising a plurality of second switch means for obtaining a second analog output voltage
An analog converter, a capacitive element that holds the analog output voltage of the first digital-analog converter, and an analog that superimposes the voltage held by the capacitive element and the output voltage of the second digital-analog converter. A digital-analog converter, comprising: a unity-gain buffer amplifier that outputs a voltage, wherein the high-order bit and the low-order bit are converted by the first and second digital-analog conversion units, respectively. 2. An offset of the buffer amplifier to the other capacitance element during a period in which another capacitance element is connected to the inverting input terminal of the buffer amplifier and the output voltage of the first digital-analog converter is sampled. The digital-to-analog converter according to claim 1, which samples a voltage.