JP3166603B2 - D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D / A converter for converting digital data into an analog voltage, and more particularly, to a D / A converter using a load capacitance circuit.

[0002]

2. Description of the Related Art Conventionally, when a D / A converter is realized by a CMOS circuit, a resistor string is formed by connecting a large number of resistors (for example, 2 ⁿ resistors when input data is n bits). A voltage potentiometer configured to divide a reference voltage using a resistor and extract a divided voltage from a voltage dividing point corresponding to the input data of the resistor string via a switching element to output an analog voltage corresponding to the input data. Type D / A converter is used.

However, this voltage potentiometer type D
In the / A converter, when the input data has a high bit of, for example, 10 bits or more, the D / A conversion accuracy is reduced due to a variation in the resistance value of each resistor, and an analog voltage signal corresponding to the input data is obtained. There was a problem that it could not be.

On the other hand, as an A / D converter suitable for realizing a CMOS circuit, as disclosed in US Pat. No. 4,129,863, an input voltage and a reference voltage for converting an analog input voltage into a digital value are disclosed. In a successive approximation type A / D converter for successively comparing a voltage with a voltage, the reference voltage is generated using a load capacitance circuit (capacitor array) composed of a plurality of capacitors whose capacitance has been binarily loaded. A / D converter has been proposed.

In this proposed A / D converter, a capacitor array is used as a D / A converter for generating an analog voltage from digital data.
When a CMOS circuit is used, a highly accurate characteristic (capacitance) can be obtained as compared with a resistor string. By using this, a D / A that can convert digital data to an analog voltage with high accuracy can be obtained. A converter can be configured.

That is, for example, as shown in FIG.
When converting 4-bit input data to analog voltage,
Assuming that the reference value of the capacitance is c, a capacitor array including four capacitors (capacitors) Ca to Cd whose capacitances are set to c, 2c, 4c, and 8c is used as the capacitor array 52.

When the input data (4 bits) is converted into an analog voltage using the capacitor array 52, a reference voltage Vref is applied to one end of each of the capacitors Ca to Cd. Switching elements Sa to Sd for switching whether to connect the reference voltage line on the positive potential side, connect the GND line on the negative potential side, or apply the bias voltage VB. The other ends are connected to each other as output lines for dividing and outputting the reference voltage Vref. Further, a pair of switching elements Se for connecting both ends of each of the capacitors Ca to Cd and applying a bias voltage VB to each end. , Sf.

When actually converting the input data (4 bits) into an analog voltage using the D / A converter 50 having the above-described configuration, first, the switching elements Se and Sf are turned on and each of the switching elements Se and Sf is turned on. Switching element S
By switching a to Sd to the switching element Se side, a bias voltage is applied to both ends of each of the capacitors Ca to Cd, and electric charges accumulated in each of the capacitors Ca to Cd are discharged (hereinafter, this operation is referred to as a bias operation). . After that, the switching elements Se and Sf are turned off, and the respective switching elements Sa to Sd are connected to the capacitor Ca having the smallest capacitance load, for example, when the least significant bit (LSB) of the input data is “1”. The switching element Sa is switched to the reference voltage line (Vref) side, and the most significant bit (MSB) of the input data is "0".
Then, the switching element Sd connected to the capacitor Cd having the largest capacitance load is switched to the GND line (0 V) side, such as switching to the reference voltage line or the GND line side according to each bit value of the input data. (Hereinafter, this operation is called a settling operation).

As a result, the output line connecting one end of each of the capacitors Ca to Cd is connected to the reference voltage line -G.
The reference voltage between the ND lines is changed from a value 0 to a value 15
A voltage of 0 V to Vref obtained by capacitively dividing the voltage is generated in accordance with the bit input data.
If output is performed via the buffer 54 composed of a or the like, the capacitor array 52 can be used as a D / A converter.

[0010]

However, when the D / A converter is configured as described above, immediately after the reference voltage is capacitively divided by the settling operation, a desired analog voltage corresponding to the input data is generated. Although it is obtained, after a while (for example, several msec.), The electric charge accumulated in each of the capacitors Ca to Cd is released, and the output voltage fluctuates or the output connecting one end of each of the capacitors Ca to Cd is connected. Depending on the wiring capacity of the line, the junction capacity of the analog switch connected to the output line, etc., this output line and the power supply (VDD) or this output line and the GND
There is a problem in that the output voltage may deviate from a normal value due to the parasitic capacitances Ce and Cf formed between the output voltage and (0 V).

Although the former problem (that is, fluctuation of output voltage) can be relatively easily solved by using a well-known sample-hold circuit, the latter problem (that is, output error due to parasitic capacitance). Cannot be easily solved.

That is, as shown in FIG. 8A, a capacitor Cg for storing electric charge and an operational amplifier (buffer) OPb for outputting a voltage of the capacitor Cg are provided on the output side of the buffer 54 via a switching element Sg. After the end of the settling operation, the switching element Sg is turned on to charge the capacitor Cg with a charge corresponding to the output of the buffer 54 within a period in which the output of the buffer 54 is stable. If the output from the sample hold circuit 60 is output as an analog voltage Vout representing the result of the D / A conversion, the output of the D / A converter can be stabilized.

However, the parasitic capacitances Ce and C of the output line
The output error due to f is, for example, as shown in FIG.
When the bias voltage VB is set to 0 V and the input data is “0000” and the normal divided voltage Vo becomes 0 V, the parasitic capacitances Ce and C are set between the biasing and the setting.
Since the potentials applied to the parasitic capacitances Ce and Cf are equal, there is no change in the amount of charge of the parasitic capacitances Ce and Cf.
Although no error occurs due to the influence of f, the difference between the potentials applied to the parasitic capacitances Ce and Cf at the time of bias and at the time of settling increases as the input data (and thus the divided voltage Vo) increases. The error of the voltage Vo increases. When the bias voltage VB is set to the reference voltage Vref, when the input data is “1111” and the normal divided voltage Vo becomes the reference voltage Vref, the divided voltage Vo is set.
Does not occur, the error in the divided voltage Vo increases as the input data (and thus the divided voltage Vo) decreases. Further, the bias voltage VB is changed to the reference voltage Vref.
(VB = Vref / 2), no error occurs when the divided voltage Vo reaches the bias voltage VB, but the error increases as the divided voltage Vo increases or decreases. . Therefore, the bias voltage V
If B is fixed, good output characteristics cannot be obtained regardless of the voltage value.

Therefore, the present inventors have considered a method of changing the bias voltage VB according to input data in order to solve this problem. For example, 4 shown in FIG.
In the case of a bit D / A converter, as shown in FIG.
A 2-bit voltage potentiometer type D / A converter (DAC) 62 using a resistor string is separately provided, and the upper two bits D2 and D3 of the input data D0 to D3 are converted to the two-bit D / A converter.
The analog voltage is converted by the / A converter 62 and the analog voltage is used for the bias voltage VB.

However, in this method, as shown in FIG. 9B, the error disappears at the point where the divided voltage Vo becomes equal to the bias voltage VB, but the error becomes the largest at the point where VB switches, and A linearity error also occurs. Also,
In this method, a D / A converter using a resistor string must be separately provided, and there is a problem that the cost is increased.

The present invention has been made in view of such a problem, and as described above, a load capacitance circuit (capacitor array)
In constructing the D / A converter using the above, it is possible to obtain a highly accurate D / A conversion result without being affected by the parasitic capacitance formed in the load capacitance circuit, and to realize the D / A converter with a simple configuration. The purpose is to.

[0017]

According to a first aspect of the present invention, there is provided a D / A converter for converting input data into an analog voltage. , And the capacity of each capacitor is weighted to 2 ⁱ times the reference capacity in accordance with each bit i (i: 0, 1,..., (N−1)) of the input data. A capacitance circuit (that is, the above-described capacitor array) is used.

First, the discharging means connects the both ends of each of the capacitors to each other to discharge the electric charge of each of the capacitors. Thereafter, the voltage dividing setting means sets the open ends of each of the capacitors to the respective capacitors. Depending on the bit value of the input data to be connected, by connecting to the positive potential side or the negative potential side of the reference voltage, the load capacitance circuit causes the reference voltage to be divided at a capacitance ratio according to the input data, and the holding means The divided voltage generated at the common connection point of the capacitors by the operation of the divided voltage setting means is sampled and the hold voltage is output as a voltage signal after D / A conversion. The discharging means, the voltage division setting means, and the holding means operate sequentially and repeatedly at predetermined intervals, and when the discharging means discharges each capacitor, the output from the holding means (that is, the output from the D / A converter). Output voltage) as the bias voltage,
Applied to both ends of each capacitor.

As a result, in the D / A converter of the present invention (claim 1), an error occurs temporarily in the output voltage immediately after the start of the D / A conversion or immediately after the input data changes. If the change of the input data does not occur for at least two or more periods of the D / A conversion of the predetermined period, each means performs the above-described bias operation, settling operation and sampling operation on the same input data. During the repetition, the output voltage becomes a normal voltage value corresponding to the input data, and it is possible to obtain a D / A conversion result with extremely high precision as compared with the above-described D / A converter. In addition,
The details of this operation will be described in detail in an embodiment described later.

Further, according to the present invention (claim 1), at the time of discharging operation, the last D / A conversion result sampled and held by the hold circuit is used as a bias voltage between both ends of each capacitor constituting the load capacitance circuit. You only need to apply
Since it is not necessary to separately provide a special circuit for improving accuracy, such as the above-described D / A converter using a resistor string, the D / A converter using the load capacitance circuit can be configured extremely simply. And the cost can be reduced.

Next, the D / A converter according to claim 2 is
The D / A conversion operation of the discharge means, the voltage division setting means, and the hold means at predetermined intervals is performed at least twice consecutively on the same input data. For this reason, a D / A converter that can always obtain a highly accurate D / A conversion result can be realized.

Next, in the D / A converter according to the third aspect, not only the n capacitors corresponding to the number of bits of the input data but also the capacitance are set to the reference capacitance, One end is provided with a correction capacitor connected together with these n capacitors. Then, the discharging means discharges the electric charge of the correcting capacitor together with the n capacitors, and the voltage dividing setting means connects the open end of the correcting capacitor to the negative potential side of the reference voltage.

As a result, according to the D / A converter of the present invention (claim 3), the reference voltage Vref is divided at a resolution of 1/2 ⁿ , and when the input data has the maximum value, the output voltage Vou
It operates as a general D / A converter in which t becomes “Vout = Vref · (2 ⁿ −1) / 2 ⁿ ”.

That is, when the D / A converter is constituted by using the load capacitance circuit composed of n capacitors as described in claim 1, more specifically, the load capacitance circuit is shown in FIG. When the capacitor array 52 is used, since the number of capacitors, that is, the number of capacitors Ca to Cd is four corresponding to the input data, the input data has the minimum value “000”.
0 ”, all the switching elements Sa to Sd are GN
D line (0V), the output voltage Vout is 0V
When the input data is the maximum value “1111”, all the switching elements Sa to Sd are connected to the reference voltage line (Vre
f), the output voltage Vout becomes Vref. Therefore, even with such a configuration, an analog voltage corresponding to input data can be obtained.

However, in general, if the input data is n bits, the D / A converter is required to output V / V with respect to the reference voltage Vref.
It has a resolution of ref / ²ⁿ and the input data is "1111"
, The output voltage Vout is configured to be Vref · 15/16. Therefore, in the present invention (claim 3),
A capacitor having a reference capacitance serving as a reference for weighting is separately used as a capacitor for output voltage correction so that the output characteristics are the same as those of a general D / A converter. Is connected to the negative potential side. As a result, according to the present invention (claim 3), a D / A converter that can obtain the same output characteristics as a conventionally used D / A converter using a load capacitance circuit (capacitor array) is provided. It is possible to provide a highly versatile D / A converter.

In the D / A converter according to the fourth aspect, the D / A converter according to the third aspect further includes:
A voltage potentiometer type D / A conversion circuit for outputting an analog voltage obtained by dividing the reference voltage by a resistance ratio according to the input data is provided, and at the time of settling operation, the open end of the correction capacitor is set by the voltage dividing setting means. It is connected to the output of the D / A conversion circuit.

As a result, according to the present invention (claim 4),
When the input data is a high bit, the upper n bits of the input data are D / A using a load capacitance circuit (capacitor array).
And the remaining lower x bits are D / A-converted by a voltage potentiometer type D / A conversion circuit, and the D / A conversion result by this voltage potentiometer type D / A conversion circuit is
It can be synthesized with the output voltage via the correction capacitor.

In this case, the circuit area of the load capacitance circuit (capacitor array) and the voltage potentiometer type D
Since the number of bits assigned to each circuit can be arbitrarily set in consideration of the circuit area of the resistor strings constituting the / A conversion circuit, the circuit area of the entire D / A converter can be reduced.
The size of the device can be reduced.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the D / A converter of this embodiment converts 4-bit input data Din (D0 to D3) into an analog voltage Vout, similarly to the D / A converter 52 shown in FIG. The D / A converter 10 includes a capacitor array 12 and a control unit 20 that controls the D / A converter 10.

The D / A converter 10 includes the capacitor array 1
2, a buffer 14 composed of an operational amplifier OP1 connected to the output line L of the capacitor array 12, and connected to the output of the buffer 14 via a switching element S8, and the output voltage is sampled and held when the switching element S8 is turned on. Capacitor (capacitor) C6
Sample and hold circuit 1 comprising an operational amplifier OP2
6 is provided.

Similarly to the capacitor array 52 shown in FIG. 8, the capacity of the capacitor array 12 corresponds to the number of bits (4 bits) of the input data, and the capacities are c, 2c, and c, respectively.
It includes four capacitors (capacitors) C2, C3, C4, and C5 set to 4c and 8c, and a capacitor (capacitor) C1 for correcting the output voltage of the capacitance c.

One end of each of the capacitors C1 to C5 is connected to each other to form an output line L, and the other end of each of the capacitors C2 to C5 is connected to
Each end is connected to a reference voltage line on the positive potential side to which the reference voltage Vref is applied, or GND on the negative potential side.
Switching elements S2 to S5 for switching between connecting a line or connecting an output line L are provided;
Further, the other end of the capacitor C1 is provided with a switching element S1 for switching between connection to a GND line and connection to an output line L. The output line L
And switching elements S1 to S5, switching elements S6 and S7 are provided. When the switching elements S6 and S7 are turned on, the switching elements S1 to S5 are turned on.
5 is switched to the output line L side to connect both ends of each of the capacitors C1 to C5, and to connect each of the capacitors C1 to C5.
C5 can be discharged.

The output of the sample and hold circuit 16 is connected to the discharge line of the electric charge between the switching elements S6 and S7. When the electric charge of each of the capacitors C1 to C5 is discharged, the potential between both ends of each of the capacitors C1 to C5 is changed. The output voltage Vout from the sample-and-hold circuit 16, and hence from the D / A converter, is applied.

The above eight switching elements S1 to S1
Among the switching elements S8, the switching elements S6 to S8 are each configured by one analog switch composed of an n-channel and a P-channel MOSFET. The switching element S1 has one end of the capacitor C1 selectively connected to the GND line and the output line L. In order to make connection, it is composed of two analog switches SW1 and SW2 composed of MOSFETs (FIG. 2).
(See (a)). Further, the switching elements S2 to S5 include three MOSFETs for selectively connecting one ends of the capacitors C2 to C5 to the reference voltage line, the GND line, and the output line L, respectively. Analog switch SW
1, SW2 and SW3 (see FIG. 2B).

On the other hand, as shown in FIG. 3, the control unit 20 divides the frequency of the external input clock CLK and generates a reference signal corresponding to a preset D / A conversion period To. And a latch circuit 24 that receives the reference signal from the frequency dividing circuit 22 and latches the input data Din in synchronization with the D / A conversion period To. A control for receiving a reference signal from the circuit 22 and generating a control signal for controlling switching timing of the switching elements S1 to S8 (in other words, operation timings of the bias operation, the settling operation, and the sampling operation). And a circuit 26.

That is, as shown in FIG. 4, the control unit 20 operates the control circuit 26 to operate the D / A conversion period To (from 10 μ to 50 μse in this embodiment) output from the frequency divider 22.
c. period), first, this D
A bias control signal that is at a high level for a predetermined period within the / A conversion period To, and a period between the fall of this control signal and the elapse of one D / A conversion period and the next rise of the control signal A settling control signal that goes high for a predetermined period of time, and goes high after a lapse of a predetermined time required for the control signal to go high to stabilize the divided voltage Vo of the output line L, and then the control signal goes high. A control signal for sampling, which becomes a low level before the signal is inverted to a low level, is generated.

The control circuit 26 generates the generated 3
When the control signal among the various kinds of control signals is at a high level, the switching elements S6 and S7 are turned on, and the switching elements S1 to S5 are switched to the switching element S6.
Is connected to discharge both ends of each of the capacitors C1 to C5, and the output voltage Vout of the sample and hold circuit 16 is applied as a bias voltage to both ends of each of the capacitors C1 to C5 (bias operation).

When the control signal is at the high level, the LSB (D0) side of the input data Din latched by the latch circuit 24 corresponds to the small-capacity capacitor C2 side so that each bit of the input data Din The values D0 to D3 correspond to the capacitors C2 to C5, and the bit values D0 to D3
Is the value "1", the switching elements S2 to S5 are switched to the reference voltage line side, and conversely, if the bit values D0 to D3 are the value "0", the switching elements S2 to S5 are switched to the GND line side. By switching to the line side, the reference voltage Vref is changed to Vref according to the input data Din.
The capacity is divided at a resolution of / 16 (set ring operation).

Further, when the control signal is at the high level, the switching element S8 is turned ON, and the voltage value of the output line L obtained by dividing the capacitance by the capacitor array 12 is calculated as follows.
The sample and hold circuit 16 performs a sample and hold (sampling operation). In the present embodiment, the control unit 20 and the switching elements S1 to S7 for performing the bias operation are used as a discharging unit, and the control unit 20 and the switching elements S1 to S5 for performing the settling operation are used as a discharge unit. The control unit 20, the switching element S8, and the sample and hold circuit 60 for executing the above-mentioned sampling operation correspond to the pressure setting means, respectively.

As described above, in the D / A converter of this embodiment, the bias operation, the settling operation, and the sampling operation are performed at a predetermined cycle (10 μsec to 50 μsec.).
To repeatedly convert the input voltage Din into the analog voltage Vout, and during the bias operation,
Each of the capacitors C1 to C constituting the capacitor array 52
5, an output voltage Vout is applied as a bias voltage.

Therefore, according to the D / A converter of this embodiment, immediately after the start of the D / A conversion or immediately after the input data changes, an error occurs temporarily in the output voltage. On the other hand, while the bias operation, the settling operation, and the sampling operation are repeated, the output voltage Vout becomes a normal voltage value corresponding to the input data Din, and a highly accurate D / A conversion result can be obtained.

In this embodiment, the capacitor array 1
2 is provided with a capacitor C1 for correcting the output voltage. At the time of settling, the open end side of the capacitor C1 is always
Since the switching element S1 is configured to be connected to the GND line, as shown in FIG. 5, the output voltage Vou
t is from “0000” to “1111” of the input data Din
0V to Vref · 15 / 16V corresponding to the change up to
Up to Vref / 16. For this reason, according to the present invention, the D / A, which has been generally used conventionally,
Output characteristics similar to those of the converter can be obtained.

Next, it will be verified how much the D / A conversion error can be improved by applying the output voltage Vout as a bias voltage to both ends of each of the capacitors C1 to C5. First, in the D / A converter of this embodiment, the reference value (reference capacitance) c of each of the capacitors C1 to C5 of the capacitor array 12 is set to 5 pF, and the parasitic capacitance C7 on the GND line side existing in the capacitor array 12 is set to 2 pF. , The parasitic capacitance C8 on the power supply line side is 2 pF. In this case, when the respective parasitic capacitances C7 and C8 are converted by the reference capacitance c, the parasitic capacitances C0 and.
4c.

The output error due to the parasitic capacitances C7 and C8 is largest when the input data Din is at the maximum value "1111" when the bias voltage is 0V, so that the power supply voltage VDD = the reference voltage Vref = 5V. , Output voltage is 0V
Then, an output error that occurs when the input data is switched to the maximum value “1111” from the state is calculated.

First, in the first conversion immediately after the input data Din changes to "1111", the output voltage Vout is 0 V. Therefore, at the time of the first bias, as shown in FIG. The bias voltage applied to both ends of .about.C5 is also 0V. Therefore, in this state, the total amount of electric charge of each of the capacitors C1 to C5, C7 and C8 is determined by the following equation (1) by the parasitic capacitance C8 between the output line L and the power supply VDD.
become that way.

(-5) · 0.4 = −2c (1) Next, at the time of settling, the switching element S1 is set to GN.
Since the switching elements S2 to S5 are connected to the reference voltage line according to the input data "1111", as shown in FIG. 6B, the switching elements S2 to S5 are connected to the open end potential of the capacitor C1. Is 0V, capacitors C2 to C5
Is the open end side potential Vref. As a result, the total amount of charge of each of the capacitors C1 to C5, C7, and C8 after the first settling is determined by calculating the voltage (divided voltage) of the output line L by Vo.
Then, the following equation (2) is obtained. (Vo-5) · (c + 2c + 4c + 8c + 0.4c) + Vo · (c + 0.4c) = 16.8Vo · c−77c (2) The amount of charge stored in the entire capacitors C1 to C5, C7, and C8 at the time of bias is set. Even if the charge is redistributed after the ring, the sum of the charge does not change.
From the equation (2), 16.8 Vo−77 c = −2 c, and when the divided voltage Vo is obtained, it becomes 4.4643 V.

Here, it is assumed that the capacitor array 12 is an ideal capacitor array without the parasitic capacitances C7 and C8, and when the output voltage Vo is obtained, the output voltages Vo are stored in all the capacitors C1 to C5, C7 and C8 at the time of bias. The total charge amount is 0 because the potentials at both ends of all the capacitors are 0 V. As a result, the total charge amount (ideal value) after settling in this case is as shown in the following equation (3). When the ideal divided voltage Vo is obtained from this equation, it becomes 4.6875 V.

(Vo−5) · (c + 2c + 4c + 8c) + Voc = 16Voc−75c (3) Therefore, when the parasitic capacitances C7 and C8 as described above exist, the divided voltage Vo and, consequently, the divided voltage Vo The error of the output voltage Vout is 4.4463 V−4.6875 V = −223.3 m
V.

However, in this embodiment, since the output voltage Vout is used as the bias voltage, the first output voltage 4.4 is used as the second bias voltage as shown in FIG.
643V will be used. Therefore, when the input data Din is “1111”, the total charge amount of all the capacitors at the time of the second bias is 0 because the potentials at both ends of the capacitors C1 to C5 are 4.4643V, and the parasitic capacitance is 0. Considering C7 and C8, the following equation (4) is obtained.

(4.464-5) · 0.4c + 4.4643 · 0.4c = 1.57144c (4) Since the charge amount after settling is as in the above equation (2), When the divided voltage Vo is obtained by assuming that the amount of charge at the time is equal to this, it becomes 4.67671 V.
For this reason, the error of the divided voltage Vo and, consequently, of the output voltage Vout is 4.676871V-4.6875V = -10.
63 mV (2.073%), which is greatly improved.

Further, a third output voltage Vo is calculated.
The bias voltage is the second output voltage 4.676871V.
And the total charge of all capacitors is given by the following equation (5). (4.676871-5) · 0.4c + 4.676871 · 0.4c = 1.714472c (5) Since the charge amount after settling is as in the above equation (2), the charge amount at the time of biasing is When the divided voltage Vo is determined as equal to this, it becomes 4.686992V. Therefore,
3. The error of the divided voltage Vo, and hence the output voltage Vout, is 4.
686992V-4.6875V = -0.5076mV
(0.010%), which is further improved.

This operation will be described with reference to the time chart of FIG. The D / A conversion is repeated at a period To, and the D / A conversion is continuously performed on the same data at least twice or more. The input data is taken into the latch at the rise of the settling signal, and the switching data is used by the switching elements S2 to S5 to set the reference voltage Vref,
Or, it is switched to GND.

In the first D / A conversion of the input data Din2, both ends of the capacitor are biased by the output voltage of the previous input data Din1 at the time of bias, so that the input data Din2 is affected by the parasitic capacitance of the output of the capacitor array. A large error occurs in the D / A conversion value of
2 is lower than the theoretical output voltage.

In the second conversion, the bias voltage becomes the first output voltage, the error decreases, and the output voltage approaches the theoretical value. The input data Din3 is continuously converted three times. In the first conversion, since the bias voltage is the output voltage based on the input data Din2 of the previous conversion, the error is large. With the conversion, it approaches the ideal value.

As described above, according to the present embodiment, since the output voltage Vout which is the result of the previous D / A conversion is used as the bias voltage, the D / A conversion (bias, settling, sampling operation) is repeated. And the parasitic capacitance C7, C
8 can be reduced and the error can be made to converge to zero. According to the present embodiment, the output voltage V
out only needs to be applied as a bias voltage to both ends of the capacitors C1 to C5, and it is not necessary to separately provide a special circuit for improving the D / A conversion accuracy. Therefore, a D / A converter using a capacitor array is required. , The configuration can be extremely simplified, and the cost can be reduced.

As described above, one embodiment of the present invention has been described. However, the present invention is not limited to the above-described embodiment, and can take various forms. For example, in the above embodiment, a 4-bit D / A converter has been described. However, when the number of bits of input data is large, the number of capacitors and switching elements constituting a capacitor array is increased according to the number of bits. do it. In such a capacitor array, each capacitor can be formed with high precision (that is, without variation in capacitance) in a CMOS circuit, and the number of bits of input data can be reduced as in a voltage potentiometer type D / A converter using resistor strings. Is not limited by the deterioration of accuracy, and can correspond to high-bit input data.

As shown in FIG. 7, for example, a 4-bit D / A converter constructed in the same manner as the D / A converter 10 of the above embodiment is used.
The conversion unit is used as a high-order 4-bit D / A conversion unit 30 for converting the high-order n bits (4 bits) of the m-bit (m = n + x) input data Din into an analog voltage. When the unit 30 is set, the output voltage correcting capacitor C1 is connected to the output voltage correcting capacitor C1 via the switching element S1.
Voltage potentiometer type D composed of resistor strings
A / A converter circuit is input, and this D / A converter circuit is used as an upper x bit D / A converter 40 for converting lower x bits of input data Din into an analog voltage. You may.

In this case, the upper 4 bits of the input data Din are converted to the upper 4 bits D /
The A / D converter 30 performs D / A conversion, and converts the lower x bits of the input data Din into lower x bits D / A of the voltage potentiometer type.
The A / D converter 40 performs D / A conversion, and the D / A conversion results obtained by the D / A converters 30 and 40 are combined via the capacitor C1, and the reference voltage Vref is set according to the input data Din. Output voltage Vou divided at a resolution of Vref / m ²
t can be generated.

The lower x-bit D / A converter shown in FIG.
40 has y resistance values (y = 2 ^x ) Resistors R0
Ry are connected in series, and both ends thereof are connected to a reference voltage line and a GN.
Each resistor R0 to R
y, the reference voltage Vref is divided into resistors R0 to Ry.
Switching elements S provided on the ground line side of
r1 through Sry, the input data Din
Value of x bits of order 2^x Voltage can be extracted corresponding to
It is configured as follows. Then, the control unit 20 '
The switching element for extracting the divided voltage
Control signal for switching according to the lower x bits of the
A control circuit for generating a signal is also provided. In addition, for this
The circuit configuration is well known.
Therefore, detailed description is omitted.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a configuration of a D / A converter according to an embodiment.

FIG. 2 is an explanatory diagram illustrating a configuration of a switching element connected to each capacitor forming a capacitor array.

FIG. 3 is a block diagram illustrating a configuration of a control unit.

FIG. 4 is a time chart for explaining the operation of the D / A converter according to the embodiment.

FIG. 5 is an explanatory diagram illustrating output characteristics of the D / A converter according to the embodiment.

FIG. 6 is an operation explanatory diagram illustrating a convergence process of an output error by the D / A converter according to the embodiment.

FIG. 7 is an explanatory diagram showing a configuration of a D / A converter in which a D / A converter using a capacitor array and a voltage potentiometer type D / A converter are combined.

FIG. 8 is an explanatory diagram illustrating a configuration of a D / A converter including a capacitor array used in a conventional successive approximation type A / D converter and a proposal for improvement thereof.

FIG. 9 is an explanatory diagram illustrating output characteristics of the D / A converter illustrated in FIG. 9;

[Explanation of symbols]

10 D / A converter 12 Capacitor array 1
DESCRIPTION OF SYMBOLS 4 ... Buffer 16 ... Sample hold circuit 20 ... Control part S1-S8 ... Switching element C1-C6 ... Capacitor (capacitor) C7, C8 ... Parasitic capacitance 22 ... Divider circuit 24 ... Latch circuit 26 ... Control circuit 30 ... Upper 4 bits D / A converter 40... Lower-order x-bit D / A converter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-3522 (JP, A) JP-A-1-296823 (JP, A) JP-A-1-112824 (JP, A) JP-A-58-58 114527 (JP, A) JP-A-55-55622 (JP, A) JP-A-2-151126 (JP, A) JP-A-62-165438 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. A D / A converter for converting n-bit digital input data into an analog voltage, comprising: n capacitors having one end connected to each other, and determining a capacitance of each capacitor by each of the input data. Bit i (i: 0,
1,..., (N-1)), respectively, a load capacitance circuit weighted to 2 ⁱ times the reference capacitance, and at each predetermined period, both ends of each capacitor for a predetermined time shorter than the period. Discharging means for discharging the electric charge of each capacitor, and discharging the electric charge of each of the capacitors at every predetermined period. By connecting to the positive potential side or the negative potential side of the reference voltage according to the bit value of the input data corresponding to the above, the load capacitance circuit divides the reference voltage at a capacitance ratio according to the input data. A voltage dividing setting means for causing the voltage dividing means to sample and hold the divided voltage generated at a common connection point of the capacitors by the operation of the voltage dividing setting means, and outputting the hold voltage as a voltage signal after D / A conversion Means, A D / A converter, wherein when the discharging means discharges each of the capacitors, an output from the holding means is applied as a bias voltage to both ends of each of the capacitors. 2. The method according to claim 1, wherein the D / A conversion operation of the discharging means, the voltage setting means, and the holding means at predetermined intervals is performed for the same input data at least twice consecutively. Item 3. The D / A converter according to Item 1. 3. The D / A converter according to claim 1, wherein the load capacitance circuit includes:
A capacitor having a capacity set to the reference capacity, one end of which is connected to one another together with the n capacitors, wherein the discharging means also discharges the charge of the correction capacitor together with the capacitors at each of the predetermined periods. The D / A converter, wherein the voltage division setting means connects an open end of the correction capacitor to a negative potential side of a reference voltage at every predetermined cycle. 4. The D / A converter according to claim 3, further comprising: a voltage potentiometer type D / A conversion circuit that outputs an analog voltage obtained by dividing the reference voltage by a resistance ratio according to input data, The voltage dividing setting means is configured to connect the open end of the correcting capacitor to the output of the D / A conversion circuit instead of the negative potential side of the reference voltage at every predetermined cycle. D / A converter.