KR100336781B1 - Analog to digital converter - Google Patents

Abstract

The present invention relates to an analog-to-digital converter, comprising: a signal input unit for selectively outputting an analog input signal or first and second reference voltages Vref and Vgnd under the control of a controller; The switches SW1 to SWn receiving the analog signals or the first and second reference voltages input from the signal input unit under the control of the control unit, and the respective switches for de-converting the signals input through the switches SW1 to SWn ( And a plurality of die converters including a plurality of capacitor arrays configured to sample / hold an analog signal or first and second reference voltages inputted through SW1 to SWn, and output a value and a reference voltage ( A comparator for comparing and outputting Vref); A continuous approximation register for storing a value output from the comparison section; It receives the data output from the continuous approximation register and transfers it to the Dee converter unit or configures the control unit to control the operation of each component to divide the analog input signal by using the number of the Dee converter and the number of comparators as necessary to the Dee converter It is possible to have a high speed and high resolution without increasing the resolution, the power consumption can be reduced.

Description

Analog-to-digital converters {ANALOG TO DIGITAL CONVERTER}

The present invention relates to an analog-to-digital converter, and more particularly, by dividing the SAR-type analog-to-digital converter, by dividing the analog input signal as necessary by using the number of the number of the die converter and the comparator thereof, The present invention relates to an analog-to-digital converter capable of high speed, high resolution, and low power consumption without increasing the power consumption.

FIG. 1 is a block diagram showing the configuration of a typical SAR (Successive Approximation Register) type analog / digital converter. As shown in FIG. 2) and; A comparator 3 for receiving a reference voltage V _ref output from the ADC 7 and comparing the magnitudes of the two signals; A continuous approximation register (SAR) 4 for storing a value output from the comparison section 3; It is composed of a Dee converter 7 for receiving the data (D0 ~ Dn, 5) output from the continuous approximation register (4) to create a new reference voltage (V _ref ) and outputs, the operation of the conventional ADC converter The operation is described as follows.

First, the value of the continuous approximation register 4 is initialized to 0, the reference voltage V _ref of the die converter 7 is made to be 1/2 of the power supply voltage VDD, and then the analog input terminal of the comparator 3 ( Input analog signal (1) to be converted into +).

The comparison portion 3 is the sampling / holding the analog signal 1 and the reference voltage (V _ref) by comparing the size of the analog signal 1 is greater than the reference voltage (V _ref) for outputting a 'high' level based When the analog signal 1 is smaller than the reference voltage V _ref , a 'low' level is output and stored in the most significant bit MSB of the continuous approximation register 4.

Next, the die converter 7 reads the value of the continuous approximation register 4 to generate and output a new reference voltage V _ref .

Accordingly, the comparator 3 compares the magnitude of the analog signal 1 and the newly generated reference voltage V _{ref again} , and as described above, according to the result, a 'high' or 'low' level value. Is outputted and stored in the next bit (MSB-1) th of the uppermost register of the approximation register 2, and the ADC converter 7 generates a new reference voltage V _ref using it again.

This process is repeated until the least significant bit LSB of the approximation register 2 is obtained, and the value finally filled up to the least significant bit LSB becomes the digital value to which the analog signal 1 is converted.

However, in the conventional technology, in the case of configuring a die converter, a resistor string or an R-2R ladder structure and a capacitor array together with them may be simultaneously configured. In the case of having a resolution, the conventional integrated technology has difficulty in forming resistors and capacitors, and also has a problem in that the accuracy of the DC converter is poor because it is difficult to maintain constant characteristics over the entire range.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, by using the SAR type analog-to-digital converter, the number of the analog converter and the number of comparator, the component of the analog input signal as necessary By subdividing, an object of the present invention is to provide an analog-to-digital converter that can have high speed and high resolution and can reduce power consumption without increasing the resolution of the die converter.

1 is a block diagram showing the configuration of a typical SAR type analog-to-digital converter.

Figure 2 is a block diagram showing the configuration of the AD converter according to the present invention.

3 is a block diagram showing a detailed configuration of a die converter in FIG.

4 is a circuit diagram illustrating a detailed configuration of each of the die converters of the die converter unit in FIG. 3; FIG.

FIG. 5 is a circuit diagram illustrating a detailed configuration of each of the die converters and the switches in FIG.

*** Description of the symbols for the main parts of the drawings ***

9: die converter 91 to 9n: die converter

10: signal input unit 11, 12: switch

13 comparison unit 14 reference voltage application unit

15: continuous approximation register 16: control unit

SW1 to SWn: switch C10 to C4n: capacitor

The present invention for achieving the above object is a signal input unit for selectively outputting the analog input signal or the first, second reference voltage (Vref, Vgnd) under the control of the controller; The switches SW1 to SWn receiving the analog signals or the first and second reference voltages input from the signal input unit under the control of the control unit, and the respective switches for de-converting the signals input through the switches SW1 to SWn ( And a plurality of die converters including a plurality of capacitor arrays configured to sample / hold an analog signal or first and second reference voltages inputted through SW1 to SWn, and output a value and a reference voltage ( A comparator for comparing and outputting Vref); A continuous approximation register for storing a value output from the comparison section; The controller may be configured to receive data output from the successive approximation register and transfer the data to the die converter or control the operation of each component.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the structure of the AD converter according to the present invention, and as shown in FIG. A signal input unit 10 selectively outputting by control; A die converter (9) for receiving a signal input through the signal input unit (10) and performing a die conversion on a data bit input through the control unit (16); A comparison unit 13 for comparing and outputting a value output from the die converter unit 9 with a reference voltage V _ref ; A continuous approximation register (SAR) 15 for storing a value output from the comparison section 13; The control unit 16 receives the data D _{1 to} Dn output from the continuous approximation register 15 and transmits the data D _{1 to} Dn to the ADC converter 9 or controls the operation of each component.

Here, the die converter 9 includes switches SW1 to SWn for receiving an analog signal or first and second reference voltages input from the signal input unit 10 under the control of the controller 16 as shown in FIG. 3. )Wow; A plurality of die converters 91 to 9n for performing a die conversion of a signal input through the switches SW1 to SWn are configured.

In this case, each of the die converters 91 to 9n includes a plurality of capacitor arrays which sample / hold the analog signals or the first and second reference voltages inputted through the switches SW1 to SWn as shown in FIG. 4. 9 to 9nn, and FIG. 5 illustrates a detailed configuration of each of the die converters and the switches in FIG. 3. Hereinafter, the operation of the present invention configured as described above will be described.

When the analog signal 1 is input through the signal input unit 10, the signal input unit 10 may convert the analog signal 1, the reference voltage Vref, and the ground voltage Vgnd by the control unit 16 into a die converter unit ( Enter 9).

Next, the signal input unit 10 is cut off, and the analog signal 1 is charged to the respective capacitors C10 to C4n in the die converter unit 9 as shown in FIG. These capacitor arrays C10 to C4n serve as a charge redistribution function and a sample / hold function of an input signal.

In this state, the outputs of the respective die converters 91 to 9n and the reference potentials 10a to 10n are compared by the comparators 3a to 3n. Based on this comparison result, the continuous approximation register 15 outputs necessary bit data D _{1 to} Dn and a digital signal.

FIG. 3 is a detailed configuration diagram of the die converter unit 9, wherein a plurality of die converters 91 to 9n are included in the die converter unit 9, and details of the respective die converters 91 to 9n are shown in FIG. As shown in Fig. 4, the configuration is composed of a plurality of capacitor arrays 911 to 91n.

The capacitor array 911 may be configured as S10, S11 = 1C, S12 = 2C, S13 = 4C, and S14 = 8C ...., and the remaining capacitor arrays 912, 913, ... 91n are configured in the same manner. can do.

For reference, since n = 4 in S14, 6 = 4 + X and (X = 2) in N bits (n-1 capacitor) + X.

Then, four components are required because a component such as capacitor array 911 can be configured as 2 ^X.

That is, if there are four of the capacitor arrays 911, 912, 913, and 914, 6 bits may be converted.

Next, in addition to the analog signal 1, a first reference voltage Vref and a second reference voltage Vgnd are applied to the input terminal of the ADC converter 9, and the capacitor 10a of FIG. 2 is a capacitor array 911, 912, and 913. 914, the sum of all capacitances of the capacitor, that is, 64C, and other capacitors (10b, 10c, 10d) is also configured to 64C.

Under the above conditions, the AD converter operates as follows.

That is, S10 to S14, S20 to S24, S30 to S34, and S40 to S44 of the capacitor arrays 911, 912, 913, and 914 receive the analog signal 1 through the switches SW1 to SWn of FIG. Switches 11 and 12 in Fig. 2 are turned on.

In this state, the analog signal 1 is sampled in the capacitor string inside the capacitor arrays 911, 912, 913, and 914 of the die converter 91.

Next, the switches 11 and 12 are turned off, and at the same time, the state of the output terminals D _{1 to} D ₆ of the continuous approximation register 15 is D ₁ = '1', and the remaining D _{2 to} D ₆ = '0'. Is set to

In accordance with the determination of the continuous approximation register 15, the control unit 16 blocks (not connects) S10 to S14, S20 to S24, S30 to S34, and S40 to S44 so that the analog signal 1 is not applied.

At this time, since the bit data D ₁ = '1', the controller 8 connects the capacitors C14, C24, C34, and C44 with the first reference voltage Vref.

Since the remaining bit data is kept at '0', S10 to S13, S20 to S23, S30 to S33, and S40 to S43 are connected to the second reference voltage (= Vgnd).

In this state, the potentials of the inverting input terminal and the non-inverting input terminal of the comparator 3a can be defined as follows.

If inverting input terminal = V _II , non-inverting input terminal = V _NI , analog input = V _IN , V _NI is [Vref / 2], so [Vref / 2] 64C-V _IN 64C = (V _II -Vref) 32C + (V _II -0) 32C, V _II = Vref-V _IN , and the die converters 92, 93, ... 9n also apply on the same principle.

Here, if V _IN [Vref / 2], the comparator 3a outputs a logic signal '1', and if V _IN is small, a comparator 3a outputs a logic signal '0'.

Next, the output of the comparator 3a is passed to the continuous approximation register 15 so that the comparison of the second valid bit begins.

At the same time as D ₁ = '1', D ₂ is preset to '1', and the remaining D _{3 to} D ₆ are in logic '0'.

Receiving bit data of D ₁ = '1' and D _{3 to} D ₆ = '0' from the continuous approximation register 15, the controller 8 applies the switches inside the die converter unit 9 as shown in Table 1 below. do.

-S10-C10 -S20-C20 -S30-C30 -S40-C40 Vgnd is approved -S11-C11 -S21-C21 -S31-C31 -S41-C41 Vgnd is approved -S12-C12 -S22-C22 -S32-C32 -S42-C42 Vgnd is approved -S13-C13 -S23-C23 -S33-C33 -S43-C43 Vref is approved -S1n-C1n -S2n-C2n -S3n-C3n -S4n-C4n Vref is approved

At this time, the potential of the input terminals of the comparator 3a is V _NI = [Vref / 2], so [Vref / 2] 64C-V _IN 64C = (V _II -Vref) 48C + (V _II -0) 16C, V _II = [5Vref / 4]-becomes V _IN . The remaining die converters 92, 93, ... 9n also apply on the same principle.

If V _IN [3Vref / 4], the output of comparator 91 is '1' and vice versa.

That is, the D ₃ is set free at the same time as D ₂ is set.

This operation is repeated until the LSB is determined.

As a whole, the above operation is performed when the analog signal 1 is inputted, and a part of the analog signal is first controlled by the controller 16 by the switch SW1 shown in FIG. At the same time, the continuous approximation register 15 generates a logic signal '1' which is a preset and codes S10 to S1n inside the die converter 91 to compare the signal with the comparator 3a sampled / held to compare the continuous approximation register ( 15)

Next, the next portion of the analog input signal is first sampled / held by the switch SW3 of FIG. 3 to the capacitor array of the die converter 93 and at the same time the continuous approximation register 15 receives the preset logic signal '1'. The process of generating and coding S30 to S3n in the die converter 93 to repeat the comparator 3b is sampled / held and compared with the signal to be sent to the continuous approximation register 15.

In other words, the number of die converters and the number of comparators may be adjusted according to how finely the analog input signal is divided, thereby improving characteristics without increasing or decreasing the resolution of the die converter.

As described above, the analog-to-digital converter of the present invention divides the analog-to-digital converter of the SAR type by subdividing the analog input signal as necessary by using the number of die converters and the number of comparators thereof. It can have a high speed and high resolution without increasing the power consumption, it is possible to reduce the power consumption.

Claims (3)

A signal input unit for selectively outputting an analog input signal or first and second reference voltages Vref and Vgnd under the control of a controller; The switches SW1 to SWn receiving the analog signals or the first and second reference voltages input from the signal input unit under the control of the control unit, and the respective switches for de-converting the signals input through the switches SW1 to SWn ( And a plurality of die converters including a plurality of capacitor arrays configured to sample / hold an analog signal or first and second reference voltages inputted through SW1 to SWn, and output a value and a reference voltage ( A comparator for comparing and outputting Vref); A continuous approximation register for storing a value output from the comparison section; And a controller configured to receive data output from the successive approximation register and transfer the data to the die converter or control the operation of each component. delete delete