KR20050117321A - Successive approximation register adc reusing a unit block of adc for implementing high bit resolution - Google Patents

Abstract

The present invention relates to an N-bit sequential approximation analog-to-digital converter (SAR ADC), which receives the analog signal, divides a reference voltage according to the N-bit digital code, and compares it with the input signal. When the N bit digital code determination is completed by the N bit sequential approximation analog-to-digital converter that sequentially determines the N bits digital code corresponding to the input signal bit by bit, and the N bit sequential approximation analog to digital converter, The N-bit sequential approximation analog-to-digital converter is input to an ^N- bit sequential approximation analog-to-digital converter, divides the reference voltage by 2 ^N times, and sequentially determines subsequent bits until the determination of the digital code is completed. Control means for controlling the. According to the present invention, a SAR ADC can be easily implemented using a SAR block as a unit block, and a high resolution SAR ADC can be implemented in a small area by reducing the number and area of capacitors used in the SAR ADC. have.

Description

SUCCESSIVE APPROXIMATION REGISTER ADC REUSING A UNIT BLOCK OF ADC FOR IMPLEMENTING HIGH BIT RESOLUTION

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a successive approximation register ADC (SAR ADC), and in particular, a number and size of capacitors required by reusing a successive approximation ADC as a unit block. It relates to a SAR ADC that reduces and achieves higher resolution.

An ADC is a device for converting an analog signal into a digital code. The ADC is sampled and converted into a digital code or a digital signal corresponding to its magnitude. Among such ADCs, in particular, SAR ADCs have a successive approximation register (SAR), which combines digital codes sequentially with increasing or decreasing high order bits to compare them with analog signals, thereby approximating analog input signals.

FIG. 1 shows the configuration of a conventional SAR ADC, which is composed of an N-bit Digital-to-Analog Converter (DAC) 100 and a comparator 200. The N bit DAC 100 converts the N bit digital code into an analog voltage Vc corresponding thereto. The comparator 200 compares the analog voltage Vc output from the N-bit DAC with the analog signal V _IN to be converted. If the analog signal V _IN is greater than the analog voltage Vc as the comparison signal, the comparator output D _P becomes a high level Hi, that is, a logic value 1. On the contrary, if the analog voltage Vc output from the DAC 100 is greater than the analog signal V _IN , the comparator 200 outputs a signal of a low level Lo, that is, a logic value 0.

Accordingly, the most significant bit (MSB) of the digital code input to the N-bit DAC 100 is set to a logic value 1, and the analog signal V _IN and the N bit are set. Comparing the analog voltage Vc output from the DAC 100, it is possible to determine the value of the MSB of the N-bit digital code. Subsequently, the above-described comparison process is repeated while sequentially changing subsequent bits of the digital code input to the N-bit DAC 100, thereby determining the N-bit digital code corresponding to the analog signal V _IN .

FIG. 2 illustrates a SAR ADC configuring the N-bit DAC 100 of FIG. 1 using a resistor array as an example of a SAR ADC, as disclosed in Korean Patent Publication No. 261997. As shown in FIG. 2, the resistor array type DAC includes a voltage divider in which n + 1 resistors R1 to Rn + 1 are connected in series to distribute the reference voltage V _REF at predetermined intervals. In the voltage divider, the node whether 1/2, and outputs the phase voltage of the n levels decreasing from VDD to 1/2 ⁿ · VDD, the output of each voltage between the resistors n switches (SW1~SWn) Is optionally controlled.

Each switch SW1 to SWn is controlled to correspond to each bit of the N bit digital code by a control means (not shown). That is, the highest level voltage (V _REF / 2) generated by the voltage divider is turned on when the MSB of the N-bit digital code is a logic value 1, and the remaining switches are turned on when each corresponding bit is a logic value 1. Thus, the magnitude of the analog voltage output from the voltage divider increases in proportion to the magnitude of the digital code output by the control means.

FIG. 3 is a time chart illustrating a conversion operation of a SAR ADC according to the prior art, and the operation of the SAR ADC in 6-bit analog-to-digital conversion will be described in detail with reference to FIGS. 2 and 3.

First, in FIG. 2, the switch SW1 corresponding to the MSB is turned ON at a time t1 (corresponding to the digital code '100000'), and the output VREF / 2 of the N-bit DAC is compared with the analog signal V _IN . When the analog signal V _IN is greater. Accordingly, the output DP of the comparator in FIG. 3 becomes a logic value 1. According to the comparison result, the MSB of the digital code corresponding to the analog signal V _IN is determined to be 1, and the switch SW1 is kept ON. Then, the switch SW2 corresponding to the bit following the MSB is turned ON (corresponding to the digital code '110000'), and compared with the analog signal V _IN (t2), as shown in FIG. 3, the output of the comparator is shown. Since (DP) is logical value 0, the bit following MSB is determined to be zero. The switch SW2 is changed to the OFF state to maintain the state thereafter. By repeating the determination of subsequent bits according to the method described above (t3, t4, t5, t6), the voltage Vc output from the DAC is sequentially approximated to the analog signal V _IN , and ultimately the analog signal. A digital code of "100100" corresponding to (V _IN ) can be obtained.

However, the above-described resistor array type DAC has a disadvantage of high power consumption. Therefore, in recent years, focusing on the relatively large ON resistance of a metal oxide semiconductor (MOS), it is common to configure a DAC with a capacitor array having a binary weighted capacitance, which is called a capacitor array type DAC. It is called.

4 illustrates a configuration of a weighted-C SAR ADC according to the prior art.

As shown in FIG. 4, the weighted-capacity DACs constituting the weighted-capacity SAR ADC are (N + 1) with binary weights of 2 ^N-1 C, ..., 2 ¹ C, 2 ⁰ C, 2 ⁰ C. It consists of a capacitor array consisting of two capacitors. In the capacitor array, the capacitor capacity doubles as the bit increases based on the base capacity C of the capacitor corresponding to the least significant bit (LSB, Least Significant Bit, hereinafter referred to as "LSB"). The capacitance of the capacitor corresponding to the MSB of the N bit digital code is 2 ^N-1 C.

One end of the capacitor array is commonly connected to ground (GND) when the switch S _SP is turned on, and the other end of the capacitor array has (N + 1) switches (S _N− ) for selectively interrupting each capacitor. ₁ , S _N-2, ..., S ₁ , S ₀ , S _-1 ). The (N + 1) switches S _N-1 , S _N-2, ..., S ₁ , S ₀ , S _-1 are provided with a logic value 0 from a control means (not shown). Each capacitor is connected to ground GND, and when a signal of logic value 1 is input from the control means, each capacitor is commonly connected to one end of the switch S _R. Switch control signal inputted to the _{(S N-1, S N} -2, ..., S 0) is, corresponding to each bit of the digital code of N bits to determine the analog signal as will be described later. The switch is connected to the analog signal to the other end of the signal is logical value 0, the switch (S _R) for controlling (S _R) is converted, the switch (S _R) the control signal is a logic value 1 when the reference voltage (V _REF that )

The output voltage V _X of the capacitor array output from the node to which one end of the (N + 1) capacitors are commonly connected is input to the non-inverting terminal (+) of the comparator 200, and the inverting terminal (-) of the comparator is provided. Is connected to ground. Comparator 200 compares the output voltage (V _X ) and zero potential (0 V) of the capacitor array, and outputs a logic value of 1 when the output voltage (V _X ) of the capacitor array is greater than 0 V. Can be configured to output a logical value of zero. Meanwhile, the resistance array type SAR ADC of FIG. 2 directly compares the analog signal V _{IN with} the DAC output voltage V _C corresponding to the digital code, whereas the weighted-capacity SAR ADC shown in FIG. 3 corresponds to the digital code. Is configured to compare V _X corresponding to the difference between the voltage generated by the opening and closing of the switches S _N-1 , S _N-2 , ..., S ₀ and the analog signal V _IN with a zero potential. . However, one skilled in the art will understand that the two methods are based on the same principle.

The weighted-capacity SAR ADC shown in FIG. 4 performs a conversion process through three steps of sampling, holding, and redistribution.

In the first sampling step, according to the digital code input from the control means, the switch S _R of FIG. 3 is connected to the analog signal V _IN , the switch S _SP is connected to ground, and the switch S _N-1 S ₀ and S ₋₁ are connected to the switch S _R. Accordingly, in the sampling step, all capacitors of the capacitor array store the analog signal V _IN .

In the holding phase, the switch (S _SP ) is turned OFF to isolate it from ground and the switches (S _N-1 to S ₀ and S _-1 ) are connected to ground, so that the output voltage (V _X ) of the capacitor array is The inversion of the analog signal, i.e. -V _IN .

Finally, in the redistribution phase, the switch S _{R is} connected to the reference voltage V _REF . First, in order to determine the MSB of the N-bit digital code corresponding to the input analog signal, the switch S _N-1 is turned on and the reference voltage V _REF at the other end of the capacitor 2 ^N-1 C corresponding to the MSB. When is connected, the reference voltage V _REF is divided according to the capacitor capacity. Accordingly, the output voltage V _X of the capacitor array is expressed by Equation 1 below.

At this time, the comparator output V _O outputs a logic value 1 (Hi) when V _X is greater than 0 V and a logic value 0 (Lo) when less than 0 V. If the comparator output (V _O ) is a logic value of 1, since the magnitude of the analog signal is smaller than V _REF / 2, it is determined that the MSB of the N-bit digital code corresponding to the analog signal is 0, and thus the switch S of the MSB _N-1 ) to ground again. If the comparator output (V _O) is a logic value 0, it is determined to be the MSB of the N-bit digital code 1, thereby keeping the switch (S _N-1) in the ON state. Following the MSB is determined, the switch with respect to (S _N-2 to S ₀₎ and the next ranked bits determined by repeating the redistribution step sequentially, so that the switch (S _N-2 to S ₀₎ state (ON or OFF of ) Can be set.

As a result, the state or position of the switch (S _N-1 to S ₀ ) is converted to the N-bit digital code, which is expressed by the equation (2). In Equation 2, b _i corresponds to a code obtained by converting an analog signal V _IN into digital, which corresponds to ON / OFF states of the switches S _N-1 to S ₀ .

In the case of an N-bit SAR ADC, the DAC output voltage change and compare operations are performed during N cycles, and the analog signals are sequentially approximated from the MSB. In this case, Vx corresponds to a determination error or a conversion error and converges to zero as the approximation proceeds.

As we have seen, weighted-capacity SAR ADCs are ideal for CMOS technology because they consist of simple devices such as comparators and DACs, and precise analog devices are not used. However, conventional weighted-capacity SAR ADCs require an additional capacitor with twice the capacity as the resolution increases. As a result, high resolution ADCs typically use very large capacitor arrays, making it difficult to implement 10-bit or larger ADCs. Moreover, since the capacity ratio of the capacitor of the MSB and the capacitor of the LSB is very large, 2 ^N-1 times, there is a problem that it is not easy to accurately implement such a capacity ratio.

In order to solve the above problems, the present invention makes it possible to easily implement a SAR ADC having a higher resolution by using a SAR ADC as a unit block, and freely resolution according to an application using a SAR ADC block having a predetermined resolution. The goal is to make it extensible.

In addition, another object of the present invention is to reduce the number and area of the capacitors used in the SAR ADC to implement a high resolution SAR ADC in a small area.

According to the first aspect of the present invention, a SAR ADC for reusing an N bit sequential approximation analog-to-digital converter and converting an analog signal into a digital code of M bits (M> N) is provided. N bits for receiving the analog signal, distributing a reference voltage according to an N bit digital code, comparing the input voltage with an input signal, and sequentially determining the N bit digital code corresponding to the input signal sequentially bit by bit according to the comparison result. When the N-bit digital code determination is completed by the successive approximation analog-to-digital converter and the N-bit difference approximation analog-to-digital converter, a determination error is inputted to the N-bit difference approximation analog-to-digital converter and the reference voltage is set to 2. the ^N-fold division, and to determine the following bits in sequence until the determination of the complete M-bit digital code N Bit axis by step scanning analog-to-digital control means for controlling the converter.

According to a second aspect of the present invention, there is provided a successive approximation analog-to-digital converter (ADC) for converting an analog signal into an M-bit digital code, and receiving the analog signal in accordance with a ratio of a reference voltage and an input signal. An N-bit analog-to-digital converter for determining a digital code of N bits (N <M), and when the N-bit determination is completed by the analog-to-digital converter, a determination error is inputted to the analog-to-digital converter and a reference voltage is ^2N. And control means for controlling the analog-to-digital converter to divide in double and repeat the determination until the determination of the M bit digital code is completed.

According to a third aspect of the present invention, there is provided a weighted capacitance approximation analog-to-digital converter (C-weighted SAR ADC) for converting an analog signal into an M-bit digital code, and storing an inverted value of the analog signal. A capacitor array having a weighted capacitance for dividing a reference voltage into a plurality of levels according to a digital code of N bits (N <M) and adding the divided voltage to a storage signal and outputting the stored voltage; A comparator for comparing the stored signal with a voltage divided according to a digital code, and sequentially providing the N bit digital code to the capacitor array and a voltage distributed by the capacitor array according to the output of the comparator to the stored signal. A digital code of N bits corresponding to the stored signal is sequentially determined bit by bit by approximation. It comprises means and autumn. When the N bit determination is completed, the control means stores the determination error in the capacitor array and divides the reference voltage by 2 ^N times, and subsequently determines subsequent bits until the determination of the M bit digital code is completed.

According to a fourth aspect of the present invention, there is provided a method for converting an analog signal into a digital code of M bits (M> N) using an N-bit analog-to-digital converter, wherein (a) the N-bit analog- Inputting the analog signal to a digital converter; (b) providing a reference voltage to the N-bit analog-to-digital converter; and (c) using the N-bit analog-to-digital converter. Determining the bits sequentially from the upper bits of the digital code of (d) and (d) if the N bit determination is completed by the N bit analog-to-digital converter, determining a determination error according to the N bit determination. Input to the digital converter and divide the reference voltage by 2 ^N times to provide the N-bit analog-to-digital converter, repeating step (c) until the determination of the M-bit is completed It includes the system.

Reference will now be made to the preferred embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals refer to like or similar components throughout.

5 illustrates a configuration of a SAR ADC that implements a resolution of 12 bits by using a 4-bit weighted-capacity SAR ADC as a unit block according to a preferred embodiment of the present invention.

Referring to FIG. 5, in accordance with a preferred embodiment of the present invention, a SAR ADC selectively selects a four bit weighted SAR ADC block including a capacitor array 100 and a comparator 200, and a plurality of reference voltages and analog signals. A group of switches S _R1 , S _R2 , S _R3 , S _R4 for input, and a voltage follower 300 for fetching the output voltage of the capacitor array 100 and reloading the capacitor array. ), A capacitor C _VX and a switch S _P1 , S _P2 .

First, a 4-bit weighted-capacity SAR ADC consists of a capacitor array containing five capacitors with binary weights of 2 ³ C, 2 ² C, 2 ¹ C, 2 ⁰ C, 2 ⁰ C. The capacitor array 100 is input from a group of switches S _R1 , S _R2 , S _R3 , S _R4 according to a digital code input to the switches S ₃ , S ₂ , S ₁ , S ₀ , S _-1 . It distributes the voltage and outputs it, and functions as a DAC. The capacitor of the capacitor array 100 has a double capacity of the capacitor as the bit increases based on the base capacity of the capacitor corresponding to the LSB, and the capacity of the capacitor corresponding to the MSB of the N-bit digital code is shown. 2 ^N C as shown.

One end of the capacitor array is connected in common and is connected to ground GND when the switch S _SP is turned on. The other end of the capacitor array is connected to five switches S ₃ , S ₂ , S ₁ , S ₀ , S _-1 that selectively interrupt each capacitor. The five switches S ₃ , S ₂ , S ₁ , S ₀ , S _-1 connect each capacitor to ground GND when a digital code of logic value 0 is input from a control means (not shown). When the digital code of logic value 1 is input from the control means, the other end of the capacitor array is commonly connected to one end of the group of switches S _R1 , S _R2 , S _R3 , S _R4 . The control signal input from the control means to the switches S ₃ , S ₂ , S ₁ , S ₀ , S _-1 corresponds to each bit of the N bit digital code, and the analog signal V _IN is digitally encoded for each bit. Controlled sequentially to code. The group of switches S _R1 , S _R2 , S _R3 and S _R4 are analog signals V _IN , reference voltage V _REF , 1/16 of the reference voltage (V _REF ), One of 1/256 (V _REF / 256) of the reference voltage is selectively output.

The output voltage V _X of the capacitor array output from the node to which one end of the capacitor array 100 is commonly connected is input to the non-inverting terminal (+) of the comparator 200, and the inverting terminal (-) of the comparator is grounded. Is connected to. Comparator 200 compares the output voltage (V _X ) and zero potential (0 V) of the capacitor array, and outputs a logic value of 1 if the output voltage (V _X ) of the capacitor array is greater than 0, and a logic value of less than 0. Output 0.

The output voltage of the voltage follower 300, an operational amplifier capacitor array 100 under the control of switches (S _P1) of which the outputs can be implemented by feeding back on any one of the input terminals, a pair of (OP Amp), as shown It receives (V _X ) and outputs it to the capacitor (C _VX ). Accordingly, the output voltage V _X of the capacitor array may be stored without loss in the capacitor C _VX . In addition, the voltage follower 300 may be controlled by a pair of switches S _P2 to change the voltage stored in the capacitor array by restoring (ie recharging) the voltage stored in the capacitor C _VX in the capacitor array. It is configured to.

FIG. 6 is an operation state diagram sequentially illustrating operation states of a 12-bit weighted-capacity SAR ADC implemented by reusing a 4-bit weighted-capacity SAR ADC unit block shown in FIG. 5 according to an embodiment of the present invention. FIG. 7 is a timing diagram illustrating a control signal input to each switch in time according to an operation state of the 12-bit weighted-capacitance SAR ADC shown in FIG. 6.

6 and 7, an operation of a 12-bit weighted capacity SAR ADC that reuses a 4-bit weighted capacity SAR ADC unit block will be described.

6 and 7, the sampling step T1, the holding step T2, and the first redistribution step T3 performing four-bit conversion coincide with the sampling step, holding step and redistribution step already described with reference to FIG. The digital code of the upper 4 bits corresponding to the analog signal is determined.

Cycles T4 and T5 are steps for changing the magnitude of the charge voltage and the reference voltage of the capacitor array for reuse of the 4-bit SAR ADC, the primary Vx fetch and primary Vx reload phases, respectively. It is called. In more detail, the switch S _P1 is turned on during the cycle T4 so that the output voltage V _X of the capacitor array is stored (charged) in the capacitor C _VX through the voltage follower 300. When the voltage stored in the capacitor C _VX in the cycle T4 is V _X4 , this corresponds to a determination error (or an approximation error) at the time when the 4-bit conversion is completed, and is derived from Equation 2 as described below. Can be. In Equation 3, {b ₁₁ , b ₁₀ , b ₉ , b ₈ } means a 4-bit digital code converted in the cycle T3.

Subsequently during the cycle T5, the switch S _P1 is turned off and the switch S _P2 is turned on. Accordingly, the voltage stored in the capacitor C _VX is applied to the capacitor array while being kept constant through the voltage follower 300. At this time, the switch S _{R2 that} is turned on in the cycles T3 and T4 is turned off to cut off the supply of the reference voltage V _REF , and the switches S ₃ , S ₂ , S ₁ , S ₀ , and S _-1 ) Is connected to ground (GND), so all capacitors in the capacitor array are recharged with the voltage output through the voltage follower (300).

Subsequently, a subsequent 4 bit conversion process is performed in cycle T6. In the cycle T6, the switch S _P2 is turned off to terminate the voltage recharging, and the switch S _R3 is turned on to apply the newly changed reference voltage VREF / 16 to the other end of the capacitor array. The conversion process for the subsequent four bits performs bit conversion through voltage redistribution as in the first redistribution step T3 described above, which is called a second redistribution step. However, in the second redistribution step, the charge voltage of the capacitor array is changed to V _X4 according to Equation 3, and the new reference voltage (V _REF '= V _{REF is} divided by dividing the previous reference voltage by 2 ⁴ times to set the conversion range. / 16) is different. Since the conversion range is set by the reference voltage, the 4-bit digital code is determined by the ratio of the voltage charged to the capacitor array and the new reference voltage (V _REF '). The reference voltage change may be performed by controlling the switch S _R3 .

When the second redistribution step (T6) is carried out is the conversion of the upper 8 bits is completed, to the conversion of the remaining 4 bits are secondary take-Vx and secondary V _X recharge step is carried out (T7, T8). The voltage V _X7 stored in the capacitor C _VX in the cycle T7 corresponds to a determination error when the 8-bit conversion is completed, and can be derived from Equations 2 and 3 as shown in Equation 4 below. In Equation 5, {b ₇ , b ₆ , b ₅ , b ₄ } means a 4-bit digital code converted in the cycle T6.

The third redistribution step T9 determines the next four bits following the eight bit conversion and is performed by the same method as the first and second redistribution steps T3 and T6 described above. However, in the third redistribution stage T9, the charging voltage of the capacitor array is changed to V _X7 according to Equation 4, and the previous reference voltage (V _REF '= V _REF / 16) is set to 2 ⁴ to set the conversion range. The point of distribution is changed to the new reference voltage V _REF "= V _REF '/ 16 = V _REF / 256. The reference voltage change may be performed by controlling the switch S _R4 .

Finally, the 12-bit conversion is completed after the third redistribution step (T9), and the output voltage (V _X9 ) of the capacitor array can be derived from Equation 4 as follows: {b ₃ , b ₂ , b ₁ , b ₀ } means a 4-bit digital code converted in the cycle T9.

Since the result according to Equation 5 corresponds to the case of N = 12 in Equation 1, it can be understood that a 12-bit SAR ADC is implemented by the configuration of FIG. 5.

FIG. 8 illustrates a circuit for canceling an offset voltage of an OP amplifier constituting the voltage follower 300 of FIG. 5 according to a preferred embodiment of the present invention, and a pair of switches S _P0 and a capacitor C _OC ).

If there is an offset in the OP amplifier, the output of the OP amplifier (V ₀ ) is added to the offset voltage (V _OFF ) to the voltage (V ₊ ) of the non-inverting input terminal. That is, V0 = V ₊ + V _OFF . Accordingly, since the offset voltage may be added to the output voltage of the capacitor array in the aforementioned Vx drawing step and stored in the capacitor C _VX , an error may occur in a subsequent bit determination step.

In order to solve this problem, after the redistribution stages T3 and T6 of FIG. 6 are completed, prior to the voltage storage stages T4 and T7, the switch S _P0 is turned ON to increase the offset voltage V _OFF of the OP amplifier by the capacitor C. FIG. _OC ). When the charging voltage of the capacitor C _OC is V _COC , V _COC = V _OFF . In the V _X withdrawal steps T4 and T7, when the switch S _P0 is turned off and the switch S _P1 is turned on, the non-inverting input voltage V ₊ is V ₊ = V _X -V _COC = V _X -V _OFF . At this time, the output voltage of the OP amplifier is V ₀ = V ₊ + V _OFF = (V _X -V _OFF ) + V _OFF = V _X. As a result, the voltage V _CVX charged to the capacitor C _VX is equal to the output voltage of the OP amplifier, so that V _CVX = V ₀ = V _X. In the V _X recharging stages T5 and T8, even when the switch S _P1 is turned off and the switch S _P2 is turned on, the voltage of the capacitor C _OC remains as it is, so that a voltage not including an offset is applied to the capacitor array. Recharged.

Meanwhile, when an 8-bit SAR ADC is implemented using a 4-bit weighted-capacity SAR ADC as a unit block, the 4-bit conversion is performed twice, and the storage and recharging of the capacitor array output voltage is performed once. In addition, when a 10-bit SAR ADC is implemented using a 4-bit weighted-capacity SAR ADC as a unit block, only 2 bits may be determined in the third distribution step of FIG. 6. Accordingly, it can be seen that the resolution of the weighted-capacity SAR ADC according to the present invention can be freely extended even if not a multiple of the resolution of the unit block.

Although the preferred embodiment according to the present invention has been described above, this is merely exemplary and those skilled in the art will understand that various modifications and equivalents thereof may be substituted therefrom. For example, those skilled in the art will appreciate that the reuse of SAR ADC unit blocks can be applied not only to weighted SAR ADCs but also to resistor array type SAR ADCs. In addition, in the case of reusing the N-bit ADC unit block, after the N-bit determination is completed, the determination of the next bit may be performed by inputting a determination error and changing the reference voltage. Therefore, the protection scope of the present invention should be defined by the following claims.

As described above, the present invention can easily implement a SAR ADC having a higher resolution by using a SAR ADC as a unit block, and has the advantage that the resolution can be expanded and expanded according to an application.

In addition, the present invention can reduce the number and area of the capacitors used in the SAR ADC to implement a high resolution SAR ADC in a small area. In addition, since the capacitance ratio of the capacitor corresponding to the MSB and the capacitor corresponding to the LSB is small, the capacitance ratio can be more accurately implemented. Accordingly, more accurate voltage distribution is possible, thereby improving conversion accuracy. When the SAR ADC is implemented in a fixed area, the capacity of the capacitor corresponding to the LSB can be designed larger than that of the conventional art, which is advantageous in terms of noise.

1 is a block diagram of a typical SAR ADC.

2 is a block diagram of a resistor array type SAR ADC according to the prior art.

3 is a time chart illustrating the conversion operation of a SAR ADC.

4 is a block diagram of a weighted-capacity SAR ADC according to the prior art.

5 is a schematic diagram of a 12-bit weighted-capacity SAR ADC that reuses a 4-bit SAR ADC in accordance with one embodiment of the present invention.

6 is an operational state diagram of a 12-bit weighted capacity SAR ADC in accordance with an embodiment of the present invention.

7 is a timing diagram of a switch control signal in a 12 bit weighted capacitive SAR ADC in accordance with an embodiment of the present invention.

8 is a schematic diagram of a voltage follower for canceling offset voltage in accordance with a preferred embodiment of the present invention.

Claims (13)

A serial ADC (SAR ADC) that reuses an N-bit progressive approximation analog-to-digital converter to convert an analog signal into a digital code of M bits (M> N). An N-bit axis for receiving the analog signal, distributing a reference voltage according to an N-bit digital code, comparing the input signal with an input signal, and sequentially determining the N-bit digital code corresponding to the input signal sequentially bit by bit according to the comparison result Approximate analog-to-digital converter, When the N bit digital code determination is completed by the N bit gradual approximation analog-to-digital converter, a determination error is input to the N bit sequential approximation analog to digital converter, and the reference voltage is divided by 2 ^N times, and the M bit Control means for controlling the N bit sequential approximation analog-to-digital converter to sequentially determine subsequent bits until the determination of the digital code is completed Sequential approximation analog-to-digital conversion device comprising a. The method of claim 1, wherein the N-bit difference approximation analog-to-digital converter, A capacitor array for storing the input signal, the voltage distribution means for distributing a reference voltage to a plurality of voltage levels in response to an N bit digital code, and outputting a difference between the divided voltage and a voltage stored in the capacitor array and, A comparator for comparing the divided voltage with an input signal according to the output of the voltage distribution means Sequential approximation analog-to-digital conversion device comprising a. The method of claim 2, Storage means for extracting and storing the determination error under the control of the control means and inputting the stored voltage to the capacitor array when the N bit determination is completed; Sequential approximation analog-to-digital conversion device further comprising a. The method of claim 2, Voltage follower, A capacitor for storing an output voltage of the voltage follower; First switching means for selectively connecting the input terminal of the voltage follower and the voltage distribution means, and simultaneously connecting the output terminal of the voltage follower and the capacitor; And second switching means for selectively connecting the capacitor and the input terminal of the voltage follower, and simultaneously connecting the output terminal of the voltage follower and the voltage distribution means. When the determination of the N bit is completed, the control means controls the first switching means to store the determination error in the capacitor, and controls the second switching means to store the voltage charged in the capacitor in the capacitor array. To save Sequential approximation analog-to-digital converter, characterized in that. The method of claim 4, wherein Offset correction means for feeding back the offset voltage output from the voltage follower to the voltage follower to remove the offset voltage from the voltage follower Sequential approximation analog-to-digital conversion device further comprising a. A successive approximation analog-to-digital converter (ADC) that converts analog signals into M-bit digital codes, An N-bit analog-to-digital converter receiving the analog signal and determining a digital code of N bits (N <M) according to a ratio of a reference voltage and an input signal; When the N-bit determination is completed by the analog-to-digital converter, input a determination error to the analog-to-digital converter and divide the reference voltage by 2 ^N times, and repeat the determination until the determination of the M-bit digital code is completed. Control means for controlling the analog-to-digital converter Sequential approximation analog-to-digital conversion device comprising a. The method of claim 6, Storage means for extracting and storing the determination error under control of the control means and inputting the stored voltage to the N-bit analog-to-digital converter when the N-bit determination is completed; Sequential approximation analog-to-digital conversion device further comprising a. As a C-weighted SAR ADC, a weighted-capacity approximation analog-to-digital converter that converts analog signals into M-bit digital codes, A weighted capacitor array for storing the inverted value of the analog signal, for dividing a reference voltage into a plurality of levels according to a digital code of N bits (N <M), and adding the divided voltage to the storage signal for output; A comparator for comparing the stored signal with a voltage divided according to the N bits of the digital code from an output of the capacitor array; The N-bit digital code is provided to the capacitor array, and according to the output of the comparator, a voltage divided by the capacitor array is sequentially approximated to the storage signal to obtain an N-bit digital code corresponding to the storage signal. Control means for sequentially determining bit by bit, The control means stores, upon completion of the N bit determination, store a determination error in the capacitor array and divide the reference voltage by 2 ^N times, and subsequently determine subsequent bits until the determination of the M bit digital code is completed. Weighted successive approximation analog-to-digital converter characterized in that. The method of claim 8, Storage means for extracting and storing the determination error under control of the control means and storing the stored voltage in the capacitor array when the N bit determination is completed; Weighted capacity difference approximation analog-to-digital conversion device further comprising a. The method of claim 8, Voltage follower, A capacitor for storing an output voltage of the voltage follower; First switching means for selectively connecting the input terminal of the voltage follower and the capacitor array and simultaneously connecting the output terminal of the voltage follower and the capacitor; And second switching means for selectively connecting the capacitor and an input terminal of the voltage follower and simultaneously connecting the output terminal of the voltage follower and the capacitor array. When the determination of the N bit is completed, the control means controls the first switching means to store the determination error in the capacitor, and controls the second switching means to store the voltage charged in the capacitor in the capacitor array. To save Weighted successive approximation analog-to-digital converter characterized in that. The method of claim 10, Offset correction means for feeding back the offset voltage output from the voltage follower to the voltage follower to remove the offset voltage from the voltage follower Weighted capacity difference approximation analog-to-digital conversion device further comprising a. A method of converting an analog signal into an M code (M> N) digital code using an N bit analog-to-digital converter, (a) inputting the analog signal to the N-bit analog-to-digital converter, (b) providing a reference voltage to the N-bit analog-to-digital converter; (c) using the N-bit analog-to-digital converter to sequentially determine bits from the higher bits of the M-bit digital code, (d) when the N bit determination is completed by the N bit analog-to-digital converter, input a determination error according to the N bit determination to the N-bit analog-to-digital converter and divide the reference voltage by 2 ^N times to divide the N. Providing the analog-to-digital converter of bits, and repeating step (c) until the determination of the M bits is completed Analog-digital conversion method comprising a. The method of claim 10, The N-bit analog-to-digital converter is a weighted-capacity approximation analog-to-digital converter that includes a capacitor array configured of binary weighted capacity. The step (c) includes storing the input analog signal in the capacitor array, Step (d) includes retrieving a determination error according to the N-bit determination and storing the retrieved determination error in the capacitor array. Analog-to-digital conversion method characterized in that.