JPS6161577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high precision digital-to-analog converter with linearity self-calibration.

Conventionally, there is a highly accurate digital-to-analog converter having the configuration shown in FIG. In FIG. 1, current sources B ₁ -B _o are driven by a reference voltage source A and supply current to current switches C ₁ -C _o .
The current switches C ₁ to _{C o} are controlled by digital signals at the input terminals D ₁ to _{D o} , and the current sources B ₁ to _{B o} are connected to the output terminal E according to “1” or “0” of this signal. A current is selected by C ₁ to _{Co and} flows. On this occasion,
In the case of a binary digital-to-analog converter, if the output current value of current source B ₁ is 1, then B ₂ is 1/
2, B ₃ is weighted to 1/4, and B _o is weighted to 1/2 ^n-1 .

By the way, the linearity in this type of digital-to-analog converter is determined by the current ratio of each current source B ₁ to B _o , and in order to achieve high accuracy, it is necessary to configure the current sources B ₁ to B _o . There is a need to improve the performance of components such as resistors and amplifiers in terms of temperature coefficients, changes over time, etc., but there are limits to this, and even if they could be achieved, high costs would be inevitable.

The present invention has been made in view of the above points, and by adding a linearity self-calibration function to a conventionally configured digital-to-analog converter, it does not require the use of components that are particularly superior in terms of temperature coefficient and change over time. The object of the present invention is to provide a digital-to-analog converter with extremely high linearity. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention in which the digital signal is a binary code (therefore, one digit is represented by one bit), and the bit is coded from the least significant bit (i.e., the first bit) to the most significant bit. This shows a case where current values for n bits up to the lower bit (ie, the n-th bit) are to be calibrated. A is a reference voltage source, D ₁ to _{D o} are digital signal input terminals, E is an analog signal output terminal, C ₁ to _{C o} are current switches, B ₁ to _{B o} are driven by the reference voltage source A, and each bit is A current source that supplies current according to the weight to the current switches C ₁ to C _o ,
These are basically the same as in the case of FIG. G
is a bit pattern generation circuit, H ₁ to _{H o} is a signal switching circuit that switches the output of bit pattern generation circuit G and input signals D ₁ to D _o and connects them to current switches C ₁ to C _o , C _o+1 is a The current switch B _o+1 is a current source that supplies C _o+1 with a current that matches the design value of the digital B _o for the least significant bit (LSB).
Also, is a switch that connects amplifier J to the output terminal during calibration, K is a synchronous detector, L is a level judgment circuit,
M is a correction data generation circuit, N ₁ to _No are current sources B ₁ to
A digital-to-analog converter corrects the current of B _o , F is a control circuit, and O is an input terminal for a calibration start command. In this case, since n bits from the 1st bit to the nth bit are to be calibrated,
n correction digitals expressed as N ₁ to _No
An analog converter is provided, but if the calibration target is generally m bits from the 1st bit to the m-th (1≦m≦n) bit, the digital-to-analog converter is provided with N ₁ to Only m pieces up to N _n are provided.

The operation of FIG. 2 is as follows. When operating as a normal digital-to-analog converter,
Switching circuit based on control of control circuit F
H ₁ to _{H o} apply digital signals from input terminals D ₁ to D _o to current switches C ₁ to _{C o} , and set each bit to "1",
An analog output signal is obtained at the output terminal E by intermittent currents of the current sources B ₁ to _{B o} in the "0" state.
At this time, switch I disconnects amplifier J from output terminal E. The self-calibration operation in this digital-to-analog converter begins when a start command is applied to the input terminal O. When the calibration start command is applied to the input terminal O, the control circuit F
Accordingly, the data switching circuits H _{1 -Ho} connect the output side of the bit pattern generation circuit G to the current switches C _{1 -Co} . Further, the output terminal E is connected to the input of the amplifier J through the switch I. The calibration operation will be explained below with reference to the time chart shown in FIG.

As shown in Figure 3, the calibration operation starts from the nth significant bit (LSB) (from the mth bit if the calibration target is from the 1st bit to the mth bit (1≦m≦n)). be done. The current of the current source B _o+1 added for calibration is adjusted to the design value of B _o , which is the LSB, and current switches C _o and C _o+1 are alternately switched on and off using the output of the bit pattern generation circuit G. As a result, a rectangular wave corresponding to the current difference between B _{o +1} and B _o is obtained at the output of the amplifier J, and by passing this through a synchronous detector K and a level judgment circuit L, the magnitude of B _o with respect to B _{o +1} is determined. A discrimination signal is obtained. According to this discrimination signal, the correction data generation circuit M increases or decreases the data to be applied to the correction D/A converter N _o so as to reduce the current value of B _o so that the current difference between B _{o +1} and B _o becomes small. When the current difference between B _o+1 and B _o becomes less than the threshold value preset in the level judgment circuit L, B _o
Finish the correction. This completes the calibration of the nth bit. According to FIG. 3, the output of the bit pattern generation circuit G is as follows: In the next calibration of the n-1th bit, the current switches C _o+1 and C _o are turned on at the same time, and at this time C _{o -1}
is turned off, then C _o+1 and C _o are turned off, C _o-1 is turned on, and this operation is repeated to obtain the sum of the currents of current sources B _o+1 and B _o and the current of B _o-1. Correction data is input from the correction data generation circuit M to No _-1 so that the (n-1)th bit is corrected. The above operations are sequentially performed for the higher order bits, and the calibration of the most significant first bit (MSB: Most Significant Bit) is completed, and all calibrations are completed.

When calibrated as described above, the linearity of the digital-to-analog converter is determined by the noise level of the calibration system, and the required performance of each current source B ₁ to _{B o} is stable for a short period of time until the next calibration. degree and correction D/
The change due to temperature coefficient and aging is smaller than the correction range of A converter N ₁ to _No , and the current source B ₁ is smaller than that of conventional digital-analog converters.
The required performance for ~B _o is greatly relaxed, and the linearity is improved.

Note that although the above embodiment is a case of binary code,
By changing the bit pattern generator, it can be applied to BCD codes or other codes.
Also, instead of calibrating all bits, it is possible to calibrate only a few important upper bits.

As described above, according to the present invention, there is an advantage that a digital-to-analog converter with extremely high linearity can be realized without using any components that are particularly excellent in terms of temperature coefficient and change over time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional digital-to-analog converter, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram showing the operation of FIG. 2. A...Reference voltage line, _B1 ~ _{B o+1} ...Current source, _C1 ~C _o
+1 ...Current switch, _D1 to _Do ...Digital signal input line, E...Analog output terminal, F...Control circuit, G...Bit pattern generation circuit, _H1 to _Ho ...Signal switching circuit, I...Current switch, J...Amplifier, K
...Synchronous detector, L...Level judgment circuit, M...Correction data generation circuit, _N1 to _No ...D/A converter for correction,
O...Calibration start command input terminal.

Claims (1)

[Claims] A digital-to-analog converter for converting the digital signal into an analog signal, comprising n digital-to-analog converters corresponding to each digit of an input digital signal consisting of 1n (>1) digits. , a calibration control means that inputs the output analog signal, generates correction data and a calibration control signal, and performs calibration control; a calibration analog signal source that generates a calibration analog signal value that matches the design value of the output analog signal of the converting section; and a calibration analog signal source that is provided corresponding to each digit of the input digital signal, and that is connected to the input digital signal and the calibration control means. a signal selection means for selecting one of the calibration control signals from and supplying the signal to the digital-to-analog converter; and to each of the m digital-to-analog converters from the most significant digit to the m-th digit. a correction digital-to-analog converter connected to the digital-to-analog converter for correcting output analog signal values of the m digital-to-analog converters based on correction data from the calibration control section; During control, the selection means selects a calibration control signal, and
First, in order to calibrate the output analog signal value from the m-th digit digital-to-analog conversion section, the calibration analog signal value from the calibration analog signal source and the output from the m-th digit digital-to-analog conversion section are used. The difference with the analog signal value is output as correction data of the m-th digit digital-to-analog converter to the correction digital-to-analog converter, and then the difference from the m-th digit digital-to-analog converter is outputted as correction data from the m-th digit digital-to-analog converter. To calibrate the output analog signal value,
From the digit to the least significant digit (i.e. mth, m+1,..., n
The result of addition of all the analog signal values from the digital-to-analog converter up to (digit) and the analog signal value for calibration from the analog signal source for calibration, and the output analog from the digital-to-analog converter for the m-1st digit. Outputting the difference with the signal value to the digital-to-analog converter for correction as correction data of the m-1st digit digital-to-analog converter;
The same operation is repeated below, and finally, in order to calibrate the output analog signal value from the digital-to-analog converter of the most significant digit (i.e., the first digit),
up to the least significant digit of the second digit (i.e., 2nd, 3rd, etc.)
m-1, m,..., n digits)
The difference between the addition result of the analog signal from the analog converter and the calibration analog signal from the calibration analog signal source and the output analog signal value from the most significant digit digital to analog converter is calculated as the most significant digit digital. A digital-to-analog converter, characterized in that the digital-to-analog converter outputs the correction data to the digital-to-analog converter for correction as correction data for the analog converter.