CN114650061A

CN114650061A - Integrated circuit, digital-to-analog converter and driving method thereof

Info

Publication number: CN114650061A
Application number: CN202011515687.4A
Authority: CN
Inventors: 满雪成
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2022-06-21

Abstract

The invention discloses an integrated circuit, a digital-to-analog converter and a driving method thereof, wherein the circuit comprises: a first section having a plurality of first current paths forming binary weighted weight values in a digital-to-analog converter; a second section having a plurality of second current paths forming binary weighted weight values in the digital-to-analog converter; and a third part having at least one third current path forming an additional binary weighted weight value in the digital-to-analog converter so as to adjust the sum of the weight values corresponding to the first part and the second part, wherein each of the plurality of first current paths, the plurality of second current paths, and the at least one third current path is switchable between the first node and the second node, and the weight value corresponding to each of the at least one third current path is less than a preset threshold. The invention realizes digital calibration of the digital-to-analog converter, and simultaneously reduces the requirements of the chip on area and the number of switches required to be driven.

Description

Integrated circuit, digital-to-analog converter and driving method thereof

Technical Field

The invention relates to the technical field of digital-to-analog converters, in particular to an integrated circuit, a digital-to-analog converter and a driving method thereof.

Background

In the related art, a high-precision Digital-to-Analog Converter (DAC) generally adopts an R-2R ladder resistor network structure. Because the number of the resistors of the DAC of the R-2R ladder resistance network structure is small, the output impedance is small, and the thermal noise generated by the resistors is small, the R-2R ladder resistance network is further widely applied to the fields of industrial process control, automatic test systems, data acquisition systems and the like.

Fig. 1a and 1b illustrate schematic diagrams of an R-2R ladder resistance network structure according to the related art, in which resistance values of resistors are fixed to two kinds of R and 2R as shown in fig. 1 a. Theoretically, every time the precision of 1 bit (bit) is increased, only one resistor and one switch S are needed to be added to R and 2R respectively, and the area of the resistor network cannot increase exponentially along with the increase of the precision. This structure only needs to control the switch 2, which is connected to the first reference voltage VREF1 and the second reference voltage VREF2, per 2R according to a digital signal, and can obtain:

where VOUT represents the output voltage and D [ A-1:0] represents the input A-bit digital signal.

The R-2R dac shown in fig. 1a can be equivalent to a voltage source VOUT connected in series with an output resistor R (as shown in fig. 1 b). The DAC structure continues to increase the number of Bits at the low-Significant bit (LSB) end, the overall output resistance of the DAC cannot be changed, and the important advantage that the precision of the R-2R DAC structure is easy to expand is achieved.

The output precision of the structure is mainly limited by the matching precision of the resistor. When the resistance values of the resistors are not completely the same due to processes, photolithography, and the like, a deviation of the output voltage from the ideal voltage may be caused. The deviation is mainly characterized by two indexes, Differential-Non-Linearity (DNL) and Integral-Non-Linearity (INL). As the output accuracy of the DAC increases, the mismatch requirement for the Most-Significant-bit (MSB) resistance (e.g., D [ a-1]) also increases, resulting in poor performance of the structure at high accuracy.

An example of an existing trimming method is laser trimming, where individual components of a manufacturing apparatus are physically trimmed using a laser. Laser trimming is a relatively slow and expensive process that must be performed prior to packaging the DAC. Therefore, there is a limit to the accuracy thereof due to the subsequent stress generated by the components during the assembly process and the cost burden caused by performing laser trimming.

Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides an integrated circuit, a digital-to-analog converter and a driving method thereof, which can reduce the requirements of area and the number of switches to be driven on a chip while realizing digital calibration of the digital-to-analog converter.

According to a first aspect of the present disclosure, there is provided a digital-to-analog converter comprising: the first part is provided with a plurality of first current paths forming binary weighted weight values in the digital-to-analog converter, and the weight value corresponding to each current path in the plurality of first current paths is different;

the second part is connected with the first part and is provided with a plurality of second current paths forming binary weighted weight values in the digital-to-analog converter, and the weight values corresponding to each current path in the plurality of second current paths are the same; and

a third portion connected to the first portion and the second portion and having at least one third current path forming an additional binary weighted weight value in the digital-to-analog converter for adjusting a sum of the weight values corresponding to the first portion and the second portion,

each of the plurality of first current paths, the plurality of second current paths, and the at least one third current path is switchable between a first node and a second node, and a weight value corresponding to each of the at least one third current path is smaller than a preset threshold.

Optionally, a minimum weight value of a plurality of weight values corresponding to the plurality of first current paths corresponds to one least significant bit of the digital-to-analog converter.

Optionally, the first part further comprises:

a plurality of fourth current paths for forming binary weighted weight values in the digital-to-analog converter,

the weight value corresponding to each current path in the fourth current paths is different and is smaller than the minimum weight value in the weight values corresponding to the first current paths.

Optionally, the first, second and third portions are connected together by a shared connection to an output node of the digital to analog converter.

Optionally, the first node is connected to a first reference voltage input and the second node is connected to a second reference voltage input.

Optionally, any one of the first current paths, any one of the second current paths, and any one of the fourth current paths has a resistor with a resistance of 2R, and the at least one third current path has a resistor with a resistance of m × 2R,

wherein R is a positive number, m is a positive integer, and m is equal to a proportional value of a weight value corresponding to any one of the second current paths and a weight value corresponding to the at least one third current path.

Optionally, the digital-to-analog converter further comprises:

a controller configured to calibrate and compensate an initial digital-to-analog converter code received by the digital-to-analog converter, and to control switching of each current path in the digital-to-analog converter between the first node and the second node based on the calibrated and compensated digital-to-analog converter code, so that an output voltage of the digital-to-analog converter normally steps according to the initial digital-to-analog converter code.

Optionally, the controller comprises:

a first decoder for decoding and grouping the initial DAC encoding to produce a segmented encoding corresponding to the second portion, a higher order encoding corresponding to the first portion having a weight value greater than a threshold, and a lower order encoding corresponding to the first portion having a weight value less than a threshold;

the segmented coding correction searching module is connected with the first decoder and used for searching and obtaining pre-stored first calibration information according to the segmented coding;

the high-order coding correction searching module is connected with the first decoder and used for searching and obtaining pre-stored second calibration information according to the high-order coding;

a system gain error calculation module for obtaining system gain error compensation information from the initial digital-to-analog converter encoding calculation to compensate for changes in the contributions to the output voltage of the first and second portions caused by the at least one third current path;

a random gain error calculation module, configured to calculate and obtain random gain error compensation information according to the initial dac code and pre-stored random gain error information, so as to compensate for a random gain error caused by the first calibration information and the second calibration information;

an adder module, configured to obtain the calibrated and compensated dac code according to the first calibration information, the second calibration information, the system gain error compensation information, the random gain error compensation information, and the low-order coding operation;

a second decoder for decoding and grouping the calibrated and compensated digital-to-analog converter encoding to produce a first encoding, a second encoding driving the plurality of fourth current paths, and a third encoding driving the at least one third current path,

wherein the first encoding and the high-order encoding are used to jointly enable driving of the plurality of first current paths, and the segment encoding is used to enable driving of the plurality of second current paths.

Optionally, the digital-to-analog converter further comprises:

a first memory for storing the random gain error information.

Optionally, the digital-to-analog converter further comprises:

a second memory for storing the first calibration information;

a third memory for storing the second calibration information.

Optionally, the digital-to-analog converter further comprises:

a first lookup table for storing the first calibration information;

a second lookup table for storing the second calibration information.

According to a second aspect of the present disclosure, there is provided a driving method of a digital-to-analog converter having a first portion including a plurality of first current paths forming binary-weighted weight values in the digital-to-analog converter, a second portion including a plurality of second current paths having binary-weighted weight values in the digital-to-analog converter, and a third portion having at least one third current path forming additional binary-weighted weight values in the digital-to-analog converter so as to adjust a sum of the weight values corresponding to the first portion and the second portion, wherein each of the plurality of first current paths, the plurality of second current paths, and the at least one third current path is switchable between a first node and a second node, and a weight value corresponding to each of the at least one third current path is less than a preset value A threshold, the method comprising:

receiving an initial digital-to-analog converter code;

compensating and calibrating the initial digital-to-analog converter code to obtain a calibrated and compensated digital-to-analog converter code;

driving switches located on each current path of the digital-to-analog converter based on the calibrated and compensated digital-to-analog converter code.

Optionally, compensating and calibrating the initial digital-to-analog converter encoding comprises:

searching and obtaining first calibration information based on the segmented codes in the initial digital-to-analog converter codes;

searching and obtaining second calibration information based on the high-order code in the initial digital-to-analog converter code;

obtaining system gain error compensation information based on the initial digital-to-analog converter coding calculation;

obtaining random gain error compensation information based on the initial digital-to-analog converter code and random gain error calculation;

adjusting the initial digital-to-analog converter encoding based at least in part on the first calibration information, the second calibration information, the system gain error compensation information, and the random gain error compensation information.

Optionally, the weight value corresponding to each of the plurality of first current paths is different, and the weight value corresponding to each of the plurality of second current paths is the same.

Optionally, the first part further comprises: a plurality of fourth current paths for forming binary weighted weight values in the digital-to-analog converter,

According to a third aspect of the present disclosure, there is provided an integrated circuit comprising: such as the digital-to-analog converter described above.

The invention has the beneficial effects that: the integrated circuit, the digital-to-analog converter and the driving method thereof have the advantages that the third part with at least one third current path is added on the basis of the circuit structure of the original digital-to-analog converter, and the at least one third current path also contributes to output voltage to a certain extent, so that the full-scale range value of the current paths of the first part and the second part in the original digital-to-analog converter under the condition that the driving signal is that the digital-to-analog converter codes are all '1' is reduced, an interval capable of compensating mismatch errors of the digital-to-analog converter is provided, and digital calibration of the digital-to-analog converter is facilitated. Meanwhile, according to the digital-to-analog converter, only one current path is added in the digital-to-analog converter, namely, digital calibration of the digital-to-analog converter can be realized only by additionally adding one resistor and one switch in a digital-to-analog conversion chip, the requirement of the digital-to-analog conversion chip on the area is reduced, the number of the switches needing to be driven is reduced, the driving time of the chip can be reduced, and the driving efficiency is further improved. And compared with the traditional laser trimming, the digital calibration in the disclosure also ensures the accuracy of trimming the digital-to-analog converter.

On the other hand, the fourth current paths with lower weights are also provided in the first part in the present disclosure, providing a smaller operation step size in digital calibration, thereby reducing the differential non-linearity error and the integral non-linearity error of the digital-to-analog converter.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIGS. 1a and 1b show schematic diagrams of an R-2R ladder resistance network structure according to the related art;

FIG. 2a shows a schematic diagram of a digital-to-analog converter according to the related art;

FIG. 2b shows a schematic diagram of the DAC trimming of FIG. 2 a;

fig. 3 shows a schematic diagram of another digital-to-analog converter according to the related art;

fig. 4 is a schematic diagram illustrating a structure of a digital-to-analog converter provided in accordance with an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a controller for driving a digital-to-analog converter according to an embodiment of the disclosure;

FIG. 6 is a diagram illustrating the relationship between the system gain error compensation information and the DAC coding without considering the mismatch for the DAC provided according to the embodiment of the present disclosure;

FIGS. 7a and 7b show simulated schematic diagrams of the integral non-linearity error and the derivative non-linearity error of a digital to analog converter, respectively, without taking mismatch into account;

fig. 8 is a schematic diagram illustrating a possible existence interval of calibration information of a digital-to-analog converter according to the DAC encoding input provided by the embodiment of the disclosure;

fig. 9a and 9b show simulated schematic diagrams of the integral non-linearity error and the differential non-linearity error, respectively, of a digital-to-analog converter under consideration of mismatch and without calibration;

10a and 10b show simulated schematic diagrams of the integrated non-linearity error and the differential non-linearity error, respectively, of a digital to analog converter calibrated to take into account mismatch;

fig. 11 shows a flow chart of a driving method of a digital-to-analog converter provided according to an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The present invention will be described in detail below with reference to the accompanying drawings.

It should be noted that, for ease of understanding and explanation, the description is only exemplified by a 16-bit digital-to-analog converter (DAC) in this document, but it should be understood that, in practice, the disclosure herein can be applied to a DAC with any resolution.

Referring to fig. 2a, fig. 2a shows a schematic diagram of a digital-to-analog converter according to the related art.

It is known that component variations during integrated circuit fabrication can cause resistance mismatches. Thus, in an ideal R-2R ladder (or R2R ladder for ease of labeling), all resistors have exactly one arbitrary resistor element R, or two arbitrary resistor units 2R. Where a 2R resistance can be easily formed by two R resistances in series so that the nominally formed resistor during manufacture is equal to each other resistance of the DAC.

However, this design of R2R inherently results in some resistances (closest to the output) being weighted more strongly than resistances further away from the output. This increased weight and hence improved need for matching high accuracy results in the formation of a segmented design in which the DAC can be considered to consist of two parts, an interconnected R2R part and a temperature code part, the R2R part being an R2R part with alternating R and 2R resistances, wherein the weight of the 2R tap part (each branch in which the 2R tap part is located corresponds to a current path contributing to the output voltage Vout) is from 1LSB (herein, 1LSB is a unit LSB and 1LSB 1/2 is a unit LSB)¹⁶Where 16 is the number of bits of the DAC) to 2048LSB are varied by a multiple of 2, corresponding to a 12-bit digital-to-analog converter. The temperature code part is a temperature code part formed by connecting 2R resistors in parallel, the total number of the temperature code part is 15 branches, the weight of each branch is equivalent to the sum of the R2R parts, the temperature code part additionally provides 4-bit resolution, and the temperature code part and the R2R part form a 16-bit digital-to-analog converter. Compared with a 16-bit DAC consisting of only R-2R parts, the high-order DAC consisting of temperature codes has the advantages that the maximum weight of the 2R part is reduced from 32768 LSBs to 4096 LSBs, so that the matching requirement of the resistors is reduced, meanwhile, the output impedance of the DAC is reduced from 2R to 2R/16, the corresponding impedance of R and 2R is improved under the condition that the output impedance is kept constant, and the requirements on routing resistance and layout are reduced.

A disadvantage of the R2R ladder DAC (abbreviated as R2R DAC) is that mismatches between the resistances can affect both INL and DNL. Therefore, the R2R DAC with more than 12 bits needs to be calibrated before being used. The conventional method is to perform laser trimming on the R2R resistor with higher weight and the 2R resistor of the temperature code part, as shown in fig. 2b, and fig. 2b shows a schematic diagram of the digital-to-analog converter in fig. 2a during trimming. The resistance of the laser trimming section and the resistance of R2R, which are made up of different sized resistors, are used to provide fine trimming operation, which may involve the risk of parameter drift over long periods of use. The output of the DAC needs to be tested synchronously and repeatedly for many times during laser trimming, and the high precision and high linearity requirements of the DAC greatly prolong the time needed by the DAC test. Meanwhile, laser trimming is performed before packaging, and the yield of the chip is further influenced by the offset caused by packaging stress. Both from a cost standpoint and from a DAC performance standpoint, a post-package trimming method is desired that takes full advantage of the powerful computational power provided by digital circuits.

Fig. 3 is a schematic diagram of another digital-to-analog converter according to the related art, in which the DAC structure can be modified by digital signals after packaging.

As shown in fig. 3, the DAC is based on the DAC structure shown in fig. 2a, and one or more branches in the temperature code part are replaced by the same design as that in the R2R part (denoted as the second R2R part), and further calibration information of the DAC (denoted as DAC in this document)_ADJ) Providing an interval for existence. That is, the temperature code portion of the DAC in fig. 3 includes a first temperature code portion and a second R2R portion.

In the circuit structure of the DAC, each branch of the 2R resistor corresponds to a current path, and each current path can be connected to a first reference voltage V through a switch S controlled by a digital signal_REF1Or a second reference voltage V_REF2And each current path has a certain weight. Herein, a current path weighted more than a predetermined threshold is denoted as DAC_HThe current path weighted less than or equal to the predetermined threshold is denoted as DAC_LThe total current path in the DAC is denoted as DAC_V. Meanwhile, digital codes received by the DAC (such as binary codes, DAC codes for short) can be coded (denoted as DAC codes in the text)_C) Also for division into DACs_CHAnd DAC_CL. In general, resistance mismatch in a DAC can be viewed as being caused by the DAC_HDue to resistance mismatch in part of the current path, and the DAC in the DAC_LPart of the current path is considered ideal.

Assuming that the predetermined threshold is 128LSB, in the DAC shown in FIG. 3, the DAC thereof_CHCorrespond toIn input DAC coding [15:8 ]]Section of, DAC_HAnd DAC_CHOne-to-one correspondence is realized; DAC thereof_CLCorresponding to [7: 0] in the input DAC encoding]Part of, DAC_LAnd DAC_CLAnd correspond to each other. That is, DAC_CLThe corresponding weight interval is (0-255) × LSB, and the smallest branch in the second R2R2 part and the branch with the weight less than 128LSB in the R2R part form the DAC_L. Wherein, the branch whose weight is less than 128LSB in the R2R part corresponds to the weight interval of (0-255) LSB, and the smallest branch in the second R2R part can provide [ -128,0,128 ] LSB according to the state of each branch]LSB has 3 selectable weight outputs, therefore DAC_LThe corresponding weight interval is (0-255) LSB + [ -128,0,128]LSB (-128 to +383) LSB. It can be seen that the DAC in fig. 3 has extra trimming intervals (-128 to +128) LSB relative to the DAC in fig. 2a, and the trimming term DAC of the DAC can be provided_ADJTrimming is carried out as long as certain DAC is met_ADJSetting, final DAC_VThis is ideal.

However, the DAC shown in fig. 3 requires two approximately identical R2R parts, which greatly increases the chip area and the number of switches S to be driven, and thus requires a high analog circuit. At the same time, there are limited solutions available for different situations. Therefore, the present disclosure proposes another scheme for trimming and calibrating the DAC by using a digital signal, which is described in detail below, to overcome this drawback.

as shown in fig. 4, in the present disclosure, the DAC includes a first part (corresponding to a part R2R in the DAC), a second part (corresponding to a temperature code part in the DAC), and a third part (which is a part additionally provided in the DAC). The first, second and third portions are all commonly connected to the output node of the DAC to provide a respective contribution to the output voltage Vout.

The first portion has a plurality of first current paths 200 forming binary weighted weight values in the DAC, and the weight value corresponding to each of the plurality of first current paths 200 is different (the weight values corresponding to the plurality of first current paths 200 are, for example, 1LSB, 2LSB, 4LSB, · n., (n/2) LSB, n LSB from low to high, where n is a positive integer).

The second portion is connected to the first portion, and has a plurality of second current paths 300 forming binary weighted weight values in the DAC, and the weight values corresponding to each of the plurality of second current paths 300 are the same (for example, 2 nlbs for each of the plurality of second current paths 300).

The third part is connected to the first and second parts and has at least one third current path 400 forming an additional binary weighted weight value in the DAC for adjusting the sum of the weight values corresponding to the first and second parts. The at least one third current path 400 has a corresponding weight value of, for example, (2n/m) LSB, where m is a positive integer. And when the number of the third current paths is two or more, the weight values corresponding to the two or more third current paths may be the same or different, for example, the m values corresponding to each third current path are different. In this embodiment, to illustrate only one third current path, the principle is basically the same for two or more third current paths.

Further, each of the plurality of first current paths 200, the plurality of second current paths 300, and the at least one third current path 400 may be switched between the first node and the second node by the switch S, and a weight value corresponding to each of the at least one third current path 400 is smaller than a preset threshold. Wherein the first node is connected to a first reference voltage V_REF1An input terminal, a second node connected to a second reference voltage V_REF2An input terminal.

Optionally, in one embodiment of the present disclosure, the weight value corresponding to each of the at least one third current path 400 may be equal to one of the plurality of weight values corresponding to the plurality of first current paths 200, so that subsequent encoding and decoding operations may be facilitated. However, in other embodiments of the present disclosure, the weight value corresponding to each of the at least one third current path 400 may also be other values, which is not specifically limited by the present disclosure.

In this embodiment, a minimum weight value of the plurality of weight values corresponding to the plurality of first current paths 200 corresponds to one least significant bit, i.e., 1LSB, of the DAC.

In this embodiment, the first part further includes: the plurality of fourth current paths 100 have weight values forming binary weighting in the DAC, and the weight value corresponding to each of the plurality of fourth current paths 100 is different (the weight values corresponding to the plurality of fourth current paths 100 are from high to low, such as (1/2) LSB, (1/k) LSB, where k is a positive integer), and each weight value is smaller than the smallest weight value of the weight values corresponding to the plurality of first current paths 200. Meanwhile, the sum of the weight values respectively corresponding to the plurality of fourth current paths 100 and the plurality of first current paths 200 of the first part of the DAC is equal to the weight value corresponding to any one second current path in the second part of the DAC. In the present disclosure, the LSB, which is the smallest weight value (1/k) among the plurality of weight values corresponding to the plurality of fourth current paths, corresponds to the smallest resolution of the DAC according to the present disclosure.

In the DAC of the present disclosure, each of the first current paths 200, the second current paths 300, and the fourth current paths 100 has a resistor with a resistance of 2R, but in the at least one third current path 400, each of the third current paths has a resistor with a resistance of m × 2R (where, referring to the foregoing description, when the number of the third current paths is two or more, m values corresponding to the two or more third current paths may be the same or different). Where R is a positive number, m is a positive integer, and m is equal to a ratio of a weight value corresponding to any one of the second current paths 300 to a weight value corresponding to at least one third current path. That is, based on the DAC structure of the present disclosure, in practical applications, if a different weight value is set for at least one third current path 400, the at least one third current path 400 can be implemented by only changing the resistance value of the resistor, so that the number of solutions that can be selected in different situations is effectively increased. Meanwhile, in the embodiment of the disclosure, only one current path is added in the DAC, that is, only one resistor and one switch S are additionally added in the DAC chip to realize digital calibration of the DAC, so that the area requirement of the DAC chip is reduced, the number of switches to be driven is reduced, the driving time of the chip can be reduced, and the driving efficiency is further improved.

In this embodiment, also taking a 16-bit DAC as an example, and taking only 1 third current path 400 as an example for description, in the 16-bit DAC, a first portion thereof includes, for example, 3 fourth

current paths

100 and 12 first current paths 200 for providing 12 less significant bits of the 16-bit DAC, and each current path in the first portion can be connected to an adjacent current path through a resistor R. The second part of which for example comprises 15 second current paths 300, thereby providing the 4 more significant bits of the 16-bit DAC. The third section includes 1 third current path 400 for providing additional weight for the 16-bit DAC to assist the first section in trimming calibration of the DAC.

In the DAC of this embodiment, the first and second parts are segmented by a resistor R closest to the output node. And the R2R ladder network of the first section operates as a sequence of potential dividers such that the 12 least significant bits are weighted in their contribution to the output voltage Vout. In contrast, the plurality of second current paths 300 of the second portion are all directly connected to the output node, and therefore, the contribution of each of the plurality of second current paths 300 to the output voltage Vout is the same. Thus, in the example shown, its 3 current paths 100 are respectively configured to provide an effective weight of 1/2 units, an effective weight of 1/4 units, and an effective weight of 1/4 units, namely 1LSB/2, 1LSB/4, and 1 LSB/4; the 12 first current paths 200 are respectively used to provide 1 unit effective weight, 2 units effective weight, 4 units effective weight, and 2048 units effective weight, i.e. 2⁰LSB～2¹¹The weight of the LSB is weighted. Each of the 15 second current paths 300 of the second portion thereof may provide 2¹²The weight of the LSB. Further, it is possible to prevent the occurrence of,the DAC realizes 16-bit digital-to-analog conversion by the first part and the second part together.

Meanwhile, the plurality of first current paths 200, the plurality of second current paths 300, and the plurality of fourth current paths 100 in the DAC each include a 2R resistor and a switch S, and each current path in the DAC may be at the first reference voltage V_REF1And a second reference voltage V_REF2To switch between. In general, if the first reference voltage V_REF1Is less than the second reference voltage V_REF2Then each current path in the 16-bit DAC is connected to a first reference voltage V when the code received by the respective switch is a logic 0_REF1Connected to a second reference voltage V when the code received by the respective switch is logic 1_REF2。

Illustratively, the DAC in the present disclosure may be divided into a core portion (corresponding to including the plurality of first current paths 200 and the plurality of second current paths 300), an AUX portion (corresponding to including the third current path 400), and a SUB portion (corresponding to including the plurality of fourth current paths 100). If 128LSB, which is an effective weight of 128 units, is also used as the preset threshold of the weight value of each current path, and according to the aforementioned concept, the core portion of the DAC in this embodiment can be divided into DACs_H(current paths with weights greater than 128 LSB) and DAC_L(current paths with corresponding weights less than or equal to 128 LSB) and respectively encoded by the encoding DACs_CHControlling a DAC_HBy encoding the DAC_CLControlling a DAC_L。

It can be seen that conventionally, the unit effective weight of a 16-bit DAC, i.e., 1LSB 1/2¹⁶. In the present disclosure, however, the unit effective weight of the 16-bit DAC, i.e., 1LSB, becomes equal to 1/(2) due to the additional weight value provided by the AUX section¹⁶+128). That is, the unit effective weight in the present disclosure becomes smaller, that is, the contribution of any current path in the DAC to the output voltage Vout becomes smaller under the same connection structure, for example, the full-scale value of the core portion of the DAC becomes smaller in the case where the received code (i.e., the initial DAC code received by the DAC) is all logic 1. Based on this principle, the DAC in the present disclosure can provide the trimming term DAC based on the 128LSB extra weight provided by the AUX part_ADJRepair ofAnd adjusting the interval. It is understood that the 128LSB is merely exemplary, and different values may be selected according to different situations in practical applications.

Based on the above-described DAC architecture in this disclosure, (1) without taking mismatch and calibration into account

DAC_V＝DAC_CH+DAC_L,A+DAC_SUB,A+DAC_AUX,A；

DAC_L,A+DAC_SUB,A+DAC_AUX,A＝DAC_ADJ+DAC_CL+SYS_GN(DAC_C)。

Wherein, the DAC_VIs the actual DAC output; DAC_L,ACodes corresponding to current branches with weight values lower than a preset threshold value in the DAC core part; DAC_SUB,ACoding corresponding to the current branch of the SUB part; DAC_AUX,AAnd coding corresponding to the current branch of the AUX part.

DAC due to mismatch and calibration considerations _ADJ0, and further having:

DAC_L,A+DAC_SUB,A+DAC_AUX,A＝DAC_CL+SYS_GN(DAC_C)；

wherein SYS _ GN (DAC)_C) Is a DAC_CTo compensate for full scale variations of the DAC core.

That is, based on the DAC architecture of the embodiments of the present disclosure, it is possible to set SYS _ GN (DAC) without considering mismatch and calibration of the DAC_C) As system gain error correction information of the DAC code received by the DAC, and thereby compensate for full-scale variations of the DAC core. At the same time, the system gain error correction information is SYS _ GN (DAC)_C) And the initial DAC codes received by the DAC and the corresponding DAC structures can be obtained through corresponding calculation. Referring to fig. 6, fig. 6 is a schematic diagram illustrating a relationship between system gain error compensation information and DAC coding of a DAC without considering mismatch according to an embodiment of the present disclosure, and as can be seen from fig. 6, as a DAC coding sequence received by the DAC increases, corresponding gain error correction information, i.e., SYS _ GN (DAC _ GN), is obtained_C) And is increasing. In DAC programmingSYS _ GN (DAC) when the code sequence is "all 0_C) Also 0, SYS _ GN (DAC) when the DAC encoding sequence is "all 1_C) The maximum set value is reached, which in this embodiment corresponds to 128 LSB. For example, conventionally, when the DAC codes all 1, the corresponding output voltage Vout is the maximum value V_REF2For example, 5V; however, in the DAC structure of the present disclosure, due to the extra weighting weight of 128LSB provided by the AUX portion, the corresponding code of the core portion (i.e. corresponding to the conventional whole DAC portion) in the DAC structure of the present disclosure can only reach a voltage value of, for example, 4.9V at maximum corresponding to the output voltage Vout when the code is "all 1", and at this time, it is necessary that the DAC code corresponding to the AUX portion in the DAC is also "logic 1", so as to compensate for the full-scale of the DAC core portion, and make the output voltage Vout reach a maximum value of 5V. For another example, conventionally, the DAC code is "1", for example, when corresponding to DAC code 12345, the corresponding output voltage Vout is 3V, for example; however, due to the extra weighting weight of 128LSB provided by the AUX part in the DAC structure of the present disclosure, the corresponding code of the core part (i.e. corresponding to the conventional whole DAC part) in the DAC structure of the present disclosure can only reach the voltage value of, for example, 2.9V corresponding to the output voltage Vout when corresponding to the code 12345, and at this time, the AUX part in the DAC is required to provide, for example, the system gain error correction of 55LSB so as to compensate for the DAC core part, so that the output voltage Vout reaches 3V. At this time, according to the system calculation result, the DAC code corresponding to the AUX portion is set to "logic 1", and the DAC code corresponding to the DAC core portion is changed accordingly to reduce the contribution of the corresponding (128LSB-55LSB), so that the output voltage Vout finally reaches 3V. The other same principle is adopted.

If the output of the DAC in the present disclosure is analyzed without considering the mismatch and calibration of the DAC, a simulation diagram of the integral nonlinear error and the differential nonlinear error of the digital-to-analog converter without considering the mismatch can be obtained as shown in fig. 7a and 7b, respectively. Referring to fig. 7a and 7b, since the integral non-linear error INL and the differential non-linear error DNL of the DAC are mainly limited by the minimum operation step size of the DAC, while the DAC of the present disclosure is provided with a SUB portion to provide a smaller operation step size of the DAC, the DAC structure of the present disclosure can finally realize that the integral non-linear error INL and the differential non-linear error DNL of the DAC are both within an acceptable range of ± 0.3LSB, regardless of the mismatch and calibration of the DAC. It should be understood that in practice, the minimum operation compensation of the DAC required to be expanded can be reasonably selected according to the requirements of specific applications by comprehensively considering the area requirements of the chip and the requirements of the INL and the DNL, and the disclosure is not limited thereto.

(2) In the case of taking into account mismatch and calibration, there are

DAC_L,A+DAC_SUB,A+DAC_AUX,A＝DAC_CL+SYS_GN(DAC_C)+GN_ERR(DAC_C)+DAC_ADJ(DAC_CH)；

DAC_V＝DAC_CH+DAC_L,A+DAC_SUB,A+DAC_AUX,A；

Wherein GN _ ERR (DAC)_C) For random gain error calibration information, DAC_ADJ(DAC_CH) For the DAC in the core part of the DAC_HPortions of corresponding encoded calibration information.

If mismatch and calibration are considered, calibration information DAC needs to be introduced_ADJTo correct for DAC codes received by the DAC to correct for errors in the DAC structure due to mismatches in resistance, etc. In addition, in the present disclosure, it can be assumed that all the resistors corresponding to the temperature code portion 300 in the DAC core portion have mismatch and need to be calibrated; all or part of resistors corresponding to the R2R MSB part with the weight larger than a preset threshold in the R2R part 200 in the DAC core part are mismatched, and calibration is needed; and the resistance corresponding to the R2R LSB portion of the R2R portion 200 in the DAC core portion, which corresponds to a weight less than or equal to the preset threshold, has no mismatch and requires no calibration. Further, DAC_ADJI.e. to DAC_ADJ(DAC_CH)。

In this disclosure, a DAC in a DAC architecture_L-DAC_CL-SYS_GN(DAC_C) Providing available calibration information DAC_ADJThe interval in which it exists. Wherein here the DAC_LCorresponding to all codes corresponding to the part of the DAC structure with the weight value less than or equal to the preset threshold value, such as 128LSB, and the corresponding interval is (0-255) LSB+[0,128]LSB is (0-353) LSB, and DAC_CLThe corresponding interval is (0 ~ 255) LSB, SYS _ GN (DAC)_C) The corresponding interval is + [0,128 ]]LSB. At this time, when the input DAC code is "all 0", the DAC is recognized_ADJThe maximum can be 128LSB, and the minimum can be 0 LSB; when the input DAC codes to 'all 1', the DAC_ADJThe maximum may be 0LSB and the minimum may be-128 LSB. Further, a schematic diagram of the possible existence interval of the calibration information of the digital-to-analog converter provided according to the embodiment of the present disclosure as shown in fig. 8 as a function of the input DAC code can be obtained.

It will be appreciated that the calibration information DAC_ADJIt should be 0 when the DAC code of the input is "all 0" or "all 1". However, as can be seen from FIG. 8, in practical applications, the calibration information DAC_ADJThere are cases when the input DAC code is "all 1" that may not be 0, which may adversely affect the full-scale of the DAC, causing gain errors, which in turn adds random gain error calibration information GN _ ERR (DAC _ ERR) in this disclosure_C) To compensate for this gain error due to mismatch calibration. Wherein the random gain error calibration information GN _ ERR (DAC)_C) Encoding DAC for DAC_CTo another mapping of (a). In the present disclosure, the mapping needs to minimize the influence on INL and DNL of DAC, and at the same time, GN _ ERR (0) ═ 0, GN _ ERR (DAC) should be satisfied_C，MAX)＝-DAC_ADJ(DAC_C，MAX)。

Referring to fig. 9a and 9b, fig. 9a and 9b show simulated schematic diagrams of the integral non-linearity error and the derivative non-linearity error of the DAC, respectively, under the condition of considering mismatch and no calibration, and conventionally, when the mismatch condition of the resistors in the DAC is considered, the INL of the DAC can reach as large as-12 LSB, and the DNL of the DAC can reach as large as-6 LSB, which is greatly beyond the acceptable range.

While referring to fig. 10a and 10b, fig. 10a and 10b show simulated schematic diagrams of the integrated nonlinear error and the differential nonlinear error of the digital-to-analog converter after calibration under consideration of mismatch, in the present disclosure, after error correction and mismatch calibration of the DAC, the INL and DNL of the DAC are both within an acceptable range of ± 0.3 LSB.

Based on the above description, further, the DAC in the present disclosure further includes a schematic structural diagram of the controller for driving the digital-to-analog converter, as shown in fig. 5, according to the embodiment of the present disclosure. In the present disclosure, the controller is configured to calibrate and compensate for an initial DAC code received by the DAC, and to control switching of each current path in the DAC between the first node and the second node based on the calibrated and compensated DAC code such that the output voltage Vout of the DAC steps normally according to the initial DAC code.

In the embodiment of the present disclosure, the controller further includes: a first decoder 2, a segmented code correction lookup module 6, a higher order code correction lookup module (i.e., R2R MSB code correction lookup module) 7, a system gain error calculation module 5, a random gain error calculation module 4, an adder module, and a second decoder 11.

Wherein the first decoder 2 is configured to decode the initial DAC code 1 into packets to produce a segment code 2 corresponding to the second portion, a high order (i.e., R2R MSB) code 22 corresponding to the first portion having a weight value greater than a threshold, and a low order (i.e., R2R LSB) code 23 corresponding to the first portion having a weight value less than the threshold.

The segmented coding correction searching module 6 is connected to the first decoder 2, and is configured to search for and obtain pre-stored first calibration information according to the segmented coding 21.

The high-order code correction searching module 7 is connected to the first decoder 2, and is configured to search for the second calibration information stored in advance according to the high-order code.

The system gain error calculation module 5 is configured to obtain system gain error compensation information according to the initial DAC coding 1 calculation to compensate for the change in the contribution of the first and second portions to the output voltage caused by the third current path.

The random gain error calculation module 4 is configured to calculate and obtain random gain error compensation information according to the initial DAC code 1 and pre-stored random gain error information, so as to compensate for the random gain error caused by the first calibration information and the second calibration information.

And the adder module comprises a first adder 8, a second adder 9 and a third adder 10, and is used for obtaining the calibrated and compensated DAC codes according to the first calibration information, the second calibration information, the system gain error compensation information, the random gain error compensation information and the low-order codes 23.

The second decoder 11 is used to decode the calibrated and compensated DAC codes into groups to generate the first code 111, a second code (DAC) driving a plurality of fourth current paths_SUB,A)112 and a third code (DAC) driving a third current path_AUX,A)113。

Wherein the first encoding 111 and the high-order encoding 22 are used to jointly generate a DAC_R2REncoding to collectively enable driving of a plurality of first current paths, and a segmented encoding DAC_SEGFor enabling driving of a plurality of second current paths.

Further, in this disclosure, the DAC further includes: a first memory 3 for storing random gain error information.

Further, in the first embodiment of the present disclosure, the DAC stores the first calibration information and the second calibration information in a memory. Optionally, the first calibration information and the second calibration information may be stored in the second memory and the third memory, respectively, or may be stored in the same memory at the same time.

Further, in the second embodiment of the present disclosure, the DAC stores the first calibration information and the second calibration information by using a lookup table. Optionally, the first calibration information and the second calibration information may be stored in the first lookup table and the second lookup table respectively, or may be stored in the same lookup table at the same time.

Alternatively, in this embodiment, each module in the driver may be implemented by using a separate element, or may be integrated into a single integrated circuit, and the integrated circuit may be manufactured by using a Complementary Metal Oxide Semiconductor (CMOS) process, a BiCMOS process, or any other desired process or combination of processes.

Further, the calibration process of the DAC will be described in conjunction with the flow chart of the driving method of the digital-to-analog converter provided according to the embodiment of the disclosure as shown in fig. 11.

In the embodiment of the present disclosure, the DAC has the structure as shown in fig. 4 to fig. 5, and the foregoing description may be specifically referred to, and is not repeated herein.

As shown in fig. 11, in the present disclosure, the driving method of the DAC includes performing steps S1 to S3.

Therein, in step S1, an initial digital-to-analog converter code is received.

In step S2, after the initial dac code is compensated and calibrated, a calibrated and compensated dac code is obtained.

Further, the compensating and calibrating the initial dac encoding in step S2 includes: decoding the initial digital-to-analog converter to obtain a segmented code, a high-order code and a low-order code respectively; searching and obtaining first calibration information based on the segmented codes in the initial digital-to-analog converter codes; searching and obtaining second calibration information based on high-order codes in the initial digital-to-analog converter codes; obtaining system gain error compensation information based on initial digital-to-analog converter coding calculation; obtaining random gain error compensation information based on the initial digital-to-analog converter coding and random gain error calculation; adjusting the initial digital-to-analog converter encoding based at least in part on the first calibration information, the second calibration information, the system gain error compensation information, and the random gain error compensation information.

In step S3, switches located on each current path of the digital-to-analog converter are driven based on the calibrated and compensated digital-to-analog converter code.

After the calibrated and compensated digital-to-analog converter codes are obtained, the calibrated and compensated digital-to-analog converter codes are decoded again to respectively obtain binary codes for driving all parts of the DAC, and then the corresponding binary codes drive corresponding switches in all parts of the DAC, so that digital-to-analog conversion driving of the DAC is completed.

For example, assuming that the initial DAC code received by the DAC is "all 0", the weight corresponding to the sum of the first calibration information and the second calibration information searched and obtained based on the "all 0" code is 0LSB, and at this time, the system gain error calibration information and the random gain error self-calibration information obtained by corresponding calculation are both codes corresponding to 0 LSB.

Assuming that the initial DAC code received by the DAC is "all 1", the system gain error calibration information obtained by corresponding calculation based on the "all 1" code is, for example, the code corresponding to lsb (specifically, the calculation is performed based on the full scale output of the output voltage Vout). At this time, if the weight corresponding to the sum of the first calibration information and the second calibration information obtained by searching is not 0LSB, the random gain error calculation module calculates and obtains random gain error self-calibration information opposite to the calculated value of the sum of the first calibration information and the second calibration information, so that the weight corresponding to the sum of the random gain error self-calibration information and the first calibration information and the second calibration information is 0LSB, finally, the third code output in the calibrated and compensated DAC code is "1", and the second code, the fourth code and the segmented code output corresponding binary codes according to the calculated value. If the weight corresponding to the sum of the first calibration information and the second calibration information obtained by searching is 0LSB, the random gain error self-calibration information obtained by calculation is also the code corresponding to 0 LSB.

Assuming that the initial DAC code received by the DAC is an intermediate code (binary code that is not "all 0" or "all 1"), the sum of the first calibration information and the second calibration information obtained based on the intermediate code search is the code corresponding to the lsb (specifically, so that the target contribution to the output voltage Vout can be generated based on the intermediate code). Meanwhile, the system gain error calibration information obtained through corresponding calculation is, for example, a code corresponding to blbs (specifically, calculation is performed with reference to the output of the output voltage Vout as a corresponding analog value), and the random gain error self calibration information obtained through calculation is a code corresponding to dlbs, so that finally, the second code, the third code, the fourth code and the segmented code in the calibrated and compensated DAC code output corresponding binary codes according to the calculated values. It should be understood that the foregoing a, b, c and d may be any values obtained by calculation as long as they are within the range allowed by the standard.

In another aspect, the present disclosure also relates to an integrated circuit including the digital-to-analog converter shown in fig. 4 to 11.

In summary, the integrated circuit, the digital-to-analog converter and the driving method thereof according to the present disclosure add a third portion having at least one third current path on the basis of the circuit structure of the original digital-to-analog converter, and since the at least one third current path also contributes to the output voltage, the full-scale range value of the current paths of the first portion and the second portion in the original digital-to-analog converter under the condition that the driving signal is the digital-to-analog converter code full "1" is reduced, and then an interval capable of compensating the mismatch error of the digital-to-analog converter is provided, which is helpful for implementing digital calibration of the digital-to-analog converter. Meanwhile, according to the digital-to-analog converter, only one current path is added in the digital-to-analog converter, namely, digital calibration of the digital-to-analog converter can be realized only by additionally adding one resistor and one switch in a digital-to-analog conversion chip, the requirement of the digital-to-analog conversion chip on the area is reduced, the number of the switches needing to be driven is reduced, the driving time of the chip can be reduced, and the driving efficiency is further improved. And compared with the traditional laser trimming, the digital calibration in the disclosure also ensures the accuracy of trimming the digital-to-analog converter.

It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A digital-to-analog converter, comprising:

the first part is provided with a plurality of first current paths forming binary weighted weight values in the digital-to-analog converter, and the weight value corresponding to each current path in the plurality of first current paths is different;

2. The digital-to-analog converter of claim 1, wherein a smallest weight value of a plurality of weight values corresponding to the plurality of first current paths corresponds to one least significant bit of the digital-to-analog converter.

3. The digital to analog converter of claim 2, wherein the first portion further comprises:

4. A digital to analogue converter as claimed in claim 1 in which the first node is connected to a first reference voltage input and the second node is connected to a second reference voltage input.

5. A digital to analogue converter according to claim 3 wherein any one of the first plurality of current paths, any one of the second plurality of current paths and any one of the fourth plurality of current paths has a resistance of 2R therein and the at least one third current path has a resistance of m x 2R therein,

6. The digital to analog converter of claim 5, wherein the digital to analog converter further comprises:

7. The digital to analog converter of claim 6, wherein the controller comprises:

the segmented coding correction searching module is connected with the first decoder and used for searching and obtaining first pre-stored calibration information according to the segmented coding;

8. The digital to analog converter of claim 7, wherein the digital to analog converter further comprises:

a first memory for storing the random gain error information.

9. The digital to analog converter of claim 8, wherein the digital to analog converter further comprises:

a second memory for storing the first calibration information;

a third memory for storing the second calibration information.

10. The digital to analog converter of claim 8, wherein the digital to analog converter further comprises:

a first lookup table for storing the first calibration information;

a second lookup table for storing the second calibration information.

11. A method of driving a digital-to-analog converter, wherein the digital-to-analog converter has a first portion including a plurality of first current paths forming binary weighted weight values in the digital-to-analog converter, a second portion including a plurality of second current paths forming binary weighted weight values in the digital-to-analog converter, and a third portion having at least one third current path forming additional binary weighted weight values in the digital-to-analog converter so as to adjust a sum of the weight values corresponding to the first portion and the second portion, wherein each of the plurality of first current paths, the plurality of second current paths, and the at least one third current path is switchable between a first node and a second node, and a weight value corresponding to each of the at least one third current path is less than a preset threshold, the method comprises the following steps:

receiving an initial digital-to-analog converter code;

12. The driving method of the digital-to-analog converter according to claim 11, wherein the compensating and calibrating the initial digital-to-analog converter encoding includes:

13. The method according to claim 11, wherein the weighted value corresponding to each of the first current paths is different from the weighted value corresponding to each of the second current paths, and the weighted values corresponding to the current paths are the same.

14. The driving method of the digital-to-analog converter according to claim 11, wherein the first part further comprises: a plurality of fourth current paths for forming binary weighted weight values in the digital-to-analog converter,

15. An integrated circuit, comprising: a digital to analogue converter as claimed in any one of claims 1 to 10.