CN115694483B - Resistor network, low-temperature digital-to-analog converter circuit, chip and related devices - Google Patents
Resistor network, low-temperature digital-to-analog converter circuit, chip and related devices Download PDFInfo
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Abstract
The embodiment of the invention provides a resistor network applied to a digital-to-analog converter circuit, which is characterized in that on the basis of an R-2R full-resistor network architecture, a second resistor branch and a third resistor branch are respectively coupled to a plurality of resistor connection nodes in a resistor main circuit, meanwhile, the ratio of the resistance values of the main circuit resistor, a grounding resistor, a first resistor branch and an equivalent resistor after the second resistor branch and the third resistor branch are connected in parallel is 1:2:2, the integer weight represented by the original 2R branch is expanded into two non-integer weights, so that the adjustment of the resistor network on the output voltage deviation is finer, namely the calibration capability of the digital-to-analog converter under the low temperature condition can be improved, and the high resistor can be adopted to control small current, so that not only can the higher capacitance load be driven, but also the lower static power consumption can be kept.
Description
Technical Field
The present invention relates to the field of microelectronics technologies, and in particular, to a resistor network, a low-temperature digital-to-analog converter circuit, a chip, and related devices.
Background
The digital-to-analog converter is commonly classified into a current steering DAC and a resistance type DAC, wherein the basic constituent unit of the bit weight network of the current steering DAC is a current source, and the basic constituent unit of the bit weight network of the resistance type DAC is a resistance; however, at present, current mismatch or resistance mismatch of the current steering DAC or the resistance DAC is further deteriorated at low temperature, but the current calibration method is to calibrate through current injection, so that a higher signal to noise ratio cannot be obtained at low temperature, and the calibration capability is limited, which results in poor linearity of the DAC at low temperature. Therefore, it is necessary to propose a viable solution to the problem of the limited calibration capability of the DAC at low temperatures in the existing calibration mode.
Disclosure of Invention
In a first aspect of the present invention, a resistor network applied to a digital-to-analog converter circuit is provided, which not only can improve the calibration capability of the digital-to-analog converter under the low temperature condition, but also can realize the low power consumption of the digital-to-analog converter under the low temperature condition; and further, the performance requirements of the digital-to-analog converter on low power consumption, low noise and high precision under the low temperature condition are met.
In a first aspect of the invention, a resistor network is provided for use in a digital to analog converter circuit, comprising:
the resistor main circuit is formed by connecting N main circuit resistors in series, one end of the resistor main circuit is coupled to the output end of the resistor network, and the other end of the resistor main circuit is coupled to the grounding end of the resistor network through a grounding resistor;
n-n+1 first resistance branches, N second resistance branches and N third resistance branches; n is more than or equal to 2N, N is a positive integer;
the two ends of the resistor main circuit and N-N-1 resistor connection nodes on the resistor main circuit are coupled with one first resistor branch circuit, and the other N resistor connection nodes on the resistor main circuit are coupled with one second resistor branch circuit and one third resistor branch circuit;
the ratio of the resistance values among the main circuit resistance, the grounding resistance, the resistance of the first resistance branch and the equivalent resistance after the second resistance branch and the third resistance branch are connected in parallel is 1:2:2:2; and the resistance values of the resistances of the second resistance branch and the third resistance branch are non-2 powers times the main circuit resistance.
In some possible embodiments, the ratio of the resistance values between the resistances of the main circuit resistance, the first resistance branch, the second resistance branch, and the third resistance branch is 1:2:3:6.
In some possible embodiments, a resistor connection node coupled to the first resistor branch is spaced between every two adjacent resistor connection nodes coupled to the second resistor branch and the third resistor branch on the resistor main circuit.
In a second aspect of the present invention, there is provided a low temperature digital to analog converter circuit comprising:
a code conversion unit configured to convert an input original code into a calibration optimized code having n+n+1 bits according to the mapping relation table;
a parallel conversion unit configured to convert the calibration optimized code into an n+n+1-way parallel control code;
a switch array having n+n+1 switch cells, and a resistor network provided by the first aspect of the present invention;
and N-n+1 first resistance branches, N second resistance branches and N third resistance branches in the resistance network are respectively provided with a switch unit, and each switch unit is configured to be controlled by one parallel control code so as to switchably couple the first resistance branch, the second resistance branch or the third resistance branch where the switch unit is positioned to a reference voltage source or a grounding end.
In some possible embodiments, the resistive network is configured to include:
a fine calibration bit segment comprising m first resistor branches nearest to the ground resistor;
the thermometer code coding section comprises M first resistor branches closest to the output end of the resistor network;
the binary coding section comprises the rest of N-N-M-M+1 first resistance branches, N second resistance branches and N third resistance branches; wherein N-M-M is more than or equal to 2N.
In some possible embodiments, the calibration optimization coding comprises: m-bit fine calibration code, M-bit thermometer code, and n+n-M-m+1-bit binary code; the M-bit fine calibration code and the N+n-M-M+1-bit binary code are determined by the mapping relation table and the original code together, and the M-bit thermometer code is directly determined by the original code.
In some possible embodiments, a differential nonlinear error between the output voltage corresponding to the calibration optimization code and the ideal output voltage corresponding to the original code in the mapping relation table is less than 1LSB.
In some possible embodiments, the mapping table is configured to: and a lookup table taking the original code as an input and the calibration optimization code as an output.
In a third aspect of the present invention, there is provided a digital-to-analog converter chip comprising:
a substrate; and a low temperature digital-to-analog converter circuit provided in the second aspect of the present invention formed on the substrate.
In a fourth aspect of the present invention, there is provided a quantum measurement and control device comprising:
a storage and logic control unit;
a clock and synchronization triggering unit, and a plurality of low-temperature digital-to-analog converter circuits provided by the second aspect of the invention or digital-to-analog converter chips provided by the third aspect of the invention;
the storage and logic control unit is configured to buffer the received control codes corresponding to each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip, and continuously output the control codes corresponding to each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip in a first-in first-out mode;
each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip is configured to generate a corresponding analog signal according to the control code continuously output by the storage and logic control unit;
the clock and trigger unit is configured to provide a clock signal to the storage and logic control unit and a trigger signal to each of the low temperature digital-to-analog converter circuits or the digital-to-analog converter chips.
In some possible embodiments, the low temperature digital-to-analog converter circuit provided in the second aspect of the present invention or the digital-to-analog converter chip provided in the third aspect of the present invention, a part of the digital-to-analog converter chip is used for generating the gate pulse, and another part of the digital-to-analog converter chip is used for providing the dc bias signal.
In a fifth aspect of the invention, there is provided a quantum computing system comprising:
the quantum measurement and control device provided by the fourth aspect of the invention;
a qubit chip; and a low-temperature container for accommodating the quantum measurement and control device and the qubit chip and providing a low-temperature working environment for the quantum measurement and control device and the qubit chip.
In some possible embodiments, the quantum measurement and control device is ac-coupled with the qubit chip, and the quantum measurement and control device is independent of the grounding of the qubit chip.
Therefore, the resistor network applied to the digital-to-analog converter circuit provided by the invention is characterized in that on the basis of an R-2R full-resistor network architecture, a second resistor branch and a third resistor branch are respectively coupled to a plurality of resistor connection nodes in a resistor main circuit, meanwhile, the ratio of the resistances of the main circuit resistor, the grounding resistor, the first resistor branch and the equivalent resistor after the second resistor branch and the third resistor branch are connected in parallel is 1:2:2:2, the integer weight represented by the original 2R branch is expanded into two non-integer weights, so that the output voltage deviation of the resistor network is more finely regulated, namely, the calibration capability of the digital-to-analog converter under the low temperature condition can be improved, and the static power consumption can be kept lower by adopting a large resistor to control small current.
Description of the drawings:
FIG. 1 is a schematic diagram of an R-2R full resistance network architecture;
FIG. 2 is a schematic diagram of a resistor network according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a resistor network according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a resistor network according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a digital-to-analog converter circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a specific structure of a digital-to-analog converter circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a calibration flow of a digital-to-analog converter circuit chip according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a digital-to-analog converter circuit chip calibration hardware connection provided in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a quantum measurement and control chip according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a quantum computing system according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings and specific examples. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.
As shown in FIG. 1, the R-2R full resistance network architecture has two resistance values of R and 2R, so that the mismatch of resistance can be greatly reduced, meanwhile, the equivalent resistance seen from each node to the left is R, the output resistance is not changed along with the change of input codes, and the load driving capability is stable. However, the input resistance changes along with the input code, so the stability requirement on the reference voltage source is higher, meanwhile, the structure still has the problem of non-monotonous, and the accuracy of the output voltage can be ensured by auxiliary calibration.
In one embodiment of the present invention, a resistor network is provided for use in a digital-to-analog converter circuit, as shown in fig. 1, comprising:
a resistor main circuit 101, which is formed by connecting N main circuit resistors R in series, one end of which is coupled to the output end Vout of the resistor network, and the other end of which is coupled to the ground end of the resistor network through a ground resistor 105;
n-n+1 first resistor branches 102, N second resistor branches 103, and N third resistor branches 104; n is more than or equal to 2N, N is a positive integer;
the two ends of the resistor main circuit 101 and the N-1 resistor connection nodes on the resistor main circuit 101 are coupled with one first resistor branch circuit 102, and the other N resistor connection nodes on the resistor main circuit 101 are coupled with one second resistor branch circuit 103 and one third resistor branch circuit 104;
the ratio of the resistance values among the main circuit resistor R, the ground resistor 105, the resistance of the first resistor branch 102, and the equivalent resistance of the second resistor branch 03 and the third resistor branch 104 after being connected in parallel is 1:2:2:2. I.e. corresponding to 1/2 r=1/rx+1/Ry. Moreover, if the resistance of the second resistance branch 103 and the resistance of the third resistance branch 104 are the power of 2 times the main resistance, they are equivalent to other weight bits in the resistance network; therefore, to avoid redundancy of the resistive network weight bits, the resistance values of the resistances of the second resistive branch 103 and the third resistive branch 104 are power-times the non-2 power of the main path resistance.
Therefore, on the basis of the R-2R full-resistance network architecture, the resistor network provided in this embodiment is configured to configure the resistance of the main circuit, the ground resistor, the resistance of the first resistor branch, and the ratio of the resistance values between the second resistor branch and the equivalent resistance of the third resistor branch after being connected in parallel by coupling a second resistor branch and a third resistor branch to a plurality of resistor connection nodes in the main circuit of the resistor respectively, so that the integral weight represented by the original 2R branch is expanded to two non-integral weights, and the adjustment of the output voltage deviation by the resistor network is finer, that is, the calibration capability of the digital-to-analog converter under the low temperature condition can be improved.
In some possible embodiments, as shown in fig. 3, the ratio of the resistances among the main path resistance, the resistance of the first resistance branch, the resistance of the second resistance branch, and the resistance of the third resistance branch is 1:2:3:6. I.e. corresponding to Rx of 6R and Ry of 3R. Specifically, 2R in the R-2R full resistance network architecture branch is replaced by parallel connection of 6R and 3R of two paths, which is equivalent to that the current I originally flowing through the 2R branch is divided into two paths, and flows through the 6R and 3R respectively, and the current flowing through the 6RThe current flowing through 3R is +.>The weight of the 6R branch is therefore +.2 of the original 2R branch weight>Weight of 3R branch original 2R branch weight +.>Taking bit 6 as an example, when the BA6 bit is inputted to be high level, the branch is opened, and the corresponding weight is +.>When BB6 bit is inputted to high level, the branch is opened, and the corresponding weight is +.>The calibration structure is equivalent to subdividing the weight represented by the 2R branch into trisections, and the increase of the non-integer weight increases the total combination number, so that the output voltage deviation is more finely regulated.
In some possible embodiments, as shown in fig. 4, each two adjacent resistor connection nodes on the resistor main circuit, which are coupled to the second resistor branch and the third resistor branch, are separated by a resistor connection node that is coupled to the first resistor branch.
In one embodiment of the present invention, a low temperature digital to analog converter circuit 200 as shown in fig. 5 is provided, comprising:
a code conversion unit configured to convert an input original code into a calibration optimized code having n+n+1 bits according to the mapping relation table;
a parallel conversion unit configured to convert the calibration optimized code into an n+n+1-way parallel control code;
a switch array having n+n+1 switch units, and a resistor network provided in the embodiment of the present invention;
and N-n+1 first resistance branches, N second resistance branches and N third resistance branches in the resistance network are respectively provided with a switch unit, and each switch unit is configured to be controlled by one parallel control code so as to switchably couple the first resistance branch, the second resistance branch or the third resistance branch where the switch unit is positioned to a reference voltage source or a grounding end.
In this embodiment, the low-temperature digital-to-analog converter circuit 200 employs a resistor network as shown in fig. 4, and the low-temperature digital-to-analog converter circuit 200 needs to be calibrated before use.
The calibration principle is as follows: the high linearity static metrics of the digital-to-analog converter are Differential Nonlinearity (DNL) and Integral Nonlinearity (INL). INL <1, dnl <1 is generally required to be considered valid. When the integral nonlinearity is greater than 1, the input code is 4, the actual output is only 2.9, and the following bit numbers are all overlapped on the basis of the error output; in the case of DNL <1, the error may be generated by incrementing the input code so that the output approaches the normal value. If DNL >1, enlarging the input code means that there are output voltages corresponding to both input codes, and such a mapping relationship may cause errors in the calibration system, so that correction cannot be performed; therefore, the most critical part of the calibration is to make DNL <1, and meanwhile, as large errors are generally generated in jump when the high-order is 0 or 1, and the errors are maximum when jump is performed in the middle of the represented numerical range, jump situations of all 0 and all 1 are avoided as much as possible. Taking the calibration of the maximum error as an example, the calibration principle is explained.
Referring to Table 1, assuming four sign values, denoted as B3B2B1B0, respectively, the maximum DNL occurs when B3B2B1B0 changes from 0111 to 1000. If the highest bit B3 is replaced with a 6R-3R structure, the 6R branch is denoted as BA3, and the 3R branch is denoted as BB3, the weight of BA3 is 8/3, and the weight of bb3 is 16/3, as shown in table 1. If the code is input to the system according to the normal jump sequence, when the input code is 7 to 8, the conditions of all 0 and all 1 are generated; and (3) starting the calibration bit in advance at 6, so that the weight of the highest bit is smaller than the original weight, thereby leaving a margin for the upper filling for the lower bits, and forcing the lower bits not to be all 0 or 1. There are two calibration sequences, which are determined according to whether the actual output is large or small; the adjustment of one to two digits in advance before the maximum error is proper, and the adjustment can be realized at digits with a weight greater than 8/3, namely, the adjustment at 16/3 weight (second column of calibration sequence), but at the moment, the lower digits are mostly 0 or 1 due to the fact that the digits are too small, and the error is larger when the intermediate value jump is accumulated; after the maximum error point is passed, the input code is reset immediately before the situation that most of all 0 or 1 are happened again, so that the higher calibration is facilitated. In the process of opening or closing the non-maximum error bit, the error is increased along with the increase of the input value, and when the error is larger, a calibration bit with a weight larger than or smaller than the current jump bit can be opened for calibration. Thus, the differential nonlinear error can be controlled below 0.3 LSB.
Table 1: calibration principle schematic table
In this embodiment, a hardware connection schematic diagram of the calibration flow shown in fig. 8 is adopted to calibrate the low-temperature digital-to-analog converter circuit 200, and the specific calibration flow is shown in fig. 7; firstly, pre-calibration is carried out, namely an initial lookup table (LUT) is manufactured, original codes are converted into codes with calibration bits according to a calibration principle at a position with larger error, and all the hops of all 0's or 1's are avoided; because of unavoidable and inaccurately predictable mismatch errors in actual manufacturing, real-time calibration of the actual test output voltage values is required. The lookup table control program is burnt into an FPGA board, input codes are sequentially and automatically input from 0 to 1048575, and the input codes pass through an on-chip SPI parallel control circuit; the output voltage of the chip is tested by the high-precision multimeter, the data acquisition is transmitted to the PC end through the matlab program control interface converter of the PC end, the process is to input a code, the FPGA triggers one-time interruption, the high-precision multimeter is tested once, the PC end acquires one-time data, and the acquired data is sent to the optimization calibration algorithm after the acquisition is successful. The optimization calibration algorithm logic is to compare the collected data with the output corresponding to the ideal code: if the number of the input codes is greater than 1LSB, entering a calibration stage, generating a new input code, and generating a trigger for the FPGA to trigger the input of the current code; if the data is less than 1LSB, the acquired data is stored, and the input of the next code is triggered. Each time the code is calibrated to be less than 1LSB, the input of the next code is not entered, the calibration test data of the current code is stored only by taking the last optimal value, and all the previous optimal values are thrown away. The calibration algorithm logic is shown in fig. 10. Thus, all code inputs are automatically tested and calibrated, and traversed.
Of course, because of traversing all codes, the test quantity is larger, the strategy of optimizing the calibration algorithm can be adjusted to acquire differential errors at key points and when each resistor branch is started, two adjacent input codes are tested for DNL; all DNL is adjusted to be smaller than 1, and DNL of each resistor branch can be obtained through accumulation test by using LMS (least mean square) algorithm and DNL test of other values; if the DNL result is less than 1, namely monotonous is ensured, comparing the difference value between the test output voltage and the ideal voltage, if INL is more than 1, correspondingly shifting the input code by the error value, and obtaining the input code sequence with INL < 1; the test of INL can be obtained by adding DNL of each bit (the test of INL is obtained by calculation, INL is compared according to the calculation result, translation is carried out), and the phase-locked amplifier is used for modulating the test to counteract common-mode noise, so that accurate noise calibration is realized.
Therefore, in this embodiment, the integrated nonlinear error between the output voltage corresponding to the calibration optimization code and the ideal output voltage corresponding to the original code in the mapping table is less than 1LSB. The mapping table is configured to: and a lookup table taking the original code as an input and the calibration optimization code as an output.
In one embodiment of the invention, the linearity of binary codes in the digital-to-analog converter circuit is poor, and the thermometer codes have good linearity, but occupy a large circuit surface when the number of bits is large; thus, for the tradeoff of area cost and linearity, a low temperature digital to analog converter circuit 200 is provided as shown in fig. 6.
In the present embodiment, the resistor network of the low-temperature digital-to-analog converter circuit 200 is configured to:
a fine calibration bit segment 100a comprising m of said first resistor branches nearest said ground resistor;
thermometer code encoding segment 100c, comprising M of said first resistive branches nearest to said resistive network output;
the binary coding section 100b includes the rest of N-M-m+1 first resistor branches, N second resistor branches and N third resistor branches; wherein N-M-M is more than or equal to 2N.
Specifically, in the resistor network, the binary coded high bit is 2 times the weight of the adjacent low bit, and each thermometer code bit is the same high bit weight. The expression of the output voltage can be written as,
wherein, the corresponding weight of each resistance branch is 2 respectively -N 、2 1-N …2 -1 If the N-1 bit switch is closed, i.e. the data input is high, D N-1 =1, the voltage weight corresponding to the resistance branchSuperimposed to the output voltage; if the N-1 bit switch is turned off, i.e. the data input is low, D N-1 =0, the voltage weight corresponding to the resistor branch does not participate in the calculation of the output voltage. In short, each resistor branch is controlled to be switched on and off by a switch, the switch is controlled by an input code, if the switch is closed, the branch participates in weight calculation and is superimposed to output voltage, and if the switch is opened, the branch participates in weight calculationThe branch circuit does not participate in weight calculation, and has no influence on output voltage.
In this embodiment, the calibration optimization code includes: m-bit fine calibration code, M-bit thermometer code, and n+n-M-m+1-bit binary code; the M-bit fine calibration code and the N+n-M-M+1-bit binary code are determined by the mapping relation table and the original code together, and the M-bit thermometer code is directly determined by the original code.
In the present embodiment, considering that the original weight becomes 1/3 and 2/3 due to the resistance network replacing 2R in the R-2R full resistance network architecture branch with 6R and 3R of two branches in parallel, it is assumed that the original weight of the ith bit is 2 i Then becomeAnd->I.e., it can be seen that the weight of bit i+1 is changed to 1/3 of the original weight. If 2R is replaced by two paths of 6R and 3R in parallel in the i+1th branch, the 1/3 weight of the two paths acts the same as the previous bit, and the 2/3 weight acts the same as the 1/3 weight of the i+2th bit, thus the weight of the i+1th bit is provided with redundancy. The low-temperature digital-to-analog converter circuit 200 adopts a resistor network as shown in fig. 4, that is, a resistor connection node coupled to the first resistor branch is spaced between every two adjacent resistor connection nodes coupled to the second resistor branch and the third resistor branch on the resistor main circuit. Thereby avoiding the addition of redundant structures, occupying the area of the circuit and increasing the cost.
In this embodiment, the fine calibration bit segment 100a is set to continue the accurate calibration of DNL within 1LSB, for example, m takes 3, which is equivalent to adding weights of 1/2,1/4, and 1/8 to the lowest three bits, respectively, as the fine calibration bits.
In one embodiment of the present invention, there is provided a digital-to-analog converter chip including:
a substrate; and digital-to-analog converter circuits provided in various embodiments of the present invention formed on the substrate.
In this embodiment, the digital-to-analog converter circuit is fabricated by using a cmos process; moreover, by adopting an on-chip full-resistance structure and combining an off-chip calibration algorithm, a good calibration effect can be obtained at low temperature, so that a voltage stepping unit of 1ppm, namely the control accuracy of 1uV, is realized. Therefore, on the premise of meeting the working requirement, the static power consumption is about 0.3mW, and the dynamic power consumption is lower due to lower working speed, so that the heat power consumption limit of large-scale expansion can be met.
Meanwhile, since the calibration mode of current injection is not adopted, almost all noise sources are resistance thermal noise contributions, and the noise sources are reduced along with the reduction of temperature. Through test, the flicker noise 812.8nV@0.1-10 kHz and the thermal noise 7.656nV/Hz are realized at the low temperature of 4K 0.5 。
Therefore, the low-temperature digital-to-analog converter chip provided in the embodiment has the performance advantages of low power consumption, low noise and high precision in a 4K low-temperature environment.
At present, a quantum measurement and control system is being integrated from normal temperature (290K) to low temperature (4K) environment, so that the problems that a large number of signal cables are needed and the quantum measurement and control system can be connected to a quantum chip only when crossing a temperature zone are avoided, and a large amount of noise is introduced, the complexity of interconnection is brought, the cost is high, the reliability is unreliable and the like are solved. Meanwhile, the quantum measurement and control system comprises a plurality of functional units such as low-noise microwave pulse, high-stability precise voltage, square wave pulse, signal acquisition and analysis and the like, and has a larger volume, so that the quantum measurement and control system is integrated into a quantum measurement and control chip. The low-temperature digital-to-analog converter circuit provided in the embodiment has the performance advantages of low power consumption, low noise and high precision in a 4K low-temperature environment after being chipped, and is particularly suitable for a chipped scene of a quantum measurement and control system.
In one embodiment of the present invention, a quantum measurement and control device 20 as shown in fig. 9 is provided, comprising:
a storage and logic control unit 300;
a clock and synchronization triggering unit 400, and a plurality of digital-to-analog converter circuits 200 provided in the embodiments of the present invention;
the storage and logic control unit 300 is configured to buffer the received control codes corresponding to each digital-to-analog converter chip, and continuously output the control codes corresponding to each digital-to-analog converter chip in a first-in-first-out manner;
each digital-to-analog converter circuit 200 configured to generate a corresponding analog signal according to the control code continuously output by the storage and logic control unit 400;
the clock and trigger unit 400 is configured to provide a clock signal to the storage and logic control unit 400 and a trigger signal to each of the digital-to-analog converter circuits 200.
In this embodiment, a part of the digital-to-analog converter circuit is used for generating gate pulses, and another part of the digital-to-analog converter chip is used for providing direct current bias signals. The specific output configuration can be determined according to the requirements of the actual quantum measurement and control application scene.
Meanwhile, in this embodiment, the quantum measurement and control device 20 may adopt a plurality of low-temperature digital-to-analog converter chips manufactured based on the digital-to-analog converter circuit 200, so as to implement a circuit board-level quantum measurement and control device; of course, the quantum measurement and control device 20 may also be implemented as a chip-level quantum measurement and control device, i.e. a quantum measurement and control chip, by using the storage and logic control unit 300, the clock and synchronization triggering unit 400, and the digital-to-analog converter circuits 200 as chips.
In one embodiment of the present invention, there is provided a quantum computing device as shown in fig. 10, including:
the quantum measurement and control chip 20 provided in the embodiment of the invention;
a qubit chip 10; and a low temperature container (not shown in fig. 10) for accommodating the quantum measurement and control chip 20 and the qubit chip 10 and providing a low temperature working environment for the quantum measurement and control chip 20 and the qubit chip 10.
In this embodiment, the quantum measurement and control chip 20 is ac-coupled with the qubit chip 10, and the grounding of the quantum measurement and control chip 20 and the qubit chip 10 is independent, so that V can be maintained DD -V SS =1v unchanged by changing V DD The range of (2) is-3V-1V, and the direct current bias range is-4V-1V. Specifically, the number relationship between the quantum measurement and control chip and the quantum bit chip is determined according to the number of quantum bits, for example, if the number of quantum bits constructed by the quantum bit chip is large, a plurality of quantum measurement and control chips may be required.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (11)
1. A resistor network for use in a digital to analog converter circuit, comprising:
the resistor main circuit is formed by connecting N main circuit resistors in series, one end of the resistor main circuit is coupled to the output end of the resistor network, and the other end of the resistor main circuit is coupled to the grounding end of the resistor network through a grounding resistor;
n-n+1 first resistance branches, N second resistance branches and N third resistance branches; n is more than or equal to 2N, N is a positive integer;
the two ends of the resistor main circuit and N-N-1 resistor connection nodes on the resistor main circuit are coupled with one first resistor branch circuit, and the other N resistor connection nodes on the resistor main circuit are coupled with one second resistor branch circuit and one third resistor branch circuit;
the ratio of the resistance values among the main circuit resistance, the grounding resistance, the resistance of the first resistance branch and the equivalent resistance after the second resistance branch and the third resistance branch are connected in parallel is 1:2:2:2; and the resistance values of the resistances of the second resistance branch and the third resistance branch are power times of non-2 of the main circuit resistance;
the ratio of the resistance values among the main circuit resistance, the resistance of the first resistance branch, the resistance of the second resistance branch and the resistance of the third resistance branch is 1:2:3:6;
and a resistor connection node coupled with the first resistor branch is arranged between every two adjacent resistor connection nodes coupled with the second resistor branch and the third resistor branch on the resistor main circuit at intervals.
2. A low temperature digital to analog converter circuit, comprising:
a code conversion unit configured to convert an input original code into a calibration optimized code having n+n+1 bits according to the mapping relation table;
a parallel conversion unit configured to convert the calibration optimized code into an n+n+1-way parallel control code;
a switch array having n+n+1 switch cells, and a resistor network as claimed in claim 1;
and N-n+1 first resistance branches, N second resistance branches and N third resistance branches in the resistance network are respectively provided with a switch unit, and each switch unit is configured to be controlled by one parallel control code so as to switchably couple the first resistance branch, the second resistance branch or the third resistance branch where the switch unit is positioned to a reference voltage source or a grounding end.
3. The low temperature digital to analog converter circuit of claim 2, wherein said resistor network is configured to include:
a fine calibration bit segment comprising m first resistor branches nearest to the ground resistor;
the thermometer code coding section comprises M first resistor branches closest to the output end of the resistor network;
the binary coding section comprises the rest of N-N-M-M+1 first resistance branches, N second resistance branches and N third resistance branches; wherein N-M-M is more than or equal to 2N.
4. A low temperature digital to analog converter circuit as claimed in claim 3, wherein said calibration optimized code comprises: m-bit fine calibration code, M-bit thermometer code, and n+n-M-m+1-bit binary code; the M-bit fine calibration code and the N+n-M-M+1-bit binary code are determined by the mapping relation table and the original code together, and the M-bit thermometer code is directly determined by the original code.
5. The low temperature digital to analog converter circuit of claim 4, wherein a differential nonlinear error between an output voltage corresponding to said calibration optimization code and an ideal output voltage corresponding to an original code in said mapping table is less than 1LSB.
6. The low temperature digital to analog converter circuit of claim 5, wherein said mapping table is configured to: and a lookup table taking the original code as an input and the calibration optimization code as an output.
7. A digital-to-analog converter chip, comprising:
a substrate; the low-temperature digital-to-analog converter circuit according to any one of claims 2 to 6, formed on the substrate.
8. The quantum measurement and control device is characterized by comprising:
a storage and logic control unit;
a clock and synchronization triggering unit, a plurality of low temperature digital-to-analog converter circuits according to any one of claims 2-6 or digital-to-analog converter chips according to claim 7;
the storage and logic control unit is configured to buffer the received control codes corresponding to each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip, and continuously output the control codes corresponding to each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip in a first-in first-out mode;
each low-temperature digital-to-analog converter circuit or each digital-to-analog converter chip is configured to generate a corresponding analog signal according to the control code continuously output by the storage and logic control unit;
the clock and trigger unit is configured to provide a clock signal to the storage and logic control unit and a trigger signal to each of the low temperature digital-to-analog converter circuits or the digital-to-analog converter chips.
9. The quantum measurement and control device of claim 8, wherein one part of the low-temperature digital-to-analog converter circuits or the digital-to-analog converter chips is used for generating gate pulses, and the other part is used for providing direct current bias signals.
10. A quantum computing device, comprising:
the quantum measurement and control device of claim 8 or 9;
a qubit chip; and a low-temperature container for accommodating the quantum measurement and control device and the qubit chip and providing a low-temperature working environment for the quantum measurement and control device and the qubit chip.
11. The quantum computing device of claim 10, wherein the quantum measurement and control device is ac coupled with the qubit chip and the quantum measurement and control device is independent of a ground of the qubit chip.
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