JPH08125536A - Resistance radder, d/a converter and a/d converter - Google Patents

Abstract

PURPOSE: To realize high-dimensional resolution with less parts by changing connection routes to positive/negative analog voltage sources after analog conversion with a resistance radder and enlarging the number of the dimension of resolution obtained by changing analog output into plural stages. CONSTITUTION: The resistance radder is formed by resistance groups 17-19. In the resistance group 17, 2<n> -2-pieces of resistances 4 having resistance values R are serially connected to the resistances 51 and 52 having resistance values R/2, and 2<n> -pieces of radder taps are connected to the connection points of the negative analog voltage source-side of the resistances 4, 51 and 52. In the resistance group 18, 2<n-m> -pieces of resistances having the resistance value R/2 are serially connected, and one end is connected to the resistance group 17 and the other end to the analog voltage source 1 through a connection means 24. The middle parts of the respective resistances 53 are connected from the connection means 21-23 to the power source 1. In the resistance group 19, 2<n-m> -1-pieces of the resistances 53 are serially connected, and one end is connected to the resistance group 17 and the other end to a power source 2 through a connection means 34. The middle parts of the resistances 53 are connected to the power source 2 through connection means 31-33. Thus, analog voltage can be changed in 2<n-m> stages by selection-controlling the connection means 21, 24 and 31-34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance ladder, a DA converter using the resistance ladder, and an AD converter using this DA converter.

[0002]

2. Description of the Related Art A for converting an analog voltage into a digital value
The -D converter requires a reference voltage to be compared with the analog voltage to be converted. As such an A-D converter,
It is typical to generate an analog reference voltage for comparison by a DA converter using a resistance ladder in which a plurality of resistors are connected in series. FIG. 16 is a circuit diagram showing a configuration of a main part of a conventional n-bit resolution D-A converter using a resistance ladder, and this conventional example is a 4-bit resolution D-A converter. In the figure, 1 is a positive analog voltage source (VREF),
2 is a negative analog voltage source (AVSS), and (2 ⁿ −2) [= 14] resistors 4 each having a resistance value of R are connected in series to the positive analog voltage source 1 and the negative analog voltage source 2. The connected resistor series 4, 4, ..., The resistor 6 having a resistance value of 3R / 2, which connects one end of the resistor series 4, 4, ... To the positive analog voltage source 1, and the other end of the resistor series 4, 4 ,. Resistor ladder 3 consisting of a resistor 5 having a resistance value R / 2 for connecting a negative analog voltage source 2
Is connected. The resistance ladder 3 has a total resistance value of 16 · R, and obtains a voltage division value of 2 ⁴ steps of the potential difference between the positive analog voltage source 1 and the negative analog voltage source 2. 2 between the resistor 5 of the resistor ladder 3 and the negative analog voltage source 2 and between each resistor.
Ladder tap T1 to take out each of the ^four partial pressure values
T16 is connected.

The switching tree 7 is provided with switch groups 70 to 77 which are controlled so as to select one of the ladder taps T1 to T16 of the resistor ladder 3 to obtain an analog output 8.
The switch groups 70 to 77 are digital signals a, a, b, a, which represent a 4-bit digital value “abcd” by a positive logic and a negative logic, which are given from an external control circuit (not shown) via a word line. Bar b, c, bar c, d, bar d
ON / OFF is controlled by each level of.
In the figure, it is assumed that the switches 70 to 77 are turned on when the digital signal corresponding to the code attached to each of them is "1". That is, FIG. 14 shows the digital value "abc".
"d" is "10 10 ₂ ", the digital signal a, the bars b and c, the bar d is "1", and the other digital signals are "0".

[0004]

[Table 1]

Table 1 shows the digital value "abcd" and VRE.
It shows the relationship between the analog voltage value of the analog output 8 when F is 4V and AVSS is 0V and the ladder taps T1 to T16 from which this analog voltage value is obtained. As is clear from the table, the voltage of the ladder tap is 0.125V between Vlad and the ladder tap T16, which is the potential difference between the ladder tap T1 and the ladder tap T2, which are the lowest resistance ladders to obtain the potential of VSS. The potential difference is 0.375V, and the potential difference between the other ladder taps T2 to T15 is 0.25V, respectively, and the partial pressure value obtained by decomposing the potential difference between VREF and AVSS by 2 ⁴ [= 16] is taken out by the ladder taps T1 to T16. Has been.

FIG. 17 shows, for example, Japanese Patent Laid-Open No. 54-15136.
No. 8 (USP.879646),
16 is a 4-bit resolution successive approximation type A-D converter using the D-A converter of FIG. 16, in which 9 is a 4-bit resolution D-A converter having the configuration of FIG. . D-
The A converter 9 serves as a reference voltage for comparing an analog voltage of one of the ladder taps T1 to T16 corresponding to a 4-bit digital value as shown in Table 1 with an analog input (AIN) 25 from the outside. It is supplied to the comparator 16. Four
The bit control circuit 10 generates a digital signal a, bars a, b, ..., Bar d corresponding to a 4-bit digital value and supplies the digital signal to the DA converter 9 via a word line. The 4-bit digital value is determined based on the comparison result signal 20 from the comparator 16 that compares the analog output 8 of the −A converter 9.

Next, the operation of digital conversion by the A / D converter having the above-described structure is performed by the analog input 25 of 1.3.
The case of V will be described as an example. First, the reference voltage for comparison is D
In order to output from the -A converter 9, the digital value "abc"
When the digital signal corresponding to the digital value "1000 ₂ " in which the most significant bit "a" of d "is set to" 1 "is given to the DA converter 9, the DA converter 9 outputs (VREF / 2 )-(VREF / 32) [V] (= 1.87)
5 V) is supplied to the comparator 16. The comparator 16 has a D-
Analog output 8 and analog input from A converter 9 (AI
N) 25. [(VREF / 2)-(VREF / 32)]: AIN That is, 1.875V: 1.3V As a result, since the AIN side is low, the 4-bit control circuit 10 causes the comparison result signal 20 to output the digital value of the bit "a". Is set to "0".

Next, the digital signal corresponding to the digital value "0100 ₂ " in which the bit "b" is set to "1" is D-
When applied to the A converter 9, the DA converter 9 outputs (VREF / 4)-(VREF / 32) [V] (= 0.87).
5 V) is supplied to the comparator 16. The comparator 16 has a D-
Analog output 8 and analog input from A converter 9 (AI
N) 25. [(VREF / 4)-(VREF / 32)]: AIN That is, 0.875V: 1.3V As a result, since the AIN side is high, 4 depending on the comparison result signal.
The bit control circuit 10 determines the digital value of the bit “b” to be “1”.

Next, the digital signal corresponding to the digital value "0110 ₂ " in which the bit "c" is set to "1" is D-
When applied to the A converter 9, the DA converter 9 produces (3.VREF / 8)-(VREF / 32) [V] (= 1.
375 V) is supplied to the comparator 16. The comparator 16 has a D-
Analog output 8 and analog input from A converter 9 (AI
N) 25. [(3 · VREF / 8)-(VREF / 32)]: AIN That is, 1.375V: 1.3V As a result, since the AIN side is low, 4 depending on the comparison result signal.
The bit control circuit 10 determines the digital value of the bit “c” to be “0”.

[0010] Next, a digital signal corresponding to the bit "d" the digital value set to "1""0101_2" D-
When given to the A converter 9, the DA converter 9 outputs (5.VREF / 16)-(VREF / 32) [V] (=
1.125 V) is supplied to the comparator 16. The comparator 16 has a D-
Analog output 8 and analog input from A converter 9 (AI
N) 25. [(5 · VREF / 16)-(VREF / 32)]: AIN That is, 1. 125V: 1.3V As a result, since the AIN side is high, it becomes 4 depending on the comparison result signal.
The bit control circuit 10 determines the digital value of the bit “d” to be “1”. Or more analog voltages 1.3V of AIN successive comparison is converted into a digital value "0101 _2".

[0011] The digital value of the conversion result "0101 _2",
As is clear from Table 1, the input voltage of the analog input (AIN) is between 1.125 and 1.375V. The width of such a voltage is generally called a quantization error, and is determined by the resolution of the AD converter with respect to the reference voltage. The A / D converter converts the digital value into a digital value that is twice as high as the 8-bit resolution at 9-bit resolution and twice as high as 9-bit resolution at 10-bit resolution. Therefore, the width of the quantization error becomes narrower as the resolution becomes higher, and the value indicated by the digital value approximates to the analog voltage. The advantage of the A-D converter that generates the analog reference voltage for comparison in the D-A converter using the resistance ladder is that the D-A converter generates the analog reference voltage by the voltage division of the resistors, so that As long as the variation is uniform, the partial pressure value is extremely accurate.
The conversion characteristic of the AD converter using the -A converter has a very good linearity.

On the other hand, the disadvantage of this AD converter is that the AD
The DA converter must generate a number of partial pressure values corresponding to the resolution of the converter. Therefore, A with 8-bit resolution
For use in a -D converter, at least 2 ⁸ [= 25
6], at least 2 ⁹ with 9-bit resolution [= 51
2], at least 2 ¹⁰ [= 10 at 10-bit resolution]
24] The number of resistors is required, and the number of resistors is required every time the resolution is increased by 1 bit. Therefore, if the resolution is increased, the area is expanded and the manufacturing yield is lowered, so that the LSI manufacturing cost is increased. There was a disadvantage. In order to improve the above-mentioned disadvantages, for example, Japanese Patent Laid-Open No. Hei 1-97020 discloses A
In the process of -D conversion, once select two adjacent ladder taps of the series resistance ladder, and install a series resistance ladder with a resistance much higher than the resistance between the ladder taps to create the above two ladder taps. A circuit is disclosed which improves the resolution of the A-D converter by connecting and further dividing the potential between the ladder taps originally selected by the high resistance series resistance ladder.

Further, as an AD converter using the DA converter, the DA converter sequentially repeats the conversion from the upper bit to the least significant bit in units of a plurality of bits, and the analog output in units of a plurality of bits. There is a parallel A / D converter or a serial / parallel A / D converter that performs digital conversion by repeating comparison between the analog input and a conversion target analog input. FIG. 18 is a circuit diagram showing a configuration of a conventional DA converter used in a serial-parallel AD converter for analog-converting a digital value in units of p bits, and has a 4-bit resolution shown in FIG. The D-A converter of No. 2 performs analog conversion in units of 2 bits. D
The -A converter has a resistance ladder in which 2 ⁿ [= 16] resistors are connected in series, and (2 ^p -1) [= 3] analog outputs 8
1, 82 and 83, and 15 selection switches 701 to 715 for obtaining (2 ^p −1) analog outputs 81, 82 and 83 from the resistance ladder. An AD converter using this DA converter has analog outputs 81, 82, 8
3 has (2 ^p −1) comparators (not shown) connected to each other, and the analog voltage input from the outside is converted into a 2-bit unit from a higher-order bit in a DA converter. It is for digital conversion in comparison with analog output.

Even in such a DA converter, if the resolution is to be improved, the circuit scale is increased as in the case of using the resistance ladder having the structure shown in FIG. For example, when realizing a 6-bit resolution D-A converter with the same configuration as the 4-bit resolution D-A converter shown in FIG. 18, the resistance ladder is composed of at least 64 resistors and 62 switches. Need.

[0015]

However, in the circuit disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-97020, no matter how high the resistance connected between the two ladder taps is, it is theoretical. Since the main current flowing through the resistor ladder is shunted, the potential difference between the ladder taps connected with the high resistance resistor group is reduced, and the voltage between the ladder taps connected with the high resistance resistor group is between the other ladder taps. It is practically difficult to eliminate the error caused by the reduced potential difference because it is not the same as the potential difference of.

Assuming that the resistance value of this high resistance resistance group is 20 as the resistance value between the adjacent ladder taps of the first resistance ladder.
When it is set to 00 times, the error caused by connecting a high resistance resistor group can be set to a negligible value, but even if the error is set to an allowable value, when the same material is used for the resistors, the high resistance It is clear that the group occupies a considerable area. Furthermore, even if the problem of the area occupied by the resistance group is solved by using a high resistance material for the material, the switch that connects these high resistance resistance groups to the ladder tap can theoretically have resistance, so the resistance of the switch If the circuit is not configured in consideration of the error due to, the potential difference between the reference voltage sources connected across the resistance ladder cannot be divided accurately.

Further, in FIGS. 4 and 5 of Japanese Patent Application Laid-Open No. 54-151368 (USP.879646), three unit resistors having a resistance value R from a positive analog voltage source are provided, followed by a resistance value R. 4 resistors of / 4 are connected in series up to the negative analog voltage source to form a resistor ladder, and the 3 resistor groups and 2 analog voltages obtained from the 4 resistor groups of this resistor ladder are A 4-bit resolution D / A converter that obtains an analog output by applying a difference between two analog voltages to a non-inverting input and an inverting input of a buffer is disclosed. FIG. 7 shows a 12-bit A / D converter. The application example to is disclosed.

In this disclosed example, the resistance ladder is composed of a small number of resistors, and the area occupied by the resistors is small. However, since the number of resistors is small, the total sum of the resistance values of the resistance ladder is smaller than that of the series resistor. Therefore, when the power source impedance between the positive analog voltage source and the negative analog voltage source is not sufficiently low, the charge / discharge current of the capacitance added to the resistance ladder causes the analog voltage source to fluctuate, resulting in A-
It affects the accuracy of the D converter. In addition, when the resistance value of the whole is low, the resistance component of the conductors that connect the individual resistors has a large effect on the entire resistance ladder, and the resistance ladder is configured with due consideration of the resistance component of the conductor that is originally small. There is a need to.

Further, in order to test the disconnection of the ladder taps with the AD converter having the 6-bit resolution which has the DA converter with the series resistance ladder built in, 64 ladder taps of the resistance ladder and ladder taps are used. There are 64 paths from the switch to the analog output through the switching tree.
It was necessary to perform D conversion and test the accuracy of 64 points.
Further, in the shipping inspection of the LSI, among all the circuits, those having even one defective transistor are selected as defective products. Although the conversion accuracy of the A-D converter is generally tested for the A-D converter and the LSI equipped with the A-D converter, the A-D converter using the resistance ladder is tested for the number of points according to the resolution. Therefore, as the resolution increases, the number of test points increases, and the test time increases, which causes an increase in manufacturing cost.

The present invention has been made in order to solve such a problem, and after analog conversion is performed by a resistance ladder having the same structure as the conventional one, connection paths to positive and negative analog voltage sources are provided. The analog output of the conversion result is changed in a plurality of steps by changing the value of the conversion result to extend the order of the resolution, and an object of the present invention is to provide an AD converter with a high conversion accuracy that realizes a high-order resolution with a small number of components. And

The present invention also provides A- which has a high-order resolution.
The purpose of the present invention is to provide an inexpensive A-D converter by saving the labor of testing the D converter.

[0022]

In the resistance ladder according to the first aspect of the present invention, a resistance series having a total resistance value of (2 ^m -1) · R, and a connection point between the resistances and one end of the resistance series are generated. a first resistor group having a 2 ^m-number of ladder tap taking out 2 ^m pieces of divided voltage value, 2 ^nm number of resistors of the resistance value are connected in series a respective resistance value R / 2 ^nm In order to adjust the number of resistors whose total sum is R and the number of resistors inserted in the connection path from the first resistor group to the first reference voltage source, the connection point between the resistors and one end of the resistor string are respectively A second resistor group having connecting means for connecting to one reference voltage source, and a resistor string in which (2 ^nm −1) resistors each having a resistance value of R / 2 ^nm are connected in series, and A connection point between the resistors and a resistor string to adjust the number of resistors inserted in the connection path from the first resistor group to the second reference voltage source. A third resistor group having connecting means for connecting both ends to a second reference voltage source, and the connecting path is shifted by a combination of the connecting means of the second and third resistor groups, and is taken out from the ladder tap. It is characterized in that the analog voltage applied is changed in steps of 2 ^nm .

A resistance ladder of the second invention is a resistance ladder of the first invention, wherein a connecting means for connecting one end of the second resistance group to the first reference voltage source and one end of the third resistance group are connected to each other. Two
The connecting means for connecting to the reference voltage source is omitted, and both ends of the resistance ladder are always connected to the first and second reference voltage sources.

In the resistance ladder of the third invention, the number of the second and third resistance groups in the first invention to be inserted in the connection path from the first resistance group to the first or second reference voltage source is ( 2 ^nm
-1) The number of resistance values R / 2 reduced from one by one
^It consists of a resistor string in which ^nm resistors are connected in series and a resistor string in which one resistor is connected (2 ^nm-
1) It is characterized in that a resistance row of the row is provided.

In the resistance ladder of the fourth invention, the number of the second resistance group in the first invention to be inserted in the connection path from the first resistance group to the positive analog voltage source is decreased from 2 ^{nm by} one. and the number of the resistance value R / 2 ^nm resistor string of 2 ^nm string consisting a resistor from resistor array connected in series to each and the third resistor groups, from the first resistance group to the negative analog voltage source the number to be inserted into the connection path (2 ^nm -1) a resistor string connected in series to each one by one reduced so the number of resistance value R / 2 ^nm of resistance from pieces (2 ^nm -1) column It is characterized in that a resistor train of is provided.

In the resistance ladder of the fifth invention, each of the plurality of resistances of the first resistance group of the resistance ladders of the first to fourth inventions comprises a plurality of unit resistances having substantially the same resistance value. Each of the resistors constituting the second and third resistor groups is connected in series, and a plurality of unit resistors are connected in parallel so that the resistance value becomes R / 2 ^nm .

In the resistance ladder of the sixth aspect of the invention, a plurality of resistors are connected in series and the total resistance value is (2 ^m −1) · R, the connection point between the resistors and the resistance string. A first resistance group having 2 ^m ladder taps for extracting a divided voltage value of a potential difference between the first and negative analog voltage sources generated at one end and at least a substantial resistance value (2 ^m −1)・ 3R /
Less than (2 ^{m + 1} −3) and (2 ^m −1) · R / (2 ^{m + 1}
-1) A resistor that is not less than or equal to one, a connecting unit that generates the resistor between the first resistor group and the positive analog voltage source, a resistor having a substantial resistance value less than the resistor, and the resistor that is the first resistor. A second resistance group having connection means for generating between the first resistance group and the positive analog voltage source, and capable of selecting the resistance value generated between the first resistance group and the positive analog voltage source in 2 ^nm steps. , A connecting means for connecting at least the first resistance group and the negative analog voltage source 2, a resistance having a substantial resistance value less than R and not 0, and the resistance as a first resistance group and a negative analog voltage source. And a third resistance group capable of selecting a resistance value generated between the first resistance group and the negative analog voltage source in 2 ^nm steps, and a second and a third resistance group. The connection route is changed by combining the connection means of the resistor groups of And wherein the changing the log voltage to 2 ^nm step.

In the resistance ladders of the first to fourth and sixth inventions, 2 ^nm of the resistance of the second resistance group is inserted between the first resistance group and the first reference voltage source, and the first resistance group is inserted. In the connection state in which the resistance of the third resistance group is not inserted between the resistance group and the second reference voltage source, the voltage between the first and second reference voltage sources is 2
^A divided voltage value of ^m steps is obtained, and (2 ^nm -1) resistors are inserted between the first reference voltage source and one resistor between the second reference voltage source and the second reference voltage source. Then, an analog output obtained by adding 1/2 ⁿ of the potential difference between the first and second reference voltage sources to the analog voltage in the above-mentioned connected state is obtained.
The number of resistors inserted between the second reference voltage source and the second reference voltage source is reduced by one, and the number of resistors inserted between the second reference voltage source and the second reference voltage source is reduced by one.
Whenever the number increases, an analog output is obtained from the ladder tap by adding the voltage of 1/2 ⁿ of the potential difference between the first and second reference voltage sources to the analog voltage at the time of m-bit conversion. ^A voltage division value of ^m · 2 ^nm = 2 ⁿ steps can be obtained with a small number of resistors and connecting means, and the resistance ladder of the second invention can obtain a similar voltage division value with a smaller number of parts than the first invention.

In the resistance ladder of the fifth invention, the resistance of the second resistance group in which unit resistances having substantially the same resistance value are connected in parallel between the first resistance group and the first reference voltage source are Two
^In a connection state in which ^nm sets are inserted and the resistance of the third resistance group is not inserted between the first resistance group and the second reference voltage source, 2 ^m between the first and second reference voltage sources The divided voltage value of the step is obtained, (2 ^nm −1) sets of resistors in which unit resistances are connected in parallel with the first reference voltage source are inserted, and the unit resistance is connected with the second reference voltage source. When one pair of resistors connected in parallel is inserted, the first analog voltage
And an analog output to which a voltage of 1/2 ⁿ of the potential difference between the second reference voltage source is applied is obtained, and hereinafter, a set of resistors in which unit resistors inserted in parallel with the first reference voltage source are connected in parallel. Whenever the number of sets decreases by one and the number of sets of resistors connected in parallel with the second reference voltage source increases by one, the ladder tap changes to the analog voltage at m-bit conversion. 1
And an analog output to which a voltage of 1/2 ⁿ of the potential difference between the second reference voltage source is applied is obtained, and as a result, 2 ^m · 2 ^nm =
A partial pressure value of 2 ⁿ steps is obtained. In the resistance ladder of the fourth aspect of the present invention, the unit resistances having substantially the same resistance value are connected in series or in parallel to form the first to sixth resistance groups. Even if there is a manufacturing variation in the resistance, as long as the resistors have the same shape, the variation tendency of the total resistance is the same. Therefore, a resistor with a resistance value of R / 2 ^nm should be formed accurately. Can
As a result, an accurate analog voltage can be obtained.

A DA converter according to a seventh aspect of the present invention is the first through sixth aspects.
And either of the resistor ladder of the invention, from among the 2 ^m pieces of the ladder taps of the first resistor group of the resistor ladder, one should take out the analog voltage corresponding to the digital value of the upper m bits of the n bits Selectively combining the means for selecting the ladder tap and the connecting means for the second and third resistor groups depending on whether the upper m bits are converted or the lower (nm) bits are converted, A resistance value of 2 ^m · R is generated between the first and second reference voltage sources by adjusting the number of resistors inserted in the connection path from the first resistance group to the first and second reference voltage sources. In the case of forming a connection path and converting lower (n−m) bits, a control means for forming the connection path while selecting a ladder tap for extracting an m-bit analog voltage at the time of m-bit conversion is provided. When converting to m-bit by changing the route It is characterized in that the analog output from the selected ladder tap changes in 2 ^nm steps.

In the DA converter of the seventh invention, 2 ^nm resistors are inserted in the connection path from the first resistor group to the first reference voltage source at the time of analog conversion of the upper m bits, and Two
Without connecting a resistor to the connection path to the reference voltage source of, the connection path may be formed to obtain the divided value of the potential difference between the first and second reference voltage sources in 2 ^m steps. After selecting one ladder tap from which a corresponding analog output can be obtained and performing m-bit digital conversion, when converting the lower (nm) bits, the ladder tap selected during m-bit conversion remains selected (m + 1 ) A connection path is formed by selectively connecting the connection means according to the digital value of the bit, and 1/2 ^{m + 1} of the potential difference between the first and second reference voltage sources is added to the analog voltage at the time of m-bit conversion. Is taken as a unit and an analog output to which a voltage corresponding to the digital value of the (m + 1) th bit is applied is taken out, and the connection path is changed to the lowest order according to the digital value. analog To conversion.

The AD converter of the eighth invention is the n-type converter of the seventh invention.
A D-A converter having a bit resolution and a tentative digital value in which a tentative value is set in order to obtain a reference analog voltage for comparison for digitally converting an analog input are given to the D-A converter, and further lower (n -M) when converting bits, DA
A ladder tap selected during m-bit conversion by changing the connection path from the first resistance group to the first and second reference voltage sources based on the comparison result between the analog output of the converter and the analog input of the conversion target. And a second control means for changing the analog output from at least (nm) times.

The AD converter of the eighth invention is the D-converter of the seventh invention.
-The analog output from the A converter is used as a reference analog voltage for comparison with the analog input to be converted, and during digital conversion of the upper m bits, the potential difference of 2 ^m steps between the first and second reference voltage sources. D- is the connection path for obtaining the pressure value.
The A-converter is formed to give a temporary digital value in which a temporary m-bit digital value is set to give a temporary digital value to the DA converter for analog conversion, and the analog output from the DA converter and the conversion target The analog input is compared with a comparator, the m-bit digital value corresponding to the analog input to be converted is determined according to the comparison result, and (n−m) bits are converted when the lower (n−m) bits are digitally converted. A temporary digital value obtained by setting a temporary value to the digital value of is given, and the connection path is changed at each conversion of each bit with the ladder tap selected at the time of m-bit conversion being selected, and at least (n− m)
Once, the analog output from the ladder tap is changed, and the analog input to be converted is finally converted into an n-bit digital value with a small number of parts.

An AD converter according to a ninth aspect of the present invention is the first to sixth aspects.
Any of the resistor ladder of the invention, from among the 2 ^m pieces of the ladder taps first resistor group of the resistor ladder has, one should take out the analog voltage corresponding to the digital value of the upper m bits of the n bits Means to select ladder taps,
Also, by selectively combining the connecting means of the second and third resistance groups, the analog voltage of 2 ^m stages taken out from the ladder tap is set to 1 of the potential difference between the first and second analog voltage sources.
/ 2 ⁿ voltage is added as an offset, and
A digital-analog (D) including first control means forming a connection path to the first and second reference voltage sources in which a resistance value of 2 ^m · R is generated between the first and second reference voltage sources. -A)
It is characterized by having a converter.

An A / D converter of a ninth aspect of the invention is a DA tap of the resistor ladder of any one of the first to sixth aspects of the invention, which is taken out from a ladder tap between the first and second reference voltage sources.
A connection path is formed such that an offset in units of 1/2 ⁿ of the potential difference between the first and second reference voltage sources is added to the ^m- stage analog voltage, and the analog input to be converted is converted into an m-bit analog signal. Convert to digital value. Therefore, 1 LSB
Even analog inputs with offsets within the range can be converted accurately.

An AD converter according to a tenth aspect of the present invention is the resistance ladder according to any one of the first to sixth aspects of the present invention, which is capable of obtaining a voltage division value of 2 ⁿ steps of the potential difference between the first and second reference voltage sources. From 2 ^m resistance ladders (where n> m) ladder taps, an analog voltage corresponding to a digital value of p bits [where m ≧ p] of the upper m bits of n bits is extracted (2 ^p −1) means for selecting one ladder tap,
And when converting the upper m bits, or the lower (n-
m) The connecting means of the second and third resistance groups is selectively combined depending on whether to convert bits, and a resistance value of 2 ^m · R is generated between the first and second reference voltage sources. Comparing a digital-to-analog (D-A) converter with first control means forming a connection path to the first and second reference voltage sources, and an analog output from the D-A converter with the analog input. (2 ^p −1) comparators, and the ladder tap from which the highest voltage is taken out of the ladder taps from which the voltage lower than the analog input is taken at the final stage of the m-bit conversion is converted to the lower (nm) bit. Ladder tap selection means to be selected as a ladder tap used for the
Until m bits are reached in bit units, provisional digital values in which provisional values are set in order to obtain a reference analog voltage for digital conversion of analog inputs are sequentially given to the D / A converter and analogized in p bit units. The conversion is repeated, and each time analog conversion is performed, the comparator compares the analog output from the DA converter with the analog input, performs digital conversion in p-bit units, and further performs lower-order (nm) bit digital conversion. In this case, the ladder tap selection means selects the temporary digital value in which the temporary value is set in order to obtain the reference analog voltage for comparison for digitally converting the lower (n−m) bits to the DA converter. any was an analog output from the ladder taps, at least a second control means for changing (n-m) times, ladder tap selection means (2 ^p -1) pieces of analog output If not selected, i.e., the lower case conversion result of the upper m bits were all "0" (n-m)
Means for selecting a ladder tap used for bit conversion from (2 ^p -1) analog outputs.

In the AD converter of the tenth aspect of the invention, when converting the upper m bits of the n bits, the potential difference between the resistance ladder and the first and second reference voltage sources is 2%. ^A connection path is formed in which a divided voltage value of ^m levels is obtained, and a p-bit digital value is set to a D-value by setting a temporary value to the n-bit digital value for every p bits from the upper n bits. The analog output from the (2 ^p -1) ladder taps output from the A converter is compared with the analog input of the conversion target, respectively, and the conversion target of any of the voltage ranges specified by the analog output of each ladder tap is compared. The upper m bits are digitally converted in p-bit units while sequentially narrowing down whether analog inputs are included, and selected at the final stage of m-bit conversion when converting the lower (nm) bits (2 ^p -1)
The number of ladder taps, that is, the values for m bits are determined, and the voltage range in which the analog output corresponding to the n-bit digital value whose lower (n−m) values are all “0” is included is determined. Of the ladder taps shown, a ladder tap lower than the analog input to be converted and having the highest voltage value extracted is selected as a ladder tap for converting lower (nm) bits, and the lower (n−m) is selected. m) The digital value of the bit is set to a temporary digital value, the connection path is changed for each conversion of each bit, and at least (n-
m), change the analog output from the ladder tap,
The final analog input to be converted is n with a small number of parts.
Convert to digital value of bits. At this time, the lower order (n-
m) At the time of bit conversion, all m-bit values are “0”, that is, the analog outputs of (2 ^p −1) ladder taps are all higher voltage values than the analog input to be converted,
If no ladder tap is selected, a ladder tap for lower (nm) bit conversion is selected.

The test method of the AD converter of the eleventh invention is as follows.
The test of 2 ^m points to test each of the ladder taps taken out different analog output of 2 ^m stages, by changing the connection path, the ladder tap changes 2 ^nm stage analog voltage units corresponding to 1/2 ⁿ bits Is performed for each ladder tap that extracts an analog output corresponding to the m-bit minimum digital value and the maximum digital value or for a ladder tap near the ladder tap.
By performing the accuracy test of ^nm −1) points, a test corresponding to 2 ⁿ points is performed, the test time is significantly shortened, and the manufacturing cost of the AD converter is reduced.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings showing its embodiments. [Embodiment 1] FIG. 1 is a circuit diagram showing a configuration of a D-A converter having an n-bit resolution using a resistance ladder which is an embodiment of the present invention. In this embodiment, n = 6 and m = 4 and 1/2 · LSB correction is not performed. In the figure, 1
Is a positive analog voltage source, 2 is a negative analog voltage source,
The resistance ladder arranged between the positive analog voltage source 1 and the negative analog voltage source 2 is composed of three resistance groups 17, 18, and 19. The DA converter of the present embodiment selects the ladder tap by the upper first m bits of the n bits in the first resistance group 17 at the center, and the value of the lower (n−m) bit [= lower 2 bits]. The connection path to the positive and negative analog voltage sources 1 and 2 is shifted in accordance with the above, and the voltage of the ladder tap determined up to m bits is changed in 2 ^nm steps to ^convert the analog voltage corresponding to the n-bit digital value to analog. It is output to the output 8.

In the first resistor group 17, (2 ^m −2) [= 14] resistors 4 each having a resistance value R are connected in series, and the resistors 4 connected in series are connected to the end of the negative analog voltage source 2 side. Is resistance 51
However, the resistor 52 is connected to the end on the positive analog voltage source 1 side. The two resistors 51 and 52 divide the resistance value R into two, and in the present embodiment, since the 1/2 LSB is not corrected, the resistance value of the resistor 51 is the same as that of the resistor 4, and the resistance value of the resistor 52 is Since the resistor 51 has the same resistance value as the resistor 4, it is equal to 0Ω,
The total resistance value is (2 ^m −1) · R. Each resistor 4, 5
Ladder taps 11, ..., 14 are connected between the terminals 1, 52 and the connection terminal of the resistor 51 on the negative analog power supply 2 side, respectively, and the total number of ladder taps is 2 ^m [= 16]. Note that only some of the ladder taps 11 to 14 are shown in the drawing.

The second resistor group 18 has a resistance value R / 2.
2 ^nm [= 4] resistances 53 of ^nm [= 1/4 · R] are connected in series, and one end of the series-connected resistances 53, 53, ... Is connected to the resistance 52 of the first resistance group 17. The other end is connected to the positive analog voltage source 1 via the connecting means 24. Further, the middle of each resistor 53 is connected to the connecting means 21, 22, 2
3 to the positive analog voltage source 1, respectively.

The third resistor group 19 has a resistance value R / 2.
The resistance 53 of ^nm [= 1/4 · R] is (2 ^nm −1) [=
3] are connected in series, and the resistor string 5 is connected in series.
One end of 3, 53, ... Is connected to the resistor 51 of the first resistance group 17, is connected to the negative analog voltage source 2 via the connecting means 34, and the other end is connected to the negative analog voltage via the connecting means 31. It is connected to the voltage source 2. Further, the middle of each resistor 53 is connected to the negative analog voltage source 2 via connecting means 32, 33, 34, respectively.

The ladder taps 11 of the first resistor group 17,
…, 14 has 2 ^m [= 16] ladder taps 11,
…, 14 out of 1 analog voltage, analog output 8
A switching tree 78 for selectively outputting as is connected. Connection means 21 to 24 of the second resistor group 18,
And the connection means 31 to 34 of the third resistance group 19 are controlled by the control signals e to l given from the n-bit control circuit 80 which is the first control means, so that the second resistance group 18 and the third resistance group 19 are connected. In each case, ON / OFF is controlled so that any one of the connecting means is in the connected state. Also, n
The bit control circuit 80 sends 2 to the switching tree 78.
The control signals for m bits are generated via the m control signal lines to determine the digital value of the upper m bits, and the connection means 21 to 24 to the positive analog voltage source 1 and the negative analog voltage source 2 are generated. To generate control signals e to l with the connection means 31 to 34.

Next, the operation of analog conversion of the D / A converter having the above configuration will be described. When converting a 6-bit digital value to analog, first, the n-bit control circuit 80 makes the control signals h and 1 significant to convert the upper 4 bits of the 6-bit to analog, and the connecting means 24 and 3.
While 4 is connected, a control signal according to the digital value of the upper 4 bits is given to the switching tree 78 via 2 · m control signals to turn on the corresponding switch of the switching tree 78 to turn on the switching tree 78. Is the ladder tap 1 of the first resistor group 17 for extracting the analog output corresponding to the digital value of the upper 4 bits.
Select from 1, ..., 14. For example, when the switching tree 78 selects the ladder tap 13, the voltage of the ladder tap 13 is output as the analog output 8.

Next, the n-bit control circuit 80 keeps the switching tree 78 selecting the ladder tap 13 and keeps the control signals e to e in accordance with the digital value of the lower 2 bits.
Any one of g and any one of the control signals i to k is made significant to connect means 21 to 2 of the second and third resistance groups 18 and 19.
A combination of 3 and 31 to 33 forms a connection path to the first and second analog voltage sources 1 and 2. That is, the bottom 2
When the digital value of the bit is "00", the control signals h and l
To make the connecting means 24 and 34 in the connected state,
In the case of 1 ", the control signals g and k are made significant and the connecting means 2
In the case of "10", the control signals f and j are made significant and the connecting means 22 and 32 are brought into the connected state, and in the case of "11", the control signals e and i are made significant and the connecting means 21 and 31 are connected to form a connection path between the positive analog voltage source 1 and the negative analog voltage source 2.

In the connection path formed as described above,
4 [= 2 ^nm ] resistors 53 of the second resistor group 18 are inserted between the first resistor group 17 and the positive analog voltage source 1 to ^connect the first resistor group 17 and the negative analog voltage source 2. In a connection state in which the resistor 53 of the third resistor group 19 is not inserted between,
With the analog output of the lowest ladder tap 15 set to zero, a voltage division value of 16 [= 2 ^m ] steps between the positive and negative analog voltage sources 1 and 2 can be obtained. 3 [= (2 ^nm −1)] resistors are inserted between the positive analog voltage source 1 and one resistor between the negative analog voltage source 2 and the positive analog voltage source 1. Positive and negative analog voltage sources 1 and 2 are added to the connected analog voltage in which four resistors 53 are inserted between
An analog output is obtained by applying a voltage of 1/64 [= 1/2 ⁿ ] of the potential difference between the two. In the state where 2 [= (2 ^nm −2)] resistors are inserted between the positive analog voltage source 1 and 2 resistors between the negative analog voltage source 2 and the positive analog voltage source 1, Positive and negative analog voltage sources 1 and 2 are added to the connected analog voltage in which four resistors 53 are inserted between
An analog output with a voltage of 2/64 [= 2/2 ⁿ ] of the potential difference between them is obtained. In the state where 1 [= (2 ^nm −3)] resistors are inserted between the positive analog voltage source 1 and 3 resistors are inserted between the negative analog voltage source 2 and the positive analog voltage source 1, The positive and negative analog voltage sources 1 and 2 are added to the connected analog voltage in which four resistors 53 are inserted between
An analog output with a voltage of 3/64 [= 3/2 ⁿ ] of the potential difference between the two is obtained.

In other words, the voltage value of the ladder tap 13 selected by the digital value of the upper 4 bits is 1/2 ⁶ of the potential difference between the positive and negative analog voltage sources 1 and 2 [=
A voltage of 1/2 ⁿ ] is applied to generate a voltage division value of 4 [= 2 ^nm ] stages in the ladder tap 13. For example, when the potential difference between the positive and negative analog voltage sources 1 and 2 is 3.20V, this potential difference 3.20V is 16 [=
2 ^m ], and the potential difference between adjacent ladder taps becomes 200 mV. Therefore, the analog output 8 is 200 mV when the second lowest ladder tap 13 is selected when the m-bit conversion is completed. The analog conversion of the lower 2 bits is performed by halving the potential difference between the positive and negative analog voltage sources 1 and 2 to the voltage value 200 mV of the ladder tap 13 selected at the time of the analog conversion of the upper 4 bits.
⁶ Lower 2 in units of [= 2 ⁿ ] voltage [= 50 mV]
Add a voltage according to the digital value of the bit, 4 [=
A partial pressure value of 2 ^nm ] is generated in the ladder tap 13.
At this time, the analog output 8 when the lower 2 bits are “01” is 250 mV, the analog output 8 when it is “10” is 300 mV, and the analog output 8 when it is “11” is 350 mV.
It becomes mV.

[Embodiment 2] FIG. 2 is a circuit diagram showing the structure of a DA converter of n-bit resolution using a resistance ladder which is an embodiment of the present invention. Note that, as in the first embodiment, n
= 6, m = 4, 1/2 LSB correction is not performed, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The present embodiment is different from the first embodiment in that the resistor series 53, 53, ... Of the second resistor group 28 are located between the positive analog voltage source 1 side end and the positive analog voltage source 1.
Is that no connecting means is provided between the negative analog voltage source 2 and the end of the resistor group 53 of the resistor group 29 on the negative analog voltage source 2 side.

The operation of the D / A converter of this embodiment is almost the same as that of the first embodiment, but the difference from the first embodiment is that the n-bit control circuit 80 converts positive and negative analog voltage sources 1 and 2. Control signal l at the time of forming the connection path of
To make the connection means 34 in a connected state, and when the lower 2 bits are converted, the digital value of the lower 2 bits is "0".
In the case of "0", the control signal 1 is made significant to bring the connecting means 34 into the connected state, and in the case of "11", the control signal e is made significant to bring the connecting means 21 into the connected state.

Since the series resistance ladder in which all the resistance groups of the first to third resistance groups 17, 28 and 29 are connected is always connected to the positive analog voltage source 1 and the negative analog voltage source 2, Positive analog voltage source 1 and negative analog voltage source 2
The connection route to the connection means 21 to 23, 32 to 3 is selected.
However, since the connection means 21 to 23 and 32 to 34 have a lower resistance value than the resistance 53, the positive analog voltage is higher than the resistance value of the connection path formed by the combination. The resistance value of the path in which all the resistance groups are constantly connected to the source 1 and the negative analog voltage source 2 is sufficiently high,
The connection path selected by the combination of the connection means 21-23 and 32-34 dominates the resistance value between the positive and negative analog voltage sources 1 and 2. Therefore, when the accuracy expected of the resistance ladder has some margin, the resistance ladder having the configuration of the present embodiment can further reduce the number of circuit elements as compared with the resistance ladder of the first embodiment.

[Embodiment 3] FIG. 3 is a circuit diagram showing the structure of a DA converter of n-bit resolution using a resistance ladder according to an embodiment of the present invention. Note that, as in the first embodiment, n =
6, m = 4, 1/2 LSB correction is not performed, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The second embodiment is different from the first embodiment in that
The configuration of the resistance group 38 and the third resistance group 39 is the same as that of the first embodiment, and the description thereof is omitted.

The second resistor group 38 has 3 [= (2 ^nm-
1)] Resistors of 3 [= (2 ^nm −1)] columns in which resistors 53 each having a resistance value of R / 2 ^nm are respectively connected in series, each of which is sequentially reduced from one to one. Columns,
And connecting means 21 for selectively connecting one end of each of these resistor strings individually and commonly connecting the other end to the positive analog voltage source 1.
24, and the other end of the resistor string has a resistor 5 with a resistance value of R / 2 ^nm .
3 are commonly connected to the first resistor group 17.

Each of the third resistor group 39 has a resistance value R.
/ 2 ^nm resistances starting from 3 [= (2 ^nm -1)] and decreasing to 1 by 1 each, 3 [= (2 ^nm -1)] columns connected in series Resistor series, and connection means 31 to 3 for selectively connecting one end of each of these resistor series individually or commonly connecting the other end to the negative analog voltage source 2.
4, the other end of the resistor string is commonly connected to the first resistor group 17.

[Embodiment 4] FIG. 4 is a circuit diagram showing a structure of a DA converter of n-bit resolution using a resistance ladder according to an embodiment of the present invention. Note that, as in the first embodiment, n =
6, m = 4, 1/2 LSB correction is not performed, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The second embodiment is different from the first embodiment in that
The configuration of the resistance group 48 and the third resistance group 39 is described. Since the resistance group 39 is the same as that of the third embodiment and the operation is the same as that of the first embodiment, the description thereof is omitted.

The second resistance group 48 has a resistance value R, respectively.
The number of / 2 ^nm resistors starting from 4 (= 2 ^nm ) and decreasing to one by one, each of the 2 ^nm series of resistors connected in series, and each end of the series of resistors individually Connection means 21 to selectively connect to the positive analog voltage source 1
24, and the other end of the resistor string is commonly connected to the first resistor group 17.

By the way, in the above first to fourth embodiments, the connecting means 2 to the positive analog voltage source 1 and the negative analog voltage source 2 is used.
1 to 24, 31 to 34 are assumed to have no resistance component, but in the case of manufacturing an LSI, these connecting means are mainly composed of MOSFETs, and their M
The specific resistance between the source and drain of the OSFET is usually
Since it is known at the stage of designing the circuit, the linearity error due to the intrinsic resistance of the transistor can be eliminated by subtracting the intrinsic resistance of the transistor from the resistors 51 and 52 or 53 located at both ends of the first resistor group. Is possible. Further, it is ideal that all the connecting means 21 to 24 and 31 to 34 have the same resistance value and are designed to be at least lower than the resistance 53 and to have an extremely low resistance value. All the analog voltages generated by the ladder have good linearity.

In addition, the first resistor group 17 is connected to the second resistor group 2
8 and the third resistance group 19, or the first resistance group 17 and the second resistance group 28 and the third resistance group 39 in combination, the same effect as the first embodiment can be obtained. It goes without saying that it will be done.

When a voltage equal to that of the positive analog voltage source 1 is required as the analog output, the positive analog signal can be easily obtained by setting all the connecting means 31 to 34 to the negative analog voltage source 2 in the non-connection state. A voltage equal to that of the voltage source 1 can be obtained. Similarly, when a voltage equal to that of the negative analog voltage source 2 is required, the connecting means 21 to 2 to the positive analog voltage source 1 are connected.
A voltage equal to that of the negative analog voltage source 2 can be easily obtained by making all 4 unconnected.

[Embodiment 5] FIG. 5 is a circuit diagram showing the structure of a DA converter of n-bit resolution using a resistance ladder according to an embodiment of the present invention. Note that, as in the first embodiment, n =
6, m = 4, 1/2 LSB correction is not performed, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The first embodiment is different from the first embodiment in that
The resistance group 17 of the unit resistance 5 of the resistance value R / 2 is 2 ((2
^m −1) connected in series, 2 ^m ladder taps 11,
, 14 are connected between both ends of the resistor series 5, 5, ... Connected in series and between every two resistors 5, and the second resistor
In the third resistance groups 18 and 19, 2 [= 2 ^{nm / 2} ] unit resistances 5 each having a resistance value R / 2 are connected in parallel to realize a resistance value R / 2 ^nm in pairs. That is the point.

When a resistor is formed in the LSI manufacturing process, the resistor has some variations in the width of the resistor, the area of through holes for connecting to the conductor, the through hole interval, the contact resistance, and the like. However, as long as they all vary on the same chip, they do not have a great influence on the partial pressure value generated by the resistance ladder. Therefore, the resistance ladder may be configured with the resistance having the smallest resistance value as the unit resistance. For example, when the entire resistance ladder is designed with the resistance 53 having the smallest resistance value as the unit resistance in the first embodiment, the resistance 4 Is to connect four resistors 53 in series, or to design the resistor width to be 1/4. In this case, even if the resistor 53 has a small area, the resistor body needs a through hole to be connected by a conductor, and the second resistor group 18 and the third resistor group 19 can be configured with a small area. But the first resistor group 17
Area increases. Further, when the width of the resistor is set to 1/4, even if the variation is on the same chip, the proportion of variation in the width becomes large, so that it becomes difficult to obtain a product with stable performance.

In view of the above, in the present embodiment, the resistance value of the unit resistance having the minimum resistance value is R / 2, and the resistance 5 is connected in parallel to obtain the resistance having the value of R / 2 ^nm . It constitutes a highly accurate resistance ladder.

[Embodiment 6] FIG. 6 is a circuit diagram showing a configuration of a DA converter having an n-bit resolution using a resistance ladder according to an embodiment of the present invention. Further, n = 6 and m = 4, the same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. This embodiment is different from the fourth embodiment in the resistance values of the resistances of the second resistance group 58 and the third resistance group 49. Since the other configurations are the same as those of the first embodiment, the description thereof will be omitted. .

The second resistor group 58 has a resistance value of (2 ^m −
1) ・ 3R / (2 ^{m + 1} -3) or less, and (2 ^m -1) ・
A resistance 54 not lower than R / (2 ^{m + 1} −1), a resistance 57 whose resistance value is less than that of the resistance 54, a resistance 55 whose resistance value is less than that of the resistance 57, and a resistance value Resistance 55
Through the resistor 54 and the resistor 56 which is less than the resistance value of 0 and is not 0, and the first resistor group 17 and the positive analog voltage source 1 when the lower nmb (= 2) bit of the digital value is "00". The connecting means 24 for connecting, the connecting means 23 for connecting the first resistor group 17 and the positive analog voltage source 1 via the resistor 57 when the lower 2 bits of the digital value are “01”, and the lower order of the digital value. The connecting means 22 for connecting the first resistor group 17 and the positive analog voltage source 1 via the resistor 55 when the 2 bits are "10", and the first when the lower 2 bits of the digital value are "11". 1 has a resistor group 17 and a positive analog voltage source 1 via a resistor 56 and a connecting means 21.

The third resistor group 49 includes a resistor 61 having a resistance value less than R and a resistor 5 having a resistance value less than that of the resistor 61.
9, a resistor 60 whose resistance value is less than the resistance value of the resistor 59 and is not 0, and a connection which connects the first resistor group 17 and the negative analog voltage source 2 when the lower 2 bits of the digital value are "00". Means 34 and the lower 2 bits of the digital value are "01"
Connection means 33 for connecting the first resistor group 17 and the negative analog voltage source 2 via the resistor 60, and the first resistor group 17 when the lower 2 bits of the digital value are "10".
And the negative analog voltage source 2 via a resistor 59, and the first resistor group 17 and the negative analog voltage source 1 when the lower two bits of the digital value are "11". It has the connection means 31 connected via.

In the DA converter configured as described above, 64 (= 2 ⁿ ) different voltages are obtained with the negative analog reference voltage source 2 as a reference, so that the error of the voltage of each ladder tap from the theoretical value is obtained. Within the theoretical voltage step width, that is, D−
It must be installed within 1 LSB of the A converter. For example,
In the figure, when all the upper m (= 4) bits are “1”, the ladder tap 11 is selected, and when the lower 2 bits are also “0”, the theoretical value of the voltage obtained from the ladder tap 11 is It is (2 ^m −1) / 2 ^m times the potential difference between the positive analog voltage source 1 and the negative analog voltage source 2. In this state, up to the voltage corresponding to the value of the ladder tap 12, there is no ladder tap that can be specified by the upper 4 bits. This is an allowable range for the tap 11. However, when the resolution of m bits or more is intended, the theoretical values when the ladder tap 11 or the ladder tap 12 is selected and the lower 2 bits are “10” are the positive and negative analog voltage sources 1 and 2. Of the potential difference between (2
It should be within ^{m + 1} -3) / 2 ^{m + 1} times to (2 ^{m + 1} -1) / 2 ^{m + 1} times. Therefore, the resistance value R ₅₄ of the resistor ₅₄
R ₅₄ <(2 ^m −1) · 3R / (2 ^{m + 1} −3) (1) and R ₅₄ > (2 ^m −1) · R / (2 ^{m + 1} −1) (2) ). Also, a resistor 54 for obtaining a voltage between the ladder tap 11 and the ladder tap 12 by the lower 2 bits,
The relationship among the resistance values R ₅₄ , R ₅₅ , R ₅₆ , and R ₅₇ of ₅₅ , ₅₆ , and ₅₇ is R ₅₄ > R ₅₇ > R ₅₅ > R ₅₆ > 0Ω (3).

In the figure, when all the upper 4 bits are "0", the ladder tap 14 is selected,
When the lower 2 bits are “0”, the theoretical value of the voltage obtained from the ladder tap 14 is equal to the potential of the negative analog voltage source 2. At this time, a voltage lower than the theoretical voltage of the ladder tap 13 and higher than the negative analog voltage source 2 is an allowable range for the ladder tap 14. The relationship between the resistance values R ₅₉ , R ₆₀ and R ₆₁ of the resistors ₅₉ , ₆₀ and ₆₁ for obtaining the voltage between the voltages obtained from the ladder tap 14 and the ladder tap 13 by the lower 2 bits is R ₆₁ >. R ₅₉ > R ₆₀ > 0Ω (4).

As described above, from the equations (1) to (4), when strict precision is not required and only a multi-order resolution is to be obtained, the first Resistance group 17
It can be understood that if the structure of (1) is precise, the D-A converter with n-bit resolution can be obtained by the structure of the first to fourth embodiments. 11 and 13, the resistance values connected between the first resistor group 17 and the positive analog voltage source 1 and between the negative analog voltage source 2 in the circuits of Examples 1, 2, and 3 are Since they are equivalent, the connection means 21-
When 24, 31 to 34 form a connection path between the positive analog voltage source 1 and the negative analog voltage source 2 according to the operation shown in the first embodiment, The relations shown above hold, and the strict second and third
It is easy to understand that an accurate D-A converter can be obtained because the resistor group is constructed.

[Embodiment 7] FIG. 7 is a circuit block diagram showing the configuration of a successive approximation type AD converter using the DA converter of any of Embodiments 1 to 6. As in the first embodiment, n = 6 and m = 4, and 1/2 LSB correction is not performed. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. . In the figure, 90 is a DA converter according to any one of the first to fourth embodiments, in which the n-bit control circuit 100 as the first and second control means is a second and a third.
The control signals 201 and 202 for connecting or disconnecting the connecting means of the resistor groups 18 and 19 are applied to the DA converter 90 through the respective 2 ^nm signal lines, and the second resistor group 18 and Between the positive and negative analog voltage sources 1 and 2, the connecting means of the third resistor group 19 (the connecting means 24 and 34 of FIGS. 1 and 3 or the connecting means 34 of FIG. 2) is selectively connected. Two
A connection path is formed to the positive and negative analog voltage sources 1 and 2 so that the resistance value of ^m · R is formed, and the digital value of the upper m bits of the n bits is changed from the upper bit of the m bits to the temporary digital The analog output 8 from the DA converter 90 obtained by sequentially setting the values and the analog input 25 input from the outside through the input terminal AIN are compared by the comparator 16 and sequentially based on the comparison result signal 20. Determined sequentially by the approximation method.

Further, the n-bit control circuit 100 keeps selecting the ladder tap that outputs the analog voltage corresponding to the m-bit digital value selected at the time of converting the m-bit, and the lower (n- m) control signals 201 and 202 corresponding to the digital value in which a temporary value is set in the bit
To the DA converter 90, and the second resistor group 18 and the third resistor group 18
Is output from the ladder tap of the first resistor group 17 by selectively connecting the respective connecting means of the resistor group 19 and changing the connection path to the positive analog voltage source 1 and the negative analog voltage source 2. If the analog voltage is at least (n-
m) times, and then the analog output 8 from the DA converter 90 and the analog input 25 are compared to determine the digital value of the lower (n−m) bits by the successive approximation method.

Next, the digital conversion operation of the AD converter having the above-mentioned structure will be described with reference to FIGS. 8 and 11 are diagrams showing the state transition of the connection path of the resistance ladder of any one of the embodiments 1, 3, 4, 5 in which connection / disconnection of the connection means is controlled by the control signals e to l, FIGS. 9 and 1.
1 is a control signal e to l that causes the state transitions of FIGS.
2 is a timing chart of. For example, the ladder tap 13 which is selected as the one most approximated to the analog input 25 by the conversion result of the 4th bit when the digital conversion of the upper 4 bits is completed is the ladder tap 13 shown in FIGS. In this case, the analog voltage corresponding to the digital value “000100 ₂ ” is output from the analog output 8, and the potential difference between the positive analog voltage source 1 and the negative analog voltage source 2 is 3.2V. The voltage of the analog output 8 is 200 mV.

In the A-D conversion of the 5th bit, the digital value is temporarily set to "000110 ₂ ", and the ladder tap selected in the 4th bit is connected to the comparator 16 and 4
Connecting means 24 and 34 connecting the resistance ladder to the positive and negative analog voltage sources 1 and 2 by A-D conversion up to the bit-th bit.
Is disconnected, and the connection means 22 and 32 are connected to connect the positive and negative analog voltage sources 1 and 2 to the resistance ladder. At this time, the ladder tap 13 has two resistors 53 inserted on the negative analog voltage source 2 side at the same time as compared to the state at the end of conversion of the fourth bit (FIGS. 8A and 10A). Two resistors 53 on the side of the positive analog voltage source 1 are reduced (FIGS. 8B and 10B). Therefore, the voltage of the ladder tap 13 is 300 mV. The comparator 16 compares the voltages of the analog output 8 and the analog input 25 from the ladder tap 13 at this time. As a result of comparison between the analog output 8 and the analog input 25, if the voltage of the analog input 25 is higher, the 5th bit is set to “1”, and if the voltage of the analog output 8 is higher, the 5th bit is determined. Set to "0".

If the voltage of the analog input 25 is higher than that of the analog output 8 as a result of the comparison of the 5th bit, the digital value is temporarily set to "000111 ₂ " and the conversion to the 6th bit is started. A-D up to the 5th bit
The conversion means disconnects the connection means 22 and 32 that have connected the resistance ladder to the positive and negative analog voltage sources 1 and 2, and instead puts the connection means 21 and 31 into the connected state, and the positive and negative analog voltage source 1 , 2 and the resistance ladder are connected. At this time, the ladder tap 13 is in the state at the end of conversion of the fourth bit (see FIG. 8).
Compared to (a)), three resistors 53 on the positive analog voltage source 1 side are reduced, and at the same time, a resistor 53 on the negative analog voltage source 2 side.
3 are inserted (Fig. 8 (c)). Therefore, the voltage of the ladder tap 13 is 350 mV. Comparator 1
6 is the analog output from the ladder tap 13 at this time 8
And the voltage of the analog input 25 are compared. As a result of comparison between the analog output 8 and the analog input 25, the analog input 2
When the voltage of 5 is higher, the 6th bit is set to “1” and the 6-bit analog value becomes “000111 ₂ ”. When the voltage of analog output 8 is higher, the 6th bit is “0”. , And the 6-bit analog value is "000."
110 ₂ ".

On the other hand, if the voltage of the analog input 25 is lower than that of the analog output 8 according to the comparison result of the 5th bit, the digital value is temporarily set to "000101 ₂ " and the conversion to the 6th bit is started. A-up to the bit
Positive and negative analog voltage sources 1 and 2 for resistance ladder by D conversion
The connection means 22 and 32 connected to is connected to the positive and negative analog voltage sources 1 and 2 and the resistance ladder in place of the connection means 23 and 33. At this time, the ladder tap 13 is in the state at the end of conversion of the fourth bit (see FIG. 1).
0 (a)), the resistor 53 on the positive analog voltage source 1 side
1 is reduced, and at the same time, the resistance 5
One 3 is inserted (FIG. 10 (c)). Therefore, the voltage of the ladder tap 13 is 250 mV. The comparator 16 compares the voltages of the analog output 8 and the analog input 25 from the ladder tap 13 at this time. As a result of the comparison between the analog output 8 and the analog input 25, when the voltage of the analog input 25 is higher, the 6th bit is set to “1”, the 6-bit analog value becomes “000101 ₂ ”, and the analog output 8 If the voltage is higher, the 6th bit is set to "0" and the 6-bit analog value is "00".
0100 ₂ ".

Next, the conversion characteristics of the AD converter of the present invention will be described. Figure 12 (a) shows the conventional n-bit resolution A
FIG. 12B is a diagram showing the conversion characteristic of the −D converter, and FIG. 12B is a diagram showing the conversion characteristic of the AD converter of the present invention, showing the conversion characteristic of the lower 3 bits. FIG. 12B shows that after the AD converter of the present invention digitally changes from the lower bit to the third bit with an analog output corresponding to the upper m bits (the conversion characteristic is shown by a solid line), the lower (nm) ) The state in which the conversion characteristic is shifted depending on the digital value of bit [= 2 bits] is shown by a dotted line, a one-dot chain line, and a two-dot chain line. As is clear from the figure, the conversion points of all conversion characteristics are as shown in FIG.
It matches the conversion point of the conventional conversion characteristics shown in (a). This indicates that the DA converter of the present invention can obtain conversion characteristics equivalent to those of the conventional n-bit resolution AD converter with a small number of elements.

[Embodiment 8] FIG. 13 is a circuit block diagram showing the structure of a successive approximation type AD converter having the DA converter of any of Embodiments 1 to 6. In addition, Example 1
Similarly to the above, n = 6 and m = 4, the same parts as those in the first or seventh embodiment are designated by the same reference numerals, and the description thereof is omitted. The A / D converter of the present embodiment outputs a reference analog voltage for comparison with an analog input from the outside when the analog input to which an offset within 1 LSB is added is digitally converted. The offset is excluded from the A-D conversion result by adding an offset within 1 LSB in advance to the analog output of the device.

The present embodiment is different from the seventh embodiment in that at the beginning of conversion, the connecting means of the second and third resistor groups 18 and 19 are combined to connect to the first and second analog voltage sources 1 and 2. When forming the connection path, the nm bit control circuit 102, which is a part of the third and fourth control means, outputs the first and second analog voltage sources 1 to the output from the DA converter 90. , 2
The point is to form a connection path such that an offset in units of 1/2 ⁿ of the potential difference between them is added in advance. That is, nm
The bit control circuit 102 adds an offset to the analog voltage output from the ladder tap so that the output of the 2 ^mth ladder tap that outputs the lowest analog voltage of the 2 ^m- stage analog voltage becomes larger than zero. Such connection paths are provided by connecting means 21 to 23, 31 to 33 in the case of the resistance ladders of Examples 1, 3 and 4, and connecting means 21 to 23, 32 to 34 in the case of the resistance ladder of Example 2. Are formed in combination. The m-bit control circuit 101, which is responsible for the third and fourth control means together with the n-m-bit control circuit 102, has a D- path in which a connection path is formed in this way.
A control signal for m bits is given to the A converter 90, and m bits are digitally converted by the successive approximation method in the same procedure as in the fifth embodiment.

[Embodiment 9] FIG. 14 is a circuit block diagram showing the structure of an AD converter using a resistance ladder according to an embodiment of the present invention. FIG. 15 is an AD converter of FIG. 3 is a circuit diagram showing a detailed configuration of a part of FIG. As in the first embodiment, n = 6 and m = 4, and 1/2 LSB correction is not performed, and the same parts as those in the first or seventh embodiment are denoted by the same reference numerals. The description is omitted. A- of this embodiment
The D converter uses p [=
2] Digital conversion is repeated using a successive approximation method up to m bits in bit units, and the first p-bit conversion is performed between positive and negative analog voltage sources 1 and 2 between external analog inputs. The voltage range divided by 2 ^p stages of the potential difference is narrowed down roughly, and in the next p-bit conversion, the narrowed down voltage region is divided down into 2 ^p stages.

In the figure, 91 is one of the resistance ladders of one embodiment of the present invention, and is 3 out of 2 ^m steps of partial pressure value.
[= (2 ^p -1)] analog outputs 81, 82, 83
The selection switch group 79 is composed of switches 700 to 715 as will be described later in detail and is included in the 16 [= 2 ^m ] ladder taps of the first resistance group 17. To 3 [= (2 ^p -1)] ladder taps. The 6-bit control circuit 110 is n in the fifth embodiment.
It operates almost the same as the bit control circuit 100, but at the time of m-bit conversion, a digital value in which a temporary value is set in units of 2 bits from the upper 6 bits is given to the DA converter 91. The switch group control circuit 86 connects the corresponding ladder taps to the analog outputs 81, 82, 83 according to the n-bit digital value given from the 6-bit control circuit 110 serving as the fifth and sixth control means. Signal 84 of
The 0 + p bit selection switch 700, which will be described later, is turned on.
The signal 85 for turning off is output to the selection switch group 79.

The 3 [= 2 ^p ] comparators 16 have the three analog outputs 81, 82 and 83 as one input,
The analog input 25 from the outside is used as the other input. Comparators 16 and 1 when converting the upper 4 bits
Three comparison result signals 301, 302, 303 of 6, 16
Is output to the encoder 305, and the encoder 305 outputs 3
The two comparison result signals are encoded into a 2-bit digital value and output to the 6-bit control circuit 110. Further, the comparison result signals 301, 302, 303 from the comparators 16, 16, 16 at the time of conversion of the lower 2 bits are the multiplexer 30.
0, the multiplexer 300 outputs one comparison result signal selected from the three comparison result signals 301, 302, 303 to the 6-bit control circuit 110 as the lower bit conversion result output 304.

The selection switch group 79 divides the potential difference between the positive and negative analog voltage sources 1 and 2 into four levels by dividing the upper four of the 16 ladder taps into analog outputs 81 ,.
82, 83 connected normally open switch 701,
702 and 703, and each switch of each set is connected to the analog outputs 81, 82 and 83, respectively, in order to obtain the voltage division value of four steps of the potential difference of the voltage region narrowed down by the conversion of the 2-bit unit in the previous step 4 sets of normally open switches 704-70
6,707-709,710-712,713-715
, And if all of the conversion results of the upper 4 bits are “0”, the digital value is “0000”.
And a 0 + p bit selection switch 700 for causing the DA converter 91 to output the reference analog voltage at the time of converting the lower 2 bits when the analog input to be converted from the 0 ₂ "to the digital value" 000011 ₂ "is digitally converted. Consists of.

Next, the digital conversion operation of the A / D converter having the above configuration will be described. When converting from the most significant 2 bits, by turning on the switch 701, 702, 703, the analog output 81 "110000 _2", the analog output 82 "100000 _2", also in the analog output 83 "010000 ₂ “Ladder taps that output analog voltages respectively corresponding to” are connected to obtain the voltage division values of four steps of the potential difference between the positive and negative analog voltage sources 1 and 2. Next, the comparators 16, 16, 16 output the analog output 8
1, 82, 83 and the voltage of the analog input 25 are compared, and the 6-bit control circuit 110 determines that the comparison result signal 30
From the encoding result of the encoder 305 that encodes 1, 302 and 303, it is determined to which of the voltage regions the analog input voltage is divided into four steps, and the following 2
A signal for controlling ON / OFF of switches in bit conversion is given to the selection switch group 79.

For example, when the comparison result signals 301 to 303 are all "1", the analog input 25 is the analog output 8
Since the voltage is higher than 1, the 6-bit control circuit 110
Determines the 2-bit digital value from the most significant to be “11 ₂ ”. When the comparison result signal 301 is “0” and the comparison result signals 302 and 303 are “1”, the analog input 25 has a voltage higher than the analog output 82 and lower than the analog output 81. The digital value of is fixed to "10 _2. " Also, the comparison result signals 301, 3
02 is "0", when the comparison result signal 303 is "1", the analog input 25 is higher than the analog output 83, a digital value from the most significant two bits for a voltage lower than the analog output 82 "01 ₂ To be confirmed. When all the comparison result signals 301 to 303 are “0”, the analog input 25 has a voltage lower than that of the analog output 83, so that the 2-bit digital value from the most significant bit is fixed to “00 ₂ ”. In order to obtain these 2-bit digital values, the comparison result signals 301 to 303 are set to 2 by the encoder 305.
The result encoded into bits and replaced with 2-bit data is input to the 6-bit control circuit 101.

At the time of the next 2-bit conversion, four-step voltage division values in the voltage region narrowed down by the conversion result of the previous step are obtained.
If the most significant 2 bits are “11 ₂ ”, the switch 704-
706, switches 707 to 709 in the case of “10 ₂ ”,
In the case of “01 ₂ ”, switches 710 to 712, “0”
In the case of 0 ₂ ″, the switches 713 to 715 are turned on to connect the analog outputs 81, 82 and 83 to the ladder taps respectively. The analog outputs 81 to 83 are connected to the predetermined ladder taps.
Is connected, the analog value is compared with the analog input 25 as in the case of the most significant 2 bits, the digital value of the next 2 bits is determined, and the AD conversion result of the digital value of the upper 4 bits is obtained. At this time, the analog outputs 81, 82 and 83 are sequentially connected to the adjacent ladder taps.

When converting the lower 2 bits, the analog input 25 is generated by the comparison result signals 301 to 303 of the 3rd and 4th bits.
Of the analog outputs 81 to 83 of which the voltage is higher, the multiplexer 300 selects the comparison result signal 301 corresponding to the highest analog output 81, 82, 83, and the analog output 81 to be used at the time of conversion of the lower 2 bits or 82 or 83 is determined. At the same time, the comparison result outputs 301 to 303
305 that encodes the data into 2-bit data
Completes its action. Analog output 81 or 82 or 83
After selecting, the lower 2 bits are digitally converted by the successive approximation method in the same manner as the AD converters of the fifth and sixth embodiments to achieve 6 [= n] bits of AD conversion.

On the other hand, as a result of the comparison of the third and fourth bits, when the analog input 25 is not higher than any of the analog outputs 81, 82 and 83, that is, when the conversion results of the upper 4 bits are all "0", The 6-bit control circuit 110 causes the switch group control circuit 86 to output the signal 85 to the selection switch group 79, and the analog input 25 to be converted from the digital value “000000 ₂ ” to the digital value “000011 ₂ ”.
0 + p bit selection switch 700 provided for conversion
Is turned on, and the analog output 83 is connected to the resistance ladder.
In this way, the 0 + p bit selection switch 700 is
It is used only for A-D conversion in a voltage region where only bits can be "1".

The AD converter of this embodiment is characterized in that a switch for determining the lower p bits is provided. Although the 0 + p bit selection switch 700 is connected to the analog output 83 in the present embodiment, if the multiplexer 300 can perform control to select the analog outputs 81, 82 and 83 as the lower bit conversion result output 304 in a timely manner, There is no particular limitation, and the analog outputs 81 and 82 may be connected. Further, although the resistance ladder of any one of the first to sixth embodiments is used in the present embodiment, in addition to these embodiments, an A-D combined with a logic circuit capable of controlling the equivalent circuit of the first to sixth embodiments is used. It may be a converter. In the AD converter of the present embodiment configured as described above, the resistance ladder can be configured by a small-scale circuit as in the other embodiments, and the A / D converter of the conventional similar system can be used. The resolution can be expanded by adding one switch as compared with the switch group.

In all of the embodiments described above, the n-bit control circuit (including the m-bit control circuit, the n-m-bit control circuit and the 6-bit control circuit) is a conventional successive approximation type,
Alternatively, it is equivalent to a successive approximation (successive approximation) register used in an AD converter called a successive approximation type,
For the operation of the successive approximation type A / D converter, see “AD / D
-A conversion circuit design "(February 20, 1980, published by CQ Publishing Co., Ltd., page 11), etc.
It is introduced in the literature on converters, and can be easily configured with shift registers and flip-flops. Further, although no detailed control signal is disclosed for the n-bit control circuit, the comparator, the switch and the switch tree, the control method according to the prior art is equivalent to the A / D converter of the present invention.
In particular, the n-bit control circuit and the comparator operate to obtain a predetermined accuracy according to the control signal. The control signal required for AD conversion of the lower (n−m) bits can be easily generated by the logic circuit based on the signal generated in the AD conversion process described in the description of the embodiment.

The AD converter of the present invention has been described as sequentially performing conversion up to n bits. ) A predetermined accuracy can be obtained by a conversion method that obtains an approximate value by incrementing or decrementing bits.

Further, in this embodiment, the resistance ladder, DA
The configuration of the converter and the AD converter is described as a configuration in which the connecting means to the positive and negative analog voltage sources is built in the LSI, but the configuration of the analog voltage sources included in the second and third resistance groups is described. Even if the path to the connection means is provided outside the LSI and the analog voltage source outside the LSI is connected by means of a program or the like, the same effect as this embodiment can be obtained. Further, the connecting means at this time is not limited to the transistor, and may be a mechanical part such as a relay.

N-bit control circuit (m-bit control circuit, n
An m-bit control circuit, including a 6-bit control circuit) controls the switching tree and the means for connecting the resistance ladder to the positive and negative analog voltage sources, while the n-bit control circuit controls the switching tree and the analog voltage source. The data used to control the connection means to the conventional D-A converter or A
Needless to say, the value can be read out like the control circuit of the -D converter, and the n-bit control circuit controls the analog output voltage of the built-in DA converter,
The analog input voltage from the outside is converted into a digital value from the result of the comparison between the analog output voltage of the -A converter and the analog input voltage from the outside by the comparator.
It goes without saying that data can be written in the control circuit only for controlling the D-A converter, and the structure may be such that data can be read out as necessary.

The control circuit for controlling the A-D converter controls the upper m bits in the same manner as the conventional A-D converter, and controls the lower (n-m) bits in the positive and negative analog voltages. Any structure may be used as long as the connecting means for connecting the resistance ladder to the source is controlled by the combination based on the above-mentioned embodiment. For example, when n = 6 and m = 4, when converting the 5th bit,
The switching tree is fixed by the digital value determined by the conversion of the 4th bit, and in the conversion of the 5th bit, the analog voltage input to the comparator at the time of the conversion of the 4th bit is 1/2 ⁵ of the potential difference between the positive and negative analog voltage sources. The signals f and j in the figure are generated so as to select the path of the connecting means that only shifts the voltage of the ladder tap upward. In the conversion of the 6th bit, if the analog input voltage is lower than the analog output as a result of the comparison in the 5th bit, the analog output voltage used in the conversion of the 5th bit is 1 / N of the potential difference between the positive and negative analog voltage sources. In order to select the path of the connecting means that shifts the voltage of the ladder tap by 2 ⁶ downwards, g, k in the figure
Generate the signal. If the analog input voltage is higher than the analog output as a result of the comparison at the 5th bit, the ladder tap voltage is 1/2 ⁶ of the potential difference between the positive and negative analog voltage sources than the analog output voltage used for the 5th bit conversion. Can be easily configured by a logic circuit as long as it generates the signals e and i in the figure so as to select the path of the connecting means for shifting up.

In the resistance ladder, the DA converter, and the AD converter of the present invention, for example, in the case of the AD converter having 6-bit resolution by the conventional resistance ladder, at least 64 resistances are included in the resistance ladder. , 126 switches were needed for the switching tree to get analog output,
In the case of the AD converter of 6-bit resolution using the resistance ladder of the present invention, since the ladder tap is 16 corresponding to 4-bit resolution, it suffices if there are 30 switches for the switching tree for obtaining the analog output. A maximum of eight switches connect the ladder to the analog power supply, and an A / D converter with 2-bit expansion and 6-bit resolution can be realized. Therefore, the 6-bit resolution can be realized only by increasing the area of the resistor, which occupies most of the area of the AD converter, by about 30% as compared with that of the conventional 4-bit AD converter.

[Embodiment 10] When testing the AD converters of Embodiments 7 and 8, assuming that n = 6 and m = 4, the number of ladder taps is 16, and the route from the ladder taps to the analog output. There are also 16 routes. Since each ladder tap can generate four types of voltage, a total of 64 types of voltage can be output, but 48 types of voltages out of 64 points are connected to the positive and negative analog power supplies 1 and 2. Means 21-
Since four, 24, 31 to 34 combinations are generated, if one of the 64 analog voltages is tested at four consecutive points from one ladder tap voltage, the rest of the tests will be the remaining one.
You can test the output of 15 points of 5 ladder taps,
Since a test equivalent to a test of 64 points can be performed by a test of 19 points in total, the test time can be shortened. At this time, considering that the second and third resistance groups 18 and 19 have an error,
It is preferable to test four consecutive points for each of the top and bottom ladder taps. Even in this case, a 21-point test is sufficient.

[0094]

As described above, the resistance ladder of the present invention, D
-A and A-D converters have much fewer resistors,
Since the resolution equivalent to the conventional one can be obtained with elements such as switches, a high-precision AD converter can be configured in a small area, and the test time of the AD converter can be significantly shortened.
This has the excellent effect of reducing the manufacturing cost of the LSI chip on which these are mounted and obtaining a high-performance and inexpensive AD converter.

[Brief description of drawings]

FIG. 1D of the seventh invention using the resistance ladder of the first invention
It is a circuit block diagram which shows the structure of a -A converter.

FIG. 2D of the seventh invention using the resistance ladder of the second invention
It is a circuit block diagram which shows the structure of a -A converter.

FIG. 3D of the seventh invention using the resistance ladder of the third invention
It is a circuit block diagram which shows the structure of a -A converter.

FIG. 4 is a circuit block diagram showing a configuration of a DA converter using the resistance ladder of the present invention.

FIG. 5: D of the seventh invention using the resistance ladder of the fifth invention
It is a circuit block diagram which shows the structure of a -A converter.

FIG. 6 is a circuit block diagram showing a configuration of a DA converter using the resistance ladder of the present invention.

FIG. 7 is a circuit block diagram showing a configuration of an AD converter of an eighth invention using the DA converter of the seventh invention.

FIG. 8 is a connection state transition diagram of a resistance ladder for explaining a digital conversion operation of the AD converter of the eighth invention.

9 is a timing chart of a control signal that causes the state transition shown in FIG.

FIG. 10 is a connection state transition diagram of a resistance ladder for explaining the operation of digital conversion of the AD converter of the eighth invention.

11 is a timing chart of a control signal that causes the state transition shown in FIG.

FIG. 12 A-D without the conventional 1/2 LSB correction
It is a figure which shows the conversion characteristic (a) of a converter and the conversion characteristic (b) of the AD converter of this invention which does not perform 1/2 * LSB correction.

FIG. 13 is a circuit block diagram showing a configuration of an AD converter of a ninth invention using the DA converter of the seventh invention.

FIG. 14 is a circuit block diagram showing a configuration of an AD converter of a tenth invention using the resistance ladder of the first or second or third or fourth invention.

15 is a circuit diagram showing a partially detailed configuration of the AD converter shown in FIG.

FIG. 16 is a circuit diagram showing a configuration of a conventional 4-bit resolution resistance ladder.

FIG. 17 is a circuit block diagram showing a configuration of a conventional AD converter.

FIG. 18 is a circuit diagram showing a main part configuration of another conventional AD converter.

[Explanation of symbols]

1 Positive analog voltage source, 2 Negative analog voltage source, 4,
5,6,51-57,59-61 resistance, 8,81,8
2,83 analog output, 11-14 ladder taps,
16 comparators, 17 first resistance group, 18, 28, 3
8, 48, 58 2nd resistance group, 19, 29, 39, 4
9 3rd resistance group, 20 Comparison result signal, 21-24
Connecting means to positive analog voltage source 1, 25 Analog inputs, 31 to 34 Connecting means to negative analog voltage source 2, 70
~ 77 switch, 78 switching tree, 79
Selection switch group, 80 n-bit control circuit, 86 switch group control circuit, 90, 91 D-A converter, 100
n-bit control circuit, 101 m-bit control circuit, 102
nm bit control circuit, 110 6-bit control circuit,
300 multiplexer, 301-303 comparison result signal, 304 lower bit conversion result output, 305 encoder, 7000 + p bit selection switch, 701-7
15 switches.

Claims (11)

[Claims] 1. A resistance ladder in which a voltage division value of the potential difference between the first and second reference voltage sources is obtained in 2 ⁿ steps, a plurality of resistances are connected in series, and the total resistance value is (2 ^m −
1) · R [where n> m], and first and second resistor lines generated at a connection point between the resistors and one end of the resistor line
Resistance of the first resistor group having a partial pressure value 2 ^m pieces of the ladder taps taken out of the potential difference between the reference voltage source, 2 ^nm pieces of resistance respectively a resistance value R / 2 ^nm are connected in series And a connecting means for selectively connecting one end of the resistor string and a connection point between the resistors to the first reference voltage source, and the other end of the resistor string is connected to the first resistor group. A second resistor group, a resistor string in which (2 ^nm −1) resistors each having a resistance value R / 2 ^nm are connected in series, and a connection point between both ends of the resistor string and each resistor. A resistance ladder comprising: a connection means for selectively connecting to a second reference voltage source; and a third resistance group in which one end of the resistance series is connected to the first resistance group. 2. In a resistance ladder capable of obtaining a voltage division value of the potential difference between the first and second reference voltage sources in 2 ⁿ steps, a plurality of resistances are connected in series, and the total resistance value is (2 ^m −
1) · R [where n> m], and first and second resistor lines generated at a connection point between the resistors and one end of the resistor line
Resistance of the first resistor group having a partial pressure value 2 ^m pieces of the ladder taps taken out of the potential difference between the reference voltage source, 2 ^nm pieces of resistance respectively a resistance value R / 2 ^nm are connected in series A connecting means for selectively connecting a column and a connection point between the resistors to a first reference voltage source is provided, one end of the resistor column being a first resistor group, and the other end being a first reference voltage. A second resistor group connected to the source, a resistor string in which (2 ^nm −1) resistors each having a resistance value R / 2 ^nm are connected in series, and both ends of the resistor string and between the resistors. Connecting means for selectively connecting the connection point of the second reference voltage source to the second reference voltage source, and one end of the resistor string is connected to the first resistor group,
A resistor ladder having a third resistor group having the other end connected to a second reference voltage source. 3. A resistance ladder in which a voltage division value of the potential difference between the first and second reference voltage sources is obtained in 2 ⁿ steps, a plurality of resistances are connected in series, and the total resistance value is (2 ^m −
1) · R [where n> m], and first and second resistor lines generated at a connection point between the resistors and one end of the resistor line
The first resistor group with 2 ^m ladder taps for extracting the voltage division value of the potential difference between the reference voltage sources of (2 ^nm −1) to 2 resistors with the resistance value R / 2 ^nm The resistance series of (2 ^nm -1) series consisting of a series of resistances and one resistance each connected in series, and each end of the series of resistances individually And a connecting means for selectively connecting the other end to the first reference voltage source in common, the other end of the resistor string being common to the first resistor group via a resistor having a resistance value of R / 2 ^nm. And a second resistance group connected to each of the resistors, each of which has a resistance value of R / 2 ^nm starting from (2 ^nm -1) and decreasing to one by one, respectively, in series connection have been (2 ^nm -1) columns in the resistor string selection, and each of them individually one end of the resistor string, or to a second reference voltage source and the other end to a common Comprising a connection means for connecting to,
A resistance ladder, comprising: a third resistance group, the other end of which is connected in common to the first resistance group. 4. A resistance ladder in which a potential division value of the potential difference between the first and second reference voltage sources is obtained in 2 ⁿ steps, a plurality of resistances are connected in series, and the total resistance value is (2 ^nm
-1). R [where n> m], and a partial pressure value of the potential difference between the first and second reference voltage sources generated at the connection point between the resistors and one end of the resistor series. The first resistor group with 2 ^m ladder taps for taking out the resistor and the number of resistors with the resistance value R / 2 ^nm, which is reduced from 2 ^nm to 1, are sequentially connected in series. It was 2 ^nm column resistor string, and includes a connection means for selectively connecting the first reference voltage source each one end of the resistor string individually,
A second resistor group in which the other end of the resistor string is commonly connected to the first resistor group, and a resistor having a resistance value of R / 2 ^nm starts from (2 ^nm −1) and is one. The second reference voltage source in which each number is sequentially reduced by one, the (2 ^nm −1) series resistor series connected in series, and one end of the resistance series individually or the other end in common A connecting means for selectively connecting to,
A resistance ladder, comprising: a third resistance group, the other end of which is connected in common to the first resistance group. 5. Each of the resistors of the first resistor group is formed by connecting a plurality of unit resistors, each of which has substantially the same resistance value, in series, and the second and third resistor groups are connected to each other. Each of the constituent resistors has a plurality of the unit resistances, and the resistance value is R /
^5. The resistance ladder according to claim 1, wherein the resistance ladder is connected in parallel to have a ^thickness of 2 ^nm . 6. In a resistance ladder capable of obtaining a voltage division value of the potential difference between the first and second reference voltage sources in 2 ⁿ steps, a plurality of resistances are connected in series and a total resistance value is (2 ^m −
1) · R [where n> m], and first and second resistor lines generated at a connection point between the resistors and one end of the resistor line
A first resistor group having 2 ^m ladder taps for extracting the divided voltage value of the potential difference between the reference voltage sources of, and at least a substantial resistance value of (2 ^m −1) · 3R /
Less than (2 ^{m + 1} −3) and (2 ^m −1) · R / (2 ^{m + 1}
−1), a connection means for generating the resistance between the first resistance group and the first reference voltage source, a resistance whose substantial resistance value is less than the resistance value and is not 0, and A connecting means for generating a resistance between the first resistance group and the first reference voltage source, and a resistance value generated between the first resistance group and the first reference voltage source in 2 ^nm steps A second resistance group that can be selected with, at least a connecting means that connects the first resistance group and the second reference voltage source, a resistance whose substantial resistance value is less than R and is not 0, and the resistance. A connection means is provided between the first resistance group and the second reference voltage source, and the resistance value generated between the first resistance group and the second reference voltage source is selected in 2 ^nm steps. A resistance ladder including a third resistance group that can be formed. 7. An n-bit resolution D / A converter using the resistance ladder according to claim 1, 2 or 3 or 4 or 5 or 6, wherein the first resistance group of the resistance ladder has 2 among the ^m ladder taps, means for selecting one of the ladder tap to take out the analog voltage corresponding to the digital value of the upper m bits of the n bits, or if converts the upper m bits, or lower The connection means of the second and third resistance groups is selectively combined depending on whether the (n−m) bit is converted, and 2 ^{m is provided} between the first and second reference voltage sources.
The ladder tap which forms a connection path to the first and second reference voltage sources where the resistance value of R is generated, and further extracts an m-bit analog voltage when converting the lower (n−m) bits And a first control means for forming the connection path while selecting the D-A converter. 8. An n-bit resolution D-A according to claim 7.
A temporary value was set in order to obtain a converter, a comparator for comparing the analog output from the DA converter with the analog input to be converted, and a reference analog voltage for comparison for digitally converting the analog input. A temporary digital value is given to the D / A converter, and a connection path through which a divided voltage value of 2 ^m steps of the potential difference between the first and second reference voltage sources is obtained at the time of converting the upper m bits is the D / A conversion. And the lower (n
In the case of (m) bit conversion, the connection path is changed based on the comparison result of the comparator while the ladder tap selected in the m-bit conversion is selected, and the ladder tap from the ladder tap selected in the m-bit conversion is changed. An AD converter, comprising: a second control unit that changes an analog output at least (nm) times. 9. The resistor ladder according to claim 1, 2 or 3 or 4 or 5 or 6, and among the 2 ^m ladder taps included in the first resistor group of the resistor ladder, the higher order of n bits. Means for selecting one ladder tap from which an analog voltage corresponding to an m-bit digital value should be taken out, and 2 ^m steps taken out from the ladder tap by selectively combining the connecting means of the second and third resistance groups Is added with an offset in units of 1/2 ⁿ of the potential difference between the first and second reference voltage sources, and a resistance of 2 ^m · R between the first and second reference voltage sources. A D-A converter comprising third control means forming a connection path to the first and second reference voltage sources at which a value is generated, and m from the D-A converter
A comparator for comparing an analog output for bits with an analog input to be converted, and a tentative digital value set with a tentative value to obtain a reference analog voltage for comparison for digitally converting the analog input. A to D converter having a fourth control means provided to the converter. 10. The resistance ladder according to claim 1 or 2 or 3 or 4 or 5 or 6, wherein the voltage division value of the potential difference between the first and second reference voltage sources is obtained in 2 ⁿ steps. Two
^{Of m} ladder taps (where n> m), p bits (however, m ≧
p] a means for selecting (2 ^p -1) ladder taps from which an analog voltage corresponding to the digital value of p] should be taken out, and when converting the upper m bits or converting the lower (n−m) bits First and second reference voltages at which a resistance value of 2 ^m · R is generated between the first and second reference voltage sources by selectively combining the connection means of the second and third resistance groups according to D with fifth control means forming a connection path to the source
-A converter, (2 ^p -1) comparators for comparing the analog output from the DA converter with the analog input to be converted, and the ladder tap selected in the final stage of the upper m-bit conversion Of the ladder taps from which a voltage lower than that of the analog input is extracted, a ladder tap selection means for selecting a ladder tap from which the highest voltage is extracted as a ladder tap used for lower (nm) bit conversion, and an upper m-bit digital At the time of conversion, the DA converter is formed with a connection path through which a divided voltage value of the potential difference between the first and second reference voltage sources in 2 ^m steps is obtained. Until the number of bits is reached, provisional digital values in which provisional values are set in order to obtain a reference analog voltage for comparison for digitally converting the analog input are sequentially applied to the DA converter, and p Was repeated analog conversion bit basis, each of the analog conversion, the at the comparator D
The analog output from the -A converter is compared with the analog input and digitally converted in p-bit units, and when the lower (n-m) bits are digitally converted, the lower (n-
m) A temporary digital value in which a temporary value is set to obtain a reference analog voltage for comparison for digital conversion of bits is given to the DA converter, while the ladder tap selected at the time of converting m bits is selected. Sixth control means for changing the connection path based on the comparison result of the comparator to change the analog output from the ladder tap selected at the time of m-bit conversion at least (nm) times in the state. A means for selecting a ladder tap to be used for lower (n−m) bit conversion when the ladder tap selection means does not select any of the (2 ^p −1) ladder taps. -D converter. 11. A 2 ^m point test for testing each of the ladder taps for extracting analog outputs of 2 ^m different levels and a 2 ^nm step in an analog voltage unit corresponding to a 1/2 ⁿ bit unit by changing the connection path. Change the voltage of the ladder tap to each ladder tap that takes out the analog output corresponding to the m-bit minimum digital value and the maximum digital value or to the ladder tap near the ladder tap 2 (2 ^nm -1) The method for testing an AD converter according to claim 8, 9 or 10, wherein a test corresponding to 2 ⁿ points is performed by performing a precision test of points.