JPS61144127A - Analog digital converter - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of the input stage by discriminating a high-order bit through the generation of a reference potential and a low-order bit through a voltage subject to level shift for an input analog signal. CONSTITUTION:The analog signal inputted to a terminal 1 is subject to level shift by the 1st series resistor group 3. Each terminal voltage subject to level shift is inputted to emitter followers 4, 5, 6, 7. On the other hand, a high-order 2-bit reference voltage is generated by the 2nd series resistor group and outputted via emitter followers 10, 11, 12, 13. The high-order 2-bit is obtained by comparing voltages of each emitter follower output of the high-order bits and the low-order bits obtained in this way, that is, outputs of comparators 18d, 18h, 18. Further, an output obtained as the result of discrimination of the further 1/4 division of the lowest level of the input dynamic range subject to 1/4 division is obtained from comparators 18a-18c.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog-to-digital converter that has a small number of elements, is simple, and is easy to mount.

[Technical background of the invention and its problems]

When digitally encoding a video signal or the like, high-speed and highly accurate analog-to-digital (A/D) conversion is required. And when incorporating this into the system, 1
It is required to simplify the peripheral circuits and make them easy to use. For this reason, conventionally, generally, as shown in FIG. The A/D converter having this configuration is called a parallel type and is capable of high-speed operation. However, when trying to encode n bits.

This method requires (2n-x) voltage comparison margins, and as the number of bits increases, the number of comparators increases exponentially. Moreover, since the input terminals of a large number of comparators are connected to the analog signal input terminal, the input capacitance is large. Therefore, in order to operate at high speed, a buffer that can flow a large current for inputting signals is required, which places restrictions on peripheral circuits. Moreover, the above comparator is 5
Usually, it is configured as shown in Fig. 4, and the emitter follower circuit (
35-40. After softening the level ratio through the circuit 5), the comparison result is amplified to a high gain by receiving a clock φ2 to exhibit a positive feedback effect, and is latched and output. The problem here is the input current of the comparator. That is, the differential amplifier (41
, 42, 49, and 50, in order to improve the frequency characteristics of 5), a certain amount of current must flow, so the input current of the differential amplifier becomes large, and it is necessary to directly connect it in series. When connected to the resistor group 31,
This input current causes an error in the reference voltage and degrades accuracy. For this reason, an emitter follower circuit is inserted to function as a buffer, but since the input current is still large, generally a negligible large current is passed through the series resistor group 31 to maintain full accuracy. ing. This = i
In order to realize this in an IC, it is necessary to reduce the resistance value, so aluminum or silicide alloy used for wiring is used as a resistor, but this leaves problems with reliability against corrosion and heat generation, and The disadvantage is that power consumption increases.

[Purpose of the invention]

The present invention was made in consideration of such circumstances, and
The goal is to perform high-speed, high-precision digital conversion processing, reduce the number of components, facilitate monolithic ICs, and reduce restrictions on peripheral circuits, thereby making analog/digital converters highly practical. The purpose is to provide a converter.

[Summary of the invention]

According to the present invention, a reference voltage for upper m bits is generated,
An emitter follower circuit is connected as a buffer from each potential, while lower t bits, which are further subdivided from the minimum voltage range of the upper bits, are generated by an input analog signal and its level shift.

Emitter follower circuits are connected in the same way as the upper bits of each potential. By comparing the outputs of these upper bit and lower bit emitter follower circuits for each combination using a group of voltage comparators, it is possible to determine which minimum voltage range of the A/D conversion resolution the input analog signal voltage falls within. .

〔Effect of the invention〕

As described above, according to the present invention, the number of resistors for generating the reference voltage is small, and since the emitter follower circuit is inserted as a buffer, the deterioration of accuracy due to input current as described in the conventional example can be suppressed. Since the input capacitance is small, there is no need to run a large current through the reference voltage generating resistor, and since the input capacitance is small, there is no need for a special drive circuit. Can be provided.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows a 4-pin A/D converter as an embodiment of the present invention. An analog signal is input to terminal 1, and is sent to the first terminal with the same resistance value R via emitter follower 2 for buffering.
The level is shifted by the series resistor group 3. Here, the voltage level-shifted by each resistor corresponds to the minimum quantization bit (L, S, B) of the A/D converter, and the total amount of level shift corresponds to the minimum resolution of the upper bits, which will be described later.

Next, the level-shifted voltage of each terminal is applied to the emitter follower.
Enter 4, 5, 6.7. On the other hand, a reference voltage for the upper two bits is generated by the second series resistor group 9 via a transistor for compensating for a level shift error corresponding to the voltage between the base and emitter of the emitter follower transistor 20. Here, 4 bits are divided into upper 2 bits and lower 2 bits.

Each resistance value of the second series resistance group 9 may be approximately four times the resistance value of the first series resistance group 3.The reference voltage for the upper two bits generated thereby is connected to each terminal. output through the emitter followers 10, 11, 12, and 13. Here, the currents of the current source 14 of the first-stage emitter follower of the input signal and the current source 15 for generating the reference voltage of the upper bit must be matched with accuracy according to the desired bit, but it is necessary to select one of them. May be adjusted. In addition, the current value generator 1 of the current source group 16 of the emitter follower of the lower bit
The current values of the current source group 17 of the emitter follower of the upper bit and the current values 2 of the current source group 17 of the emitter follower of the upper bit should be the same. Since the pace emitter voltages are the same, the error is reduced. Quantization can be performed using the voltage comparators 188 to 180 that compare the voltages between the emitter follower outputs of the upper bits and lower bits configured in this way. More specifically, by comparing the output of the emitter follower 4 and the output of the emitter follower 10°11.12.13, that is, the comparators 18d, 18h,
181 output, the upper two bits are obtained. In addition, the input dynamic range is divided into four parts, and the part with the lowest level is further divided into four parts, and the output is determined by the comparator 18.
A, 18b, 18C are obtained, and the 2nd, 3rd, and 4th from the bottom are 18e and 18f, respectively.
, 18g, and xsi, 18j.

18, 18m, 18n, and 18o generate data for the lower two bits, and together with the upper two bits, a total of 4-bit A/D converter is formed. Furthermore, according to this configuration, the emitter follower section of the conventional comparator shown in FIG. There is no need to include an emitter follower at the input, and a comparator like the one shown in Figure 2 without this can be used, so the number of elements constituting the comparator can be reduced, and the A/
Another advantage is that the number of elements in the D converter may be small.

As described above, according to the present invention, the upper bit generates a reference potential as in the conventional case, and the lower bit is determined by the level-shifted voltage of the input analog signal, thereby simplifying the circuit configuration of the input stage. Furthermore, errors due to the input current of the comparator can be suppressed, and since the input capacitance is small, it is easy to drive the input signal, which is a great practical effect.

Note that the present invention is not limited to the above embodiments. For example, the number of upper bits and the number of lower bits may be determined according to the specifications.In this embodiment, the current value was made equal to generate the reference voltage, and the resistance was weighted for the upper and lower parts. It is possible to make appropriate modifications such as keeping the resistance values the same and weighting the current values, or a combination of both. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the A/D converter according to the present invention, FIG. 2 is a diagram showing an example of the voltage comparator shown in FIG. 1, and FIG. 3 is a diagram showing an example of the voltage comparator shown in FIG. FIG. 4 is a diagram showing a converter, and FIG. 4 is a diagram showing an example of the voltage comparator shown in FIG. 3. 1...Analog signal hexagonal terminal, 2, 4-8, 10-1
3.21-27, 35-38.41-47...np
n bipolar transistor 3.9.31... Series resistance group, 14, 15, 16.17... Current source, 18a-1
8o, 32- @pressure comparator (group), 19, 20.33
...encoding circuit, 28-30, 39, 40, 4
8~50~Resistance, 34°°° encoded digital signal output terminal, 51.52... Voltage comparator output terminal, 5
3.54...Clock input terminal. Agent: Patent attorney Kensuke Norichika (and 1 other person) Figure 1

Claims (2)

[Claims] (1) An input signal level shift circuit that level-shifts the input analog signal so that the amount of level shift differs by the minimum resolution of the lower bits, and generates the same number of signals as the resolution of the lower bits, and the minimum resolution of the upper bits. A circuit that generates reference voltages that differ by the number of resolutions of the upper bits, and a voltage generated on the upper bit side and a voltage generated on the lower bit side for all combinations of the upper bit side and the lower bit side. An analog-to-digital converter comprising a voltage comparator for comparison. (2) The analog-to-digital converter according to claim 1, wherein the level-shifted one of the input signal is used as the upper bit, and the other side is used as the lower bit.