JPH06112824A - Interpolation type a/d converter - Google Patents

Abstract

PURPOSE:To obtain an interpolation type A/D converter able to implement sufficient correction even when an error of 1LSB or more takes place in the result of high-order conversion. CONSTITUTION:Correction use interpolation resistor arrays 25-28 are provided to terminal points of interpolation resistor arrays 22, 23, a voltage equivalent to 3LSB is applied to both terminals by operational amplifiers 10-13 to activate correction comparator arrays 29-34 in response to an interpolation voltage and the high-order conversion result is corrected according to the result. Through the constitution above, even when the result of conversion has an error of 1LSB or more, accurate high-order data are obtained and A/D conversion with high accuracy is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation type A / D converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art In recent years, with the progress of digitization of electronic equipment, there has been a demand for lower power consumption, higher speed, and higher accuracy of an A / D converter which is a key device thereof.
In order to reduce the power consumption of the A / D converter, it is effective to use a serial / parallel conversion method such as an interpolation type.

A conventional interpolation type A / D converter will be described below with reference to FIG. FIG. 2 shows the conventional interpolation type A.
An example of a structure of a / D converter is shown. In FIG. 2, 1 is a reference resistor train, 2 is a differential amplifier train, 3 is a switch train, 4 is a high order comparator line, 5 and 6 are differential amplifiers, 7 and 8 are reference voltage input terminals, and 9 is a high order encoder. , 22 and 23 are interpolation resistance trains, 24 is a low order comparator, 31 and 32 are correction comparators, 3
Reference numeral 5 is a lower encoder, 36 is a logic circuit, and 37 is an analog signal input terminal.

In this interpolation type A / D converter, first,
The difference voltage between each reference voltage generated in the reference resistor string 1 and the signal at the analog signal input terminal 37 is amplified in the differential amplifier string 2, and compared in the comparator string 4 to compare the voltage level of the analog signal input voltage. Is each tap voltage V _{0 to} V _{8 of the} reference resistor string 1.
To detect which tap voltage is present. And the result is converted into a binary digital signal by the upper encoder 9,
Obtain the high-order bit digital signal.

Next, the specific four switches of the switch row 3 are closed according to the level of the analog input signal detected by the upper comparator row 4. For example, when the analog input signal is at a level between the reference voltages V ₄ and V ₅ , two switches connected to V _{4 of the} reference resistance string via the differential amplifier and the reference resistance via the differential amplifier. Close the two switches connected to V ₅ in the row. As a result, the output voltages of the differential amplifiers 5 and 6 connected to the switch train 3 become equal when the analog input voltages are V ₄ and V ₅ , respectively. Next, the output voltages of the differential amplifier are interpolated by the interpolation resistance trains 22 and 23, and the interpolation voltages V ₁₄ , V ₁₅ , V ₁₆ and the interpolation resistance train 23 of the interpolation resistance train 22 are interpolated.
The interpolated voltages V ₂₄ , V ₂₅ , and V ₂₆ are compared by the lower comparator array 24 to detect the level of the analog input signal between V ₄ and V ₅ in more detail.

Then, the result detected by the lower comparator array 24 is converted into a binary digital signal by the lower encoder 35 to obtain a lower digital signal.

However, when the result of the lower comparator array 24 is not between V _{14 to} V ₁₆ and V _{24 to} V ₂₆ due to the upper conversion error, one of the correction comparators 31 and 32 is output. If so, the upper result is shifted by 1 LSB.

The obtained results of the upper encoder 9 and the lower encoder 35 are combined by the logic circuit 36. At the same time, when the upper results are different, the signals of the correction comparators 31 and 32 are used to output the upper digital signal within 1 LSB. Make a correction.

With the above operation, the signal at the analog signal input terminal 37 is converted into a digital signal with high accuracy.

[0010]

However, in the above-mentioned conventional configuration, since there is only one correction comparator at each end of the interpolation resistor string, the result of the upper encoder 9 is 1 LSB.
When the above conversion error is included, it cannot be corrected. Therefore, the signal at the analog signal input terminal 37 cannot be converted with high precision.

The present invention solves the above-mentioned conventional problems, and provides an interpolation type A / D converter capable of performing sufficient correction even when an error of 1 LSB or more occurs in the result of upper conversion. The purpose is to do.

[0012]

In order to achieve the above object, the interpolation type A / D converter of the present invention is provided with a correction interpolation resistance series at each end point of the interpolation resistance series, and performs calculation at both ends thereof. The amplifier has a configuration in which a voltage corresponding to 3LSB is applied, the correction comparator array is operated according to the interpolation voltage, and the higher conversion result is corrected according to the result.

[0013]

With this configuration, even if the higher-order conversion result has an error of 1 LSB or more, the addition of the operational amplifier for generating the correction voltage, the correction voltage setting resistor, the correction interpolating resistor string, and the correction comparator ensures accurate correction. Higher-order data can be obtained and highly accurate A / D conversion becomes possible.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows an interpolation type A / in the embodiment of the present invention.
2 shows the configuration of the D converter, and in FIG.
The same reference numerals denote the same parts, and a description thereof will be omitted.

In FIG. 1, 10 to 13 are operational amplifiers for generating a correction interpolation voltage, and 25 to 28 are correction interpolation resistor strings. The resistors 14 to 21 connected to the input and output of the operational amplifiers 10 to 13 respectively generate a voltage twice as large as the potential difference of one resistor formed in the interpolation resistor train 22 and the interpolation resistor train 23. Is set.

The operation of the interpolation type A / D converter configured as described above will be described below.

Similar to the operation of the conventional interpolation type A / D converter, first, the difference voltage between each reference voltage generated in the reference resistor train 1 and the signal of the analog signal input terminal 37 is amplified in the differential amplifier train 2. , And compares them in the upper comparator row 4 to detect which tap voltage among the tap voltages V _{0 to} V _{8 of the} reference resistance row 1 the voltage level of the analog signal input voltage falls between. Then, the result is converted into a binary digital signal by the upper encoder 9 to obtain a digital signal of upper bits.

Next, the specific four switches of the switch row 3 are closed according to the level of the analog input signal detected by the comparator row 4. For example, if the analog input signal is the reference voltage V
_For levels between ₄ and V ₅ , two switches connected to V ₄ of the reference resistor string via a differential amplifier and two switches connected to V _{5 of the} reference resistor string via a differential amplifier. Close the pieces. As a result, the output voltages of the differential amplifiers 5 and 6 connected to the switch train 3 are analog input voltages V ₄ and V ₄ , respectively.
It becomes equal at V ₅ . Next, each output voltage of the differential amplifier is interpolated by interpolation resistance trains 22 and 23, and the interpolation resistance train 22
Of the interpolating voltages V ₁₄ , V ₁₅ and V ₁₆ and the interpolating voltages V ₂₄ , V ₂₅ and V ₂₆ of the interpolating resistor row 23 are compared in the lower comparator row 24, and V ₄
More closely detect the level of the analog input signal between V and V ₅ .

Then, the result detected by the lower comparator array 24 is converted into a binary digital signal by the lower encoder 35 to obtain a lower digital signal.

However, it is determined that the result of the lower comparator array 24 is not between V _{14 to} V ₁₆ and V _{24 to} V ₂₆ due to the upper conversion error, and one of the correction comparators 29 to 34 is selected. If it is output, the upper result is shifted by that result. For example, if the voltage from the host is sent to the lower, when the signal lower comparator switches was in between _{V 14 ~V 16, V 24 ~V} 26, the output of the digital data only the result of high and low results Is determined. However, the signal from the host is V ₁₄ ~
Not between V ₁₆ and V _{24 to} V ₂₆ , but V _{17 to} V ₁₈ , V _{27 to} V ₂₈
If it is between the two, only the correction comparator 30 is output. Here, by setting the potential difference between the taps of the correction resistor rows 25 to 28 to be the same as the potential difference between the taps of the interpolation resistor rows 22 and 23, the logic circuit 36 is based on this result.
And outputs digital data obtained by combining the results of the upper encoder 9 and the lower encoder 35,
When an error occurs, the data of the upper encoder 9 is changed to 2LSB.
Minutes can be corrected.

As described above, according to the present embodiment, it is possible to completely correct the error of the upper encoder, so that the high precision A
/ D conversion is possible.

[0023]

The present invention has a built-in operational amplifier for generating a voltage on both sides of a signal from the upper side at any time when obtaining lower-order digital data, and requires the upper digital data based on the voltage. It is possible to realize an extremely excellent interpolation type A / D converter with high conversion accuracy that can be interpolated according to the above.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an interpolation type A / D converter according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional interpolation type A / D converter.

[Explanation of symbols]

 1 reference resistance row 2 differential amplifier row 3 switch row 4 upper comparator row 5, 6 differential amplifier 7, 8 reference voltage input terminal 9 upper encoder 10-13 operational amplifier 14-21 correction voltage setting resistance 22, 23 interpolation resistance Row 24 Lower comparator row 25-28 Correction interpolation resistance row 29-34 Correction comparator 35 Lower encoder 36 Logic circuit 37 Analog input terminal

Claims (1)

[Claims] 1. A first differential amplifier having two differential input terminals coupled to an analog output of an upper conversion circuit, and a second differential amplifier having two differential input terminals coupled to an analog output of the upper conversion circuit. Differential amplifier, and a first interpolation resistor string having one end coupled to the first output terminal of the first differential amplifier and the other end coupled to the first output terminal of the first differential amplifier. A second interpolation resistor string having one end coupled to a second output terminal of the first differential amplifier and the other end coupled to a second output terminal of the second differential amplifier; Has an input terminal connected to a first output terminal of the first differential amplifier, a second input terminal connected to a first output terminal of the second differential amplifier via a first resistor, A first operational amplifier having the second input terminal connected to the output terminal via a second resistor;
Input terminal is connected to the second output terminal of the first differential amplifier, and the second input terminal is connected to the second output terminal of the second differential amplifier via a third resistor. , The second
A second operational amplifier whose input terminal is connected to an output terminal via a fourth resistor, and a first input terminal which is connected to a first output terminal of the second differential amplifier, An input terminal is connected to a first output terminal of the first differential amplifier via a fifth resistor, and the second input terminal is a sixth output terminal.
A third operational amplifier connected via a resistance of the second differential amplifier, a first input terminal connected to a second output terminal of the second differential amplifier, and a second input terminal connected via a seventh resistance. The first
A fourth operational amplifier connected to the second output terminal of the differential amplifier, and the second input terminal connected to the output terminal through an eighth resistor; and an output of the first operational amplifier. The first correction interpolating resistor string connected to the first output terminal of the first differential amplifier, the output of the second operational amplifier, and the second output terminal of the first differential amplifier. Second connected
Correction interpolating resistor string, a third correcting interpolating resistor string connected to the output of the third operational amplifier and the first output terminal of the second differential amplifier, and the fourth operational amplifier. Output of the second differential amplifier and a fourth correction interpolating resistor string connected to the second output terminal of the second differential amplifier, and a comparator string coupled to each tap of the first and second interpolating resistor strings. And the first, second,
An interpolation type A / D converter having a comparator row coupled to each tap of the third and fourth correction interpolation resistance rows.