JPS5810922A - Direct flash type analog-to-digital converter - Google Patents

Abstract

PURPOSE:To perform high speed A/D conversion with less number of comparator, by providing a level detector in cross coupling connected to a single comparator, so that the output of the comparator is a simple binary output directly coded for each differential amplifying cell. CONSTITUTION:Differential amplifying cells 10, 20-130 are coupled to receive an input analog signal VIN and a specified converting reference voltage and a differential output signal is generated in response to the voltages. A differential amplifier in the cell has a converted reference voltage to the reference level and the amplifiers are cross-coupled to comparators 140, 150..., respectively. Each comparator has a high gain so that the output is a digital signal substantially, transmitted to corresponding data latching circuits 180, 190..., from which A/D-converted digital signals are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct flash type A/D converter having a C independent parallel type A/D encoder for each pin.

In the simultaneous conversion method of converting an analog voltage to a digital representation, all C bits of the digital representation are determined simultaneously. This method is known as the parallel method because it has a parallel bank of voltage comparators, and each comparator responds to an analog voltage reaching a predetermined voltage level.

In an N-bit encoder (where N is a predetermined integer), there are 2M digital output states. The maximum analog voltage is divided into 2" voltage levels. Each level represents a voltage quantity, and each quantity level is represented by one K of digital output states. A conventional N-bit encoder has 2" voltage levels. requires comparators, and each comparator determines the conversion to a particular quantity level.Thus, the traditional parallel form of the simultaneous conversion method, if N is large,
It requires a very large number of comparators. In fact, when N is 6 or more, there is a drawback that the number of comparators becomes extremely large. However, the ultra-high speed conversion achieved by this method offsets the aforementioned drawbacks.

The simultaneous conversion method also has the disadvantage that the output from the parallel bank of voltage comparators is not in a concise format, but is in the form of a 211-12 decimal data signal. Usually 2”
The -1 output is encoded by the conversion logic into the final bit of the two-way information in a compact binary format. For large values of N, typically 6 or more, the number of elements required in the conversion logic becomes extremely large due to the large number of human and logic combinations.

In this way, high-speed A/D conversion in simultaneous conversion, known in the prior art as "flash encoding," is extremely difficult for encoders with large N; it requires many comparators, and the conversion logic is This was difficult to implement due to its complexity.

The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to provide a direct flash type converter having an independent parallel type A/D encoder for each pin. According to one embodiment of the invention, each independent bit encoder is converted into a single comparator such that the output of the comparator is a compact binary output that is directly encoded into a K, single comparator! It is equipped with a series of cross-coupled level detectors. Thus, a single comparator is required for each bit and no conversion logic is required. As a result, a practical direct multi-bit flash converter can be realized.

The illustrated embodiment of the invention is a simultaneous 8-bit, Gray code, A/D converter. Each bit is encoded by a group of independent parallel Jsag circuits coupled to a comparator that provides a concise directly encoded output. The present invention includes a parallel bit encoder and generates an N-bit binary code, so it will be referred to as a "direct flash converter." In this explanation °C@
The term "transducer" means a general and
C The term "encoder" refers to circuitry within the converter.

The binary code combined in the embodiment of the present invention is also
is a unit distance code known as a ``cyclic code'', a 1-reflection binary code, or a 1-Gray code after its inventor as used herein.

The states of a 4-bit (N=4) Gray code are shown in Table 1 below as a function of quantization input voltage.

Table 1 Gray code analog value (quantization level)oo
oo.

0001 10011
20010
30110 40
111 50101
60100
71100 81
101 91111
101110
111010 121
011 131001
141000
15 Figure 1 shows the function 1 of increasing analog input voltage.
[Shows a digital waveform associated with a Gray code bit value.] In the figure, the inside waveforms relate to overrange bits, and waveforms (B), 0, p), and (g) respectively relate to the Gray code in Table 1. Here, waveform (B) represents the most significant bit, waveform 0 represents the next most significant bit, and waveform (2) represents the least significant bit. In the Gray code, as illustrated, only one bit changes in response to a human input signal that crosses any one predetermined quantization level.

Each bit of the digital representation is C encoded by an independent parallel A/D encoder. In FIG. 1, each digital output bit is characterized by a digital conversion representing analog voltages occurring (FS÷2M-1) apart. where F8 is the value of the full-scale analog signal, M is an integer representing the output digital bits, and CM=1 corresponds to the most significant bit.
The first conversion for each digital bit occurs as FS divided by di.

For example, in a system with a full-scale analog value of 256V, M=4 and the fourth digital bit corresponding to waveform
, performs the first transformation, and its quantization level is 32
V °C away.

One advantage of embodiments of the present invention is that with the resolution of the 8-pit A/D converter, the input slew rate increases as K This means that it decreases bit by bit. This is an advantage over prior art techniques which suffer from errors or glitches when the maximum slew rate is exceeded.

FIG. 2 is a circuit diagram of a flash type A/D converter according to an embodiment of the present invention. In the figure, a plurality of differential amplifier cells 1 (L 20.30.40.so, 60°70,
80.90.100.110.120 is coupled to receive input analog signal vxN. Further, each differential amplifier cell containing an individual differential amplifier is coupled to receive a predetermined set of converted reference voltages. In an embodiment of the invention, °C is 2"l-, which increases monotonically with n.
There is a conversion reference voltage of 1. Therefore, N is an integer larger than zero, and n is an integer indicating one of the conversion reference voltages such that 1<n<2''-1.5K, as will be explained in detail later.
Each differential amplifier cell generates a differential output signal in response to an applied input analog signal and a received converted reference voltage. Essentially, the differential amplifier within the differential amplifier cell functions as a level detector with a translated reference voltage to a reference level. For example, the overrange differential amplifier cell 10 can be used if the human input analog signal VIM is at full scale (256
) If it is below the conversion reference voltage, generate an output signal (IN) of a low voltage level that conforms to the waveform shown in FIG. 1 (5),
Then C input signal v! If the voltage is greater than the full-scale conversion reference voltage, a high voltage level output signal will be generated.

Differential amplifier cell 20 is coupled to a . . . -scale (128) converted reference voltage and produces a differential output signal corresponding to waveform (B) of FIG. Similarly, the differential amplifier cells 30, 40, and 50 have the waveforms (Of,
(Generates a differential output signal corresponding to Di, @.

The differential amplifier cells 20, 30, 40, 50, 60, 70 constitute independent parallel A/D encoders. Each of these differential amplifier cells has an output connected to two sampling comparators. For example, each differential amplifier cell 10 has a sampling comparator 14
0 and 150IICij & connected output lines IN and IN
It has B and 'C. The output of the differential amplifier cell 20 is also connected to sampling comparators 160 and 170. These sampling comparators have high gains such that the output from their comparator gain elements is substantially digital. .

The comparison mode in these comparators operates in response to being strobed by a positive clock pulse;
It then holds those outputs until the next positive clock pulse occurs. The sampling comparators 140 and 1
50 are strobed with opposite edges of the clock signals (OLK and 0LKB). Thus, sampling comparator 140 holds a digital output when sampling comparator 150 compares its inputs, and vice versa. This sampling operation is 20
With a duty cycle of 50% with a period of nag seconds, a
Depending on the output signal, the analog signal VIM is sampled for 10 nanoseconds.

Data latch 180. 190.200.210 are sampling comparators 140.150.160.1 respectively
70. Each data latch is connected to a corresponding sampling comparator Km and is strobed with a clock signal of opposite phase to the sampling comparator coupled to it. Thus, the output of the complementary data latch changes only on alternate clock edges.

Each data latch and comparator circuit for bit 2.3.4.5.6K is identical to the overrange bit and bit 10 circuits described above. The circuits for the 7th and 8th bits are similar to the 6-bit circuits described above, but
In practice, due to the limitations and number of conversions that can be performed within a differential amplifier cell, the two differential amplifier cells 80 and 90 are interconnected to produce a seventh digital bit output. . Similarly, differential amplifier cell 100.
110.120.degree. 130 are interconnected to generate an eighth digital bit output. Note that details of these special differential amplifier cells and the coupling circuit will be described later.

Detailed circuit diagrams of the digital amplifier cells 20, 30, 40 are shown in FIGS. 3.4.5 and likewise in FIG. 7, respectively. Each cell is physically and operationally identical, except for the number of differential amplifiers that act as level detectors within each cell and the reference voltages connected to them. This is also evident from Figures 7A-H. Each cell consists of a number of parallel differential amplifiers, ie, differentially coupled transistor pairs, and has two inputs (ie, an analog voltage input and a reference voltage input).

On the analog voltage input side of the differential amplifier, the base of the transistor in each transistor pair is connected to the input analog voltage v! coupled to receive y. Also, on the reference voltage input side of the differential amplifier, the bases of other transistors in the transistor pair are coupled to receive a converted reference voltage from a multi-voltage reference source. The relative values of these conversion reference voltages are shown in the drawing 'C' relative to 256, which represents the full scale analog voltage. The collectors on each side of the differentially coupled transistor pair are respectively coupled together, alternately coupled, or cross-coupled.

That is, the collectors of each pair of differentially coupled transistors are connected to the collectors of the other pair, alternately directly connected and cross-connected, forming two collector current paths. In other words, if each differentially coupled transistor pair is sequentially numbered 5 to correspond to each monotonically increasing conversion reference voltage it receives, then the collectors of the even numbered transistor pairs on each side of this array are joined together;
The collectors of the odd numbered transistors on each side of the array are then cross-coupled. The collectors on each side of the array are further interconnected to form a collector current path on each side. These two collector current paths are then each connected to one of the emitters in the transistor pair, and their bases are connected to Idori. The only exception is the differential amplifier cells 10 and 20, each of which In FIG. 3, the differentially coupled transistor pairs form fast alternating current paths. These alternating current paths carry currents i! and 12, respectively. The currents i1 and 12 are passed through transistors 322 and 324, respectively [pull-up resistor 32
6 and 328 K currents and the voltages developed across resistors 326 and 328, respectively, are applied to the differential inputs of comparator 140.

In operation, odd currents are summed at the current output node coupled to the input of the comparator. In the circuit of FIG. 3, a current source 300 coupled to a differentially coupled transistor pair consisting of transistors 310 and 320 produces an odd current. Other cells, such as those shown in FIGS. 4 and 5, have an even number of thresholds and differentially coupled transistor pairs.

In these cells, a ground-coupled differential amplifier °dummy”
The differential amplifier is required to meet condition 11 with an odd number of currents. In particular, current sources 330 and 340 in the circuits of FIGS. 4 and 5 are always switched to one side of the arrangement.

The differential voltage between the conversion reference voltages is large enough that each differential amplifier can operate as a 100% switch.

Each differential amplifier cell operates as follows. That is, the input analog signal vts on one side of the parallel differential amplifier
When the amplitude of t is substantially equal to one of the converted reference voltages received by that cell on the other side of the amplifier, a differential amplifier, including a 'dummy' amplifier, will have the same number of currents flowing through each of the differential amplifiers. Fully switchable to pull out on the side.

. These currents on each side are then added to the output differential current. Since there is always an odd number of currents in the differential amplifier cell,
There are remaining odd differential amplifiers that do not switch completely on one side. The remaining differential amplifiers ensure that the currents are equal through each side, eg, transistors 322 and 324. This forms an equilibrium state and the signals applied to the differential inputs of the comparator have equal voltages. However, if the input voltage v, , 6 is slightly less than or greater than the received conversion reference voltage, a differential voltage is applied to the comparator power terminal. Even if each differential amplifier requires K approximately 200mV for complete switching,
The balance can be arbitrarily resolved by the high gain of the sampling comparator. A human analog voltage V! that is slightly smaller or larger than the selected conversion reference voltage!
A polarity difference occurs in the comparator output. This polarity corresponds to an odd or even number of thresholds. As an example, FIG. 6 shows a cell corresponding to the differential amplifier cell 5o (M=4Nc) in FIG.
V cUt ) is shown in ) in FIG. 11c, Vout +t, is responsive to an input analog voltage substantially equal to one of the received conversion reference voltages, as described above.
1 Zero voltage one by one. The digital output produced for this cell is shown in FIG. 60.

When more than 32 differential transistor pairs are used in a differential amplifier according to an embodiment of the present invention, the threshold values of adjacent differential transistor pairs are very close to each other. In other words, the more elements are switched at once, the more I
I order child switching occurs close to each other. During switching, the gain of the device is reduced. This phenomenon reduces the effective gain of the entire differential amplifier cell. Due to the substantially reduced effective gain, K is difficult to distinguish from the received data differential amplifier cell. Therefore, this problem could be solved by limiting the maximum number of differential amplifiers in the cell to 32 °C for 256 full-scale analog voltages, as shown for example in Figures 7G and 7 HvAic. . This gives a minimum threshold interval of 80 mV. K to allocate more than 32 quantization levels per output bit, bits 7 and 8 (M = 7 and 8)
A differential amplifier cell is shown in FIG. In particular, for M=7, monotonically increasing conversion reference voltages are applied alternately to the two differential amplifier cells 80 and 90. The outputs from these cells are then amplified by associated comparators, and the outputs of the comparators are then amplified by e.g.
k and C1 are logically combined. For M=8, the monotonically increasing conversion reference voltage is divided into four differential amplifier cells 10
It is between 0.110.120.130. As in the case of M=7, K, cell 100.110.120°130 KI
l*L fsh*r;tfPtBkakt@purpose1tc@
-'s+b is done. For example, each output from differential amplifier cells 100 and 130 is logically combined through exclusive NOR gates 500 and 550, and each output from cells 110 and 120 is logically combined through exclusive NOR gates 530 and 540. are logically combined, and each output of the exclusive NOR gate is further OR gate 510 and 5
20 to finally produce bit 8.

The conversion reference voltages coupled to the individual differential amplifier cells are shown in Figures 3.4, 5.6, and especially Figures 7A-H. A minimum threshold spacing of 80 mV in a given differential amplifier cell ensures sufficient gain on a bit-by-bit basis. For the two least significant bits, the reference voltage applied to each set of 32 differential amplifier cells is 8
offset to form a minimum spacing of 0 mV. The logical combination of the four sets of conversion reference voltages at the minimum bit γ is 2
A resolution of 128 quantization levels is formed at intervals of 0 mV.

FIG. 8 shows details of the sampling comparators 140 and 150, and data latches 180 and 190.

The differential output from differential amplifier cell 10 in FIG. 2 is applied to inputs IN and INB into temperature sampling comparators 140 and 150. Clock signal OL) is high! I
(tzV)k, warp, -(OLKB is low 11(
3,6V), from the +5V reference supply to resistor RI
A and transistor QZA Current flows through CIN. Current also flows from the 5V reference power supply through resistor R2A and transistor QIA to the INB power supply.

From this K, the comparator 140 enters a comparison mode or a sampling mode. The differential current between the IN and INB inputs then creates a differential voltage between the respective collectors of transistors Q2A and QIA.

Since resistors RIB and R2B have a relatively small resistance value .multidot.1, the voltage at the collectors of Q2A and QIA is applied to the bases of transistors Q5 and Q6, respectively. Transistors Q5 and Q6 are emitter
Since they are coupled as followers, the differential voltage applied to their bases appears at the individual emitters. The emitters of transistors Q9 and QIO are coupled to the emitters of transistors Q5 and Q6, respectively, and operate as Zener diodes. A signal of about 4V at the emitters with a differential voltage of about 50-100mV will have a voltage of about 2V at the differential output of their bases, i.e. comparator 140.
signal.

The comparison function in the sampling comparator 140k is as follows:
This is implemented by transistors Q1 and Q2 whose bases are coupled to the emitters of said transistors Q5 and Q6, respectively. A small constant current flowing through the current source transistor Q16 and its emitter VC-connected 3Ω resistor supplies approximately 150μ current to the emitters of the differentially coupled transistor pair Q1 and Q2. The voltage difference between the emitters of transistors Q5 and Q6 resulting from the difference in current flowing to the IN input and INB input is
It appears as a voltage difference between the bases of Q1 and Q2. The collectors of transistors Q1 and Q2 are connected to the bases of transistors Q6 and Q5, respectively, forming a positive feedback loop. Specifically, as the INB current decreases, the voltage drop across resistor R2A decreases, causing the voltage at the base and emitter of transistor Q6 and the voltage at the base of transistor Q2 to increase. The increase in the base voltage across transistor Q2 causes additional current to flow through resistors RIA and R2λ, and reduces the voltage at the base and emitter of transistor Q5 and the base of transistor Q1, respectively. The current source value is chosen to be 5 to keep the loop gain less than 1. The differential coupling transistors Q 1 and Q 2 operate as high gain amplifiers and perform sampling comparison! 6140ha, OL
In response to a high signal on K and a low signal on cLKB, it operates in the C sampling and comparison mode.

The comparator a140 also operates in the °C latch mode in response to the low signal of the clock OLK and the high signal of 0LKB. 4! l, OLK low signal is transmitted through transistor Q2
A and QIA stop the current flowing to their respective IN and INB inputs. Furthermore, the high signal of 0LKB' corresponding to the high signal of CLKB (-0,8V) K is supplied to the base of transistor Q13. Transistor Q13 then supplies a relatively large current to the emitters of transistors Q1 and Q2. This relatively large current causes the loop gain to be greater than 1 in °C and is locked into one of two states depending on the relative imbalance between the base voltages in transistors Q1 and Q2.

The comparator 150 is 1. Operates in complementary state. In particular, comparator 150 responds to a high level clock signal 0LKB and operates in a sample and compare mode;
-0, 8) except for the level reaching the OLK signal, the latch and hold mode operation is performed in response to the clock OLK' signal corresponding to the OLK signal.

The inputs of the data latch 180 are connected to the level shifter transistors Q9 and QIO of the sampling comparator 140.
K-bonded 'C'. The input signal applied to the differential amplifier consisting of transistors Q20 and Q21 is restored to a single level output at the collector of transistor Q20. This restore signal is applied to the well known gFL R8 latch. This latch is "■ BBE Journal of Solid State Circuit J 197
October 3rd, vol.

80-8. No. 5 is a paper by Mr. Skokan [Emitter Function Logic Logic Family]
It is described in Fore L8IJ.

In an embodiment of the present invention, an array of 256 differential amplifiers is used.
[is composed of] The collectors in each differential amplifier are then coupled in a 26 sampler comparator circuit as shown in FIG. Each sampler comparator circuit drives 6 exclusive NOR gates and 18 output buffers. Additionally, additional circuitry provides clock and bias voltages for each of the above circuits. Is9
The figure shows a basic differential amplifier used in a differential amplifier cell.

This basic differential amplifier consists of a differential pair with an active current source.

Detailed circuit diagrams of the additional circuitry used in the above embodiments of the invention are shown in FIGS. 10-16. These circuits, except for the bias supply circuit of FIG. 12, are standard EFL library circuits. This bias supply circuit, except that it supplies the low voltage vC
8 supply circuit. Said low voltage is necessary to drive the current sources of the A/D array. A/D differential amplifier cells operate with currents as low as 200μ and therefore require low voltages. As mentioned above, since the required current is small, the resistance is small and the size of the integrated circuit in which the amplifier cells are arranged can be small.

[Brief explanation of drawings]

Figure 1 ~■ is a function of analog input voltage' [Digital waveform diagram when gray code bit value kll is reached,
FIG. z is a block diagram showing the configuration of a direct flash type converter according to an embodiment of the present invention. 3 is a detailed circuit diagram of the differential amplifier cell 20 shown in FIG. 2, FIG. 4 is a detailed circuit diagram of the differential amplifier cell '30, and FIG. 5 is a detailed circuit diagram of the differential amplifier cell 40. FIG. 6 is a detailed circuit diagram of the differential amplifier cell 50, (Bl is a waveform diagram of its output analog voltage (Vout), and 0 is a digital output diagram related to the analog voltage (Vout). FIG. 7H is a block diagram showing the left lid conversion reference voltage of each cell in the differential amplifier cell shown in FIG.
40.150 and Denitaratch 180.190, Fig. 9 is a basic circuit diagram of a differential amplifier used in a differential amplifier cell, Fig. 10 is a detailed circuit diagram of an EFL/EOL@ path, Fig. Figure 11 is the circuit diagram of the VC8 generator, Figure 12
The figure shows the circuit diagram of the vas' generator, the jv13 figure shows the circuit diagram of the Vbz buffer circuit, the figure 14 shows the circuit diagram of the exclusive NOR circuit, the figure 15 shows the clock signal generator, and the figure 16 shows the Vbz buffer circuit.
FIG. 2 is a circuit diagram of a generator. 300, 330: Current source 8, 9 people, Hirugawa Hiyu Left Pal Card Co., Ltd. agent 4F8! Shihasegawa nσ-7 F/ni, 3 FB 4゛(A Nob Lee-6 b Shima-5 FIG 70 FIG 7DF/ni-7F
FIG? to F/to 7N/Ml
rum FIG-θ F/=9 F/-10F/GJ/

Claims (2)

[Claims] (1) A direct flash type A/D converter that is an analog-digital Gray code encoder that obtains a digital signal corresponding to an analog signal with a predetermined slew rate, and is equipped with the following (a) and (b). (a) an encoding means for converting the applied analog signal from the least significant bit to the most significant bit in parallel to obtain a parallel output; (b) responsive to the voltage of the encoder and as the C slew rate increases; From the least significant bit to the most significant bit′
[Amplifying means for obtaining a parallel bit output with loss of bit precision. (2) The encoding means includes the following (a), one entry), and (
b) A power supply that provides a reference voltage of 2N-1 that increases monotonically with n (however, N is an integer greater than O, n is 1 and n<:2'
an integer in which -1 indicates a predetermined number of the reference voltages). (b) in response to the amplitude of the analog signal being compared with the level of the reference voltage; a plurality of even and odd comparators that produce a second output voltage; a first input terminal for receiving a voltage; and a second input terminal for receiving a first output voltage of the plurality of even comparators and a second output voltage of the plurality of odd comparators. A direct flash type A/D converter according to claim 1.