JPS6334353Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a direct flash type A/D with an independent parallel type A/D encoder for each bit.
Regarding converters.

In simultaneous conversion methods of converting analog voltages to digital representations, all bits of the digital representation are determined at the same time. This method is known as a parallel method because it has a parallel bank of voltage comparators, and each comparator responds to an analog voltage reaching a predetermined voltage level.

N-bit encoder (N is a predetermined integer)
In , there are two digital output states. The maximum analog voltage is divided into two voltage levels. Each level represents a quantized voltage value, and each quantization level is represented by one of the digital output states. A conventional N-bit encoder requires two comparators. Each comparator then determines the conversion to a particular quantization level. Therefore, in the conventional configuration in which the simultaneous conversion method is realized in parallel, an extremely large number of comparators are required when N is large. In fact, when N becomes 6 or more, the number of comparators becomes unfeasibly large. However, since using this method enables ultra-high speed processing, it is highly desirable to overcome this drawback.

Another drawback of the simultaneous conversion method described above is that the outputs of the parallel banks of voltage comparators are not in a compact format, but have the form of 2 ^N -1 binary data signals. The output, typically 2 ^N -1, is encoded by conversion logic into the final bit of binary information in a compact binary format. For large values of N, typically 6 or more, the number of elements required in the conversion logic becomes extremely large due to the large number of inputs and logic combinations.

Thus, high speed A/
D conversion has been difficult to implement because it requires an extremely large number of comparators for a large N encoder and the conversion logic is complex.

The present invention has been devised to overcome the above-mentioned drawbacks, and it is an object of the present invention to provide a direct flash type converter having an independent parallel type A/D encoder for each bit. According to one embodiment of the invention, each independent bit encoder has a level of cross-coupling connected to a single comparator so that the output of the comparator is a compact binary output that is directly encoded. Equipped with a detector. Thus, a single comparator is required for each bit and no conversion logic is required. As a result, a practical direct multi-bit flash converter can be realized.

The illustrated embodiment of the invention provides simultaneous 8-bit,
Gray code, A/D converter. Each bit is encoded by a group of independent parallel analog circuits coupled to a comparator that provides a concise directly encoded output. Since the present invention includes a parallel bit encoder and directly generates an N-bit binary code, it will be referred to as a "direct flash type converter." In this description, the term "transformer" has a general meaning, and the term "encoder"
The term refers to circuitry within the converter.

The combined binary codes in embodiments of the present invention are also units known as "cyclic codes,""intersecting binary codes," or "Gray codes" after the inventor as used herein. It is a distance code. The state of the 4-bit (N=4) Gray code is
The quantization as a function of input voltage is shown in Table 1 below.

Table 1 Gray code analog value (quantization level) 0000 0 0001 1 0011 2 0010 3 0110 4 0111 5 0101 6 0100 7 1100 8 1101 9 1111 10 1110 11 1010 12 1011 13 1001 14 1000 15 Figure 1 shows the augmented analog Figure 3 shows a digital waveform associated with Gray code bit values as a function of input voltage. In the figure, waveform A is associated with the overrange bit, and waveforms B, C, D, and E are each associated with the Gray code of Table 1. Here, waveform B represents the most significant bit, and waveform C is
The next most significant bit is represented, and waveform E represents the least significant bit. In the Gray code as illustrated, only one bit changes in response to an input signal crossing any one predetermined quantization level.

Each bit of the digital display is an independent parallel type A/
It is encoded by a D encoder. In FIG. 1, each digital output bit is characterized by a digital conversion representing analog voltages occurring (FS÷2 ^M-1 ) apart. where FS is the value of the full scale analog signal, M is an integer representing the output digital bit, and M=1 corresponds to the most significant bit. Additionally, the first conversion for each digital bit occurs in FS÷ ^2M .
For example, in a system with a full-scale analog value of 256V, M = 4 and the waveform E in Figure 1
The fourth digital bit corresponding to is 256V÷
16 = 16V to make the first conversion, and the quantization levels are 32V apart.

One advantage of embodiments of the present invention is that the resolution of the 8-bit A/D converter increases bit by bit as the input slew rate increases, with encoding errors resulting from high slew rates appearing first in the least significant bits. This means that it will decrease. This is an advantage over prior art techniques which suffer from errors or glitches when the maximum slew rate is exceeded.

FIG. 2 is a circuit diagram of a flash type A/D converter according to an embodiment of the present invention. In the figure, a plurality of differential amplifier cells 10, 20, 30, 40, 5
0,60,70,80,90,100,110,
120, 130 are coupled to receive input analog signal V _IN . Further, each differential amplifier cell containing an individual differential amplifier is coupled to receive a predetermined set of converted reference voltages. In the embodiment of the present invention, 2 ^N
There is a conversion reference voltage of -1. Here, N is an integer greater than zero, and n is an integer indicating one of the conversion reference voltages, such as 1n2 ^N -1. As discussed in more detail below, each differential amplifier cell generates a differential output signal in response to an applied input analog signal and a received converted reference voltage. Essentially, the differential amplifier within the differential amplifier cell functions as a level detector with a translated reference voltage to a reference level. For example, overrange differential amplifier cell 10
is, if the input analog signal V _IN is full scale 2
56 conversion reference voltage or less, the output signal (IN) at a low voltage level corresponding to the waveform in Figure 1A.
, and if the input signal V _IN is greater than the full-scale conversion reference voltage, a high voltage level output signal is generated. Differential amplifier cell 20 is coupled to a half-scale 128 converted reference voltage and produces a differential output signal corresponding to waveform B of FIG. Similarly, differential amplifier cells 30, 40, 50
generate differential output signals corresponding to waveforms C, D, and E in FIG. 1, respectively.

Differential amplifier cells 20, 30, 40, 50, 6
0 and 70 constitute independent parallel A/D encoders. Each of these differential amplifier cells has an output connected to two sampling comparators. For example, differential amplifier cell 10
are sampling comparators 140 and 15, respectively.
It has output lines IN and INB connected to 0.
The output of differential amplifier cell 20 is also connected to sampling comparators 160 and 170. These sampling comparators have high gains such that the output from the comparator gain element is substantially digital.

The compare mode in these comparators operates in response to being strobed by a positive clock pulse and holds their output until the next positive clock pulse occurs. The sampling comparators 140 and 150 are strobed on opposite edges of the clock signals (CLK and CLKB). Thus, sampling comparator 140
holds a digital output when sampling comparator 150 is comparing its inputs, and vice versa. This sampling operation is performed by analog signal V _IN
sample for 10 nanoseconds.

Data latch 180, 190, 200, 210
are sampling comparators 140 and 15, respectively.
Driven by outputs from 0,160,170. Each data latch is connected to a corresponding sampling comparator and is strobed with a clock signal of opposite phase to the sampling comparator to which it is coupled. Thus, the output of the complementary data latch changes only on alternate clock edges.

The data latch and comparator circuits for bits 2, 3, 4, 5, and 6 are identical to the overrange bit and bit 1 circuits described above. The circuits for the 7th and 8th bits are similar to the 6-bit circuits described above, but in practice, due to the limitations and number of conversions that can be performed within the differential amplifier cell, two differential Amplifier cells 80 and 90 are the seventh
are interconnected to produce an output of digital bits. Similarly, differential amplifier cell 100,1
10, 120, and 130 are interconnected to produce an eighth digital bit output. Note that details of these special differential amplifier cells and the coupling circuit will be described later.

Detailed circuit diagrams of digital amplifier cells 20, 30, 40 are shown in FIGS. 3, 4, and 5, respectively;
The same is also shown in FIG. Each cell is physically and operationally identical, except for the number of differential amplifiers that act as level detectors within each cell and the reference voltages connected to them. This is also evident from Figures 7A-H. Each cell consists of a number of parallel differential amplifiers, i.e. differentially coupled transistor pairs, and has two input sides (i.e.
(an analog voltage input side and a reference voltage input side). On the analog voltage input side of the differential amplifier, the bases of the transistors in each transistor pair are coupled to receive the input analog voltage V _IN . Also, on the reference voltage input side of the differential amplifier, the bases of other transistors in the transistor pair are coupled to receive a converted reference voltage from a multi-voltage reference source. The relative values of these conversion reference voltages represent full-scale analog voltages.
6 is shown in the drawing. The collectors on each side of the differentially coupled transistor pair are coupled together, alternately directly coupled, or cross-coupled. That is, the collectors of each pair of differentially coupled transistors are connected, alternately directly connected and cross-connected, to the collectors of the other pair to form two collector current paths. In other words, if each differentially coupled transistor pair is sequentially numbered to correspond to each monotonically increasing conversion reference voltage it receives, then the collectors of the even numbered transistor pairs on each side of the array are and the collectors of the odd numbered transistors on each side of the array are cross-coupled. The collectors on each side of the array are further interconnected to form a collector current path on each side. These two collector current paths are then each connected to one of the emitters in the transistor pair, and their bases are connected in common. The only exceptions are differential amplifier cells 10 and 20, each of which constitutes a unique differentially coupled transistor pair. In FIG. 3, differentially coupled transistor pairs form high speed alternating current paths. These alternating current paths carry currents i ₁ and i ₂ respectively. The currents i ₁ and i ₂ are passed through pull-up resistors 326 and 32 through transistors 322 and 324, respectively.
8 and developed across resistors 326 and 328, respectively, are applied to the differential input of comparator 140.

In operation, odd currents are summed at the current output node coupled to the input of the comparator. In the circuit of FIG. 3, transistors 310 and 32
A current source 300 coupled to a differentially coupled transistor pair consisting of 0 produces an odd current. For other cells, such as those shown in FIGS. 4 and 5, there are even thresholds and differentially coupled transistor pairs. In these cells, a ground-coupled differential amplifier "dummy" differential amplifier is required to match the condition with an odd number of currents. Especially the fourth
Current sources 330 and 3 in the circuit of FIG.
40 is always switched to one side of this array.

Since the differential voltage between the conversion reference voltages is sufficiently large,
Each differential amplifier can operate as a 100% switch. Each differential amplifier cell operates as follows. That is, when the amplitude of the input analog signal V _IN on one side of a parallel differential amplifier is substantially equal to one of the conversion reference voltages received by that cell on the other side of the amplifier, a "dummy" amplifier A differential amplifier containing a differential amplifier is fully switched such that the same number of currents is drawn on each side of the differential amplifier.
These currents on each side are then added to the output differential current. Since there is always an odd number of currents in the differential amplifier cells, there is a remaining odd differential amplifier on one side that does not switch completely. The remaining differential amplifier has its current flowing through each side, e.g. transistor 322.
and 324 to be equal. This forms an equilibrium condition and the signals applied to the differential inputs of the comparator have equal voltages. However, if the input voltage V _IN is slightly less than or greater than the received conversion reference voltage, a difference voltage is applied to the comparator input. Even though each differential amplifier requires approximately 200 mV for complete switching, the balance can be arbitrarily resolved by the high gain of the sampling comparator. A polarity difference occurs in the comparator output for input analog voltages V _IN that are slightly smaller or larger than the selected conversion reference voltage. This polarity corresponds to an odd or even number of thresholds. As an example, Figure 6A shows the second
A cell corresponding to the differential amplifier cell 50 (M=4) shown in the figure is shown. The signal (Vout) applied to sampling comparator 350 as a function of a monotonically increasing input analog signal is shown in FIG. 6B. As discussed above, Vout passes through zero voltage in response to an input analog voltage substantially equal to one of the received conversion reference voltages. The digital output produced for this cell is shown in Figure 6C.

When more than 32 differential transistor pairs are used in a differential amplifier according to an embodiment of the present invention, the threshold values of adjacent differential transistor pairs are very close to each other. In other words, the more elements are switched at once, the more the switching of sequential elements occurs closer to each other. If the differential transistor pair is in a semi-conducting state where it has not completely switched to either level because the threshold is close to the level of the input signal, its output will take a value halfway between the two levels. When a plurality of differential transistor pairs having threshold values close to the input signal level assume such a semi-conducting state, the outputs of adjacent differential transistor pairs cancel each other out because they are reversely connected to each other. This tendency becomes more severe as the threshold value, ie, the number of reference voltages applied to the differential amplifier cell, increases. This phenomenon appears as a reduction in the effective gain of the entire differential amplifier cell. If the effective gain is reduced too much, it is necessary to identify from the output of the cell to which voltage region the data received by the cell belongs, divided by a set of reference voltages applied to the cell. things become difficult. Therefore,
This problem could be solved by limiting the maximum number of differential amplifiers in the cell to 32 for 256 full-scale analog voltages, as shown for example in Figures 7G and 7H. . this is,
Gives a minimum threshold interval of 80mV. per output bit
To allocate more than 32 quantization levels, a differential amplifier cell for bits 7 and 8 (M=7 and 8) is shown in FIG. In particular, for M=7, monotonically increasing conversion reference voltages are applied alternately to the two differential amplifier cells 80 and 90. The outputs from these cells are then amplified by associated comparators, and the outputs of the comparators are injected into, for example, exclusive NOR gate 4 to generate the seventh encoded bit.
00 and 450 are logically combined. When M=8, the monotonically increasing conversion reference voltage is 4
differential amplifier cells 100, 110, 120, 1
Between 30 and 30. As in the case of M=7, cell 1
The comparator outputs associated with 00, 110, 120, and 130 are logically combined. For example, each output from differential amplifier cells 100 and 130 is
are logically combined by exclusive NOR gates 500 and 550, with each output from cells 110 and 120 being connected to exclusive NOR gates 530 and 540.
logically combined and exclusive by
The outputs of the NOR gates are further logically combined by OR gates 510 and 520 to ultimately produce bit 8.

The conversion reference voltages coupled to the individual differential amplifier cells are shown in Figures 3, 4, 5, 6, and especially 7A-7.
This is shown in Figure H. A minimum threshold spacing of 80 mV in a given differential amplifier cell ensures sufficient gain on a bit-by-bit basis. 32 for the two least significant bits
The reference voltages applied to each set of differential amplifier cells are staggered to form a minimum spacing of 80 mV between the reference voltages of any cell. The logical combination of the four sets of conversion reference voltages at the smallest bit is:
Forming a resolution of 128 quantization levels at 20mV intervals.

FIG. 8 shows the sampling comparators 140 and 1.
50 and a detailed circuit diagram of data latches 180 and 190. The difference output from differential amplifier cell 10 in FIG. 2 is introduced into sampling comparators 140 and 150 via inputs IN and INB. Clock signal CLK is in high state (4.2V),
and +5V when CLKB is low (3.6V)
From the reference power supply to resistor R1A and transistor Q2
Current flows through A to the IN input. Current also flows from the 5V reference power supply to the INB input through resistor R2A and transistor Q1A. This causes the comparator 140 to enter a comparison mode or a sampling mode. The differential current between the IN input and the INB input generates a differential voltage between the collectors of transistors Q2A and Q1A.

Since resistors R1B and R2B have a relatively small resistance value, the voltage at the collectors of Q2A and Q1A is equal to that of transistors Q5 and Q, respectively.
Applied to the base of 6. Transistors Q5 and Q6 are coupled as emitter followers so that the differential voltage applied to their bases appears at their respective emitters. Transistors Q9 and Q1
The emitters of 0 are coupled to the emitters of transistors Q5 and Q6, respectively, and operate as zener diodes. A signal of approximately 4V at the emitters with a differential voltage of approximately 50-100mV is
The difference output of their bases or comparators 140 is converted to a signal of approximately -2V.

The comparison function in the sampling comparator 140 is performed by transistors Q1 and Q2 whose bases are coupled to the emitters of the transistors Q5 and Q6, respectively. connected to the current source transistor Q16 and its emitter
A small constant current flowing through the 3KΩ resistor supplies approximately 150μA of current to the emitters of the differentially coupled transistor pair Q1 and Q2. Transistor Q5 resulting from the difference in current flowing to IN input and INB input
The voltage difference between the emitters of Q6 and Q6 appears as a voltage difference between the bases of transistors Q1 and Q2. The collectors of transistors Q1 and Q2 are connected to the bases of transistors Q6 and Q5, respectively, forming a positive feedback loop. In particular, INB
As the current at the input decreases, the voltage drop across resistor R2A decreases, causing the voltage at the base and emitter of transistor Q6 and the voltage at the base of transistor Q2 to increase. The increase in base voltage across transistor Q2 causes additional current to flow through resistors R1A and R2A, and increases the voltage at the base and emitter of transistor Q5, as well as transistor Q.
1, respectively. The value of the current source is chosen to keep the loop gain less than unity. In this way, the differential coupling transistor Q
1 and Q2 operate as high gain amplifiers, and sampling comparator 140 operates in a sample and compare mode in response to a high signal on CLK and a low signal on CLKB.

The comparator 140 also operates in a latch mode in response to a low signal on clock CLK and a high signal on CLKB. In particular, a low signal on CLK causes transistors Q2A and Q1A to stop flowing current to their respective IN and INB inputs. moreover,
Corresponds to the CLKB high signal (-0.8V)
The high signal on CLKB' is provided to the base of transistor Q13. And the transistor Q13 is
A relatively large current is supplied to the emitters of transistors Q1 and Q2. This relatively large current causes the loop gain to be greater than unity and is locked into one of two states depending on the relative imbalance between the base voltages in transistors Q1 and Q2.

Comparator 150 operates in a complementary state. especially,
Comparator 150 operates in a sample and compare mode in response to a high level clock signal CLKB;
and except for the level that reaches the high (−0.8) state.
The latch and hold mode operations are performed in response to the clock CLK' signal corresponding to the CLK signal.

The input of the data latch 180 is connected to the level shifter transistor Q of the sampling comparator 140.
9 and Q10.
The input signal is applied to a differential amplifier consisting of transistors Q20 and Q21, which is restored to a single level output at the collector of transistor Q20. This restored signal is applied to the well known EFL RS latch, which is described in IEEE Journal of Solid-State Circuits, October 1973, at
This is described in the paper "Emitter Function Logic Logic Family For LSI" by Mr. Skokan in Vol. SC-8, No. 5.

An embodiment of the invention is configured as a 256 differential amplifier array. The collectors of each differential amplifier are then coupled in 26 sampler comparator circuits as shown in FIG. Each sampler comparator circuit drives 6 exclusive NOR gates and 18 output buffers. Additionally, additional circuitry provides clock and bias voltages for the circuitry. FIG. 9 shows a basic differential amplifier used in a differential amplifier cell. This basic differential amplifier consists of a differential pair with an active current source.

Detailed circuit diagrams of the additional circuits used in the above embodiments of the invention are shown in FIGS. 10-16. These circuits are standard EFL library circuits with the exception of the bias supply circuit of FIG. This bias supply circuit is the same as the VCS supply circuit shown in FIG. 11, except that it supplies a lower voltage. Said low voltage is necessary to drive the current sources of the A/D array. A/D differential amplifier cells operate with only 200 μA of current and therefore require low voltages. As mentioned above, the required current is small, so the resistance is small and the size of the integrated circuit in which the amplifier cells are arranged can be small.

[Brief explanation of the drawing]

1A to 1E are digital waveform diagrams related to Gray code bit values as a function of analog input voltage; FIG. 2 is a block diagram showing the configuration of a direct flash converter according to an embodiment of the present invention; Figure 3 shows the differential amplifier cell 20 shown in Figure 2.
The detailed circuit diagram of FIG. 4 is also the differential amplifier cell 3.
0, FIG. 5 is a detailed circuit diagram of the differential amplifier cell 40, FIG. 6A is a detailed circuit diagram of the differential amplifier cell 50, and B is its output analog voltage (Vout).
C is a digital output diagram related to the analog voltage (Vout). Figure 7A-7
Figure H is a block diagram showing the conversion reference voltage on the left side of each cell in the differential amplifier cell shown in Figure 2.
FIG. 8 shows the sampling comparator 14 shown in FIG.
0,150 and data latches 180, 190, FIG. 9 is a basic circuit diagram of the differential amplifier used in the differential amplifier cell, and FIG.
Detailed circuit diagram of EFL/ECL circuit, Figure 11 is VCS
The circuit diagram of the generator, Fig. 12 is the circuit diagram of the VCS' generator, and Fig. 13 is the circuit diagram of the Vb ₂ buffer circuit.
FIG. 4 is a circuit diagram of an exclusive NOR circuit, FIG. 15 is a circuit diagram of a clock signal generator, and FIG. 16 is a circuit diagram of a Vb ₂ generator. 300, 330: Current source.

Claims (1)

[Claims for Utility Model Registration] A reference power source that provides a plurality of different reference voltages, each differential output terminal being alternately directly connected or cross-connected to the first line and the second line so that the analog input signal and the reference voltage are one or more level detectors for deriving a signal indicating the result of comparison between the two lines to the first line and the second line, and indicating the magnitude relationship between the outputs on the first line and the second line. In an A/D converter that converts an analog signal into a digital code by providing a plurality of comparison means for providing comparison outputs, for at least the least significant bit of the N-bit output of the digital code, the plurality of comparison means are provided. and a logic circuit for obtaining a corresponding bit output of a digital code by performing a logical operation on the comparison outputs of the plurality of comparison means, and for determining the value of the bit of the digital code among the plurality of reference voltages. A necessary group of reference voltages is distributed to the plurality of comparison means, and when the group of reference voltages are arranged in order of voltage value, adjacent reference voltages are applied to different comparison means. A/D converter.