JPS6226941U - - Google Patents
Info
- Publication number
- JPS6226941U JPS6226941U JP12187786U JP12187786U JPS6226941U JP S6226941 U JPS6226941 U JP S6226941U JP 12187786 U JP12187786 U JP 12187786U JP 12187786 U JP12187786 U JP 12187786U JP S6226941 U JPS6226941 U JP S6226941U
- Authority
- JP
- Japan
- Prior art keywords
- line
- reference voltages
- comparison
- gray code
- comparison means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 16
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Description
第１図Ａ〜Ｅはアナログ入力電圧の関数として
グレイコードのビツト値に関連したデイジタル波
形図、第２図は本考案の一実施例によるダイレク
ト・フラツシユ形変換器の構成を示すブロツク図
、第３図は第２図に示した差動増幅器セル２０の
群細回路図、第４図は同じく差動増幅器セル３０
の詳細回路図、第５図は差動増幅器セル４０の詳
細回路図、第６図Ａは差動増幅器セル５０の詳細
回路図、Ｂはその出力アナログ電圧（Ｖｏｕｔ）
の波形図、Ｃは前記アナログ電圧（Ｖｏｕｔ）に
関連したデイジタル出力図である。第７Ａ〜第７
Ｈ図は第２図に示した差動増幅器セルにおいて各
セルの左側に変換基準電圧を示したブロツク図、
第８図は第２図に示したサンプリング比較器１４
０，１５０及びデータラツチ１８０，１９０の詳
細回路図、第９図は差動増幅器セルに使用されて
いる差動増幅器の基本回路図、第１０図はＥＦＬ
／ＥＣＬ回路の詳細回路図、第１１図はＶＣＳ発
生器の回路図、第１２図はＶＣＳ′発生器の回路
図、第１３図はＶｂ２バツフア回路の回路図、第
１４図は排他的ＮＯＲ回路の回路図、第１５図は
クロツク信号発生器、第１６図はＶｂ２発生器の
回路図である。
３００，３３０……電流源。
1A to 1E are diagrams of digital waveforms related to Gray code bit values as a function of analog input voltage; FIG. 2 is a block diagram showing the configuration of a direct flash converter according to an embodiment of the present invention; 3 is a detailed circuit diagram of the differential amplifier cell 20 shown in FIG. 2, and FIG. 4 is a detailed circuit diagram of the differential amplifier cell 30 shown in FIG.
5 is a detailed circuit diagram of the differential amplifier cell 40, FIG. 6A is a detailed circuit diagram of the differential amplifier cell 50, and B is its output analog voltage (Vout).
C is a digital output diagram related to the analog voltage (Vout). 7th A~7th
Figure H is a block diagram showing the conversion reference voltage on the left side of each cell in the differential amplifier cell shown in Figure 2.
FIG. 8 shows the sampling comparator 14 shown in FIG.
0,150 and data latches 180, 190, Figure 9 is a basic circuit diagram of the differential amplifier used in the differential amplifier cell, Figure 10 is the EFL
/ECL circuit detailed circuit diagram, Figure 11 is the VCS generator circuit diagram, Figure 12 is the VCS' generator circuit diagram, Figure 13 is the Vb 2 buffer circuit diagram, Figure 14 is the exclusive NOR circuit. A circuit diagram of the circuit, FIG. 15 is a circuit diagram of a clock signal generator, and FIG. 16 is a circuit diagram of a Vb2 generator. 300, 330... Current source.
Claims (1)
互に直接接続、交差接続されアナログ入力信号と
前記基準電圧の１つとの大小比較結果を示す信号
を前記第１ライン、第２ラインに導出するための
１つ以上のレベル検出器を有し、前記第１ライン
と第２ライン上の出力の大小関係を示す比較出力
を与える複数の比較手段と、 を設けることによりアナログ信号をグレイコード
に変換するＡ／Ｄ変換器において、 前記グレイコードのＮビツト出力の少なくとも
最下位のビツトに対しては、 複数の前記比較手段と、 前記複数の比較手段の比較出力を論理演算する
ことによりグレイコードの対応するビツト出力を
得る論理回路を設け、 前記複数の基準電圧のうちのグレイコードの前
記ビツトの値の決定に必要とされる一群の基準電
圧を前記複数の比較手段に振分け、 前記一群の基準電圧を電圧値の順に並べた場合
に隣接する基準電圧を互いに異なる前記比較手段
に与えられるようにした ことを特徴とするＡ／Ｄ変換器。[Claims for Utility Model Registration] A reference power source that provides a plurality of different reference voltages, each differential output terminal being alternately directly connected or cross-connected to the first line and the second line so that the analog input signal and the reference voltage are one or more level detectors for deriving a signal indicating the result of a comparison between the two lines to the first line and the second line, and indicating the magnitude relationship between the outputs on the first line and the second line; In an A/D converter that converts an analog signal into a Gray code by providing a plurality of comparison means for providing comparison outputs, for at least the lowest bit of the N-bit output of the Gray code, a plurality of the above-mentioned Comparing means and a logic circuit for logically calculating the comparison outputs of the plurality of comparison means to obtain a corresponding bit output of the Gray code, and determining the value of the bit of the Gray code among the plurality of reference voltages. A necessary group of reference voltages is distributed to the plurality of comparison means, and when the group of reference voltages are arranged in order of voltage value, adjacent reference voltages can be applied to different comparison means. A/D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986121877U JPS6334353Y2 (en) | 1986-08-08 | 1986-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986121877U JPS6334353Y2 (en) | 1986-08-08 | 1986-08-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6226941U true JPS6226941U (en) | 1987-02-18 |
| JPS6334353Y2 JPS6334353Y2 (en) | 1988-09-12 |
Family
ID=31011551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986121877U Expired JPS6334353Y2 (en) | 1986-08-08 | 1986-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6334353Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54106159A (en) * | 1978-01-05 | 1979-08-20 | Analog Devices Inc | Parallel analog digital converter |
-
1986
- 1986-08-08 JP JP1986121877U patent/JPS6334353Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54106159A (en) * | 1978-01-05 | 1979-08-20 | Analog Devices Inc | Parallel analog digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6334353Y2 (en) | 1988-09-12 |
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