JPS6189897U - - Google Patents

Info

Publication number
JPS6189897U
JPS6189897U JP17479984U JP17479984U JPS6189897U JP S6189897 U JPS6189897 U JP S6189897U JP 17479984 U JP17479984 U JP 17479984U JP 17479984 U JP17479984 U JP 17479984U JP S6189897 U JPS6189897 U JP S6189897U
Authority
JP
Japan
Prior art keywords
digital data
power
envelope
generation circuit
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17479984U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17479984U priority Critical patent/JPS6189897U/ja
Publication of JPS6189897U publication Critical patent/JPS6189897U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク系統図、
第2炊は従来回路の一例のブロツク系統図、第3
図は第1図、第2図夫々に示す回路の出力するエ
ンベロープ波形の一実施例を示す図である。 1…CPU、3…マルチプレクサ、4a〜4n
…サンプリングホールド回路、5a〜5n,13
…端子、10…二乗回路、11,12…D/A変
換器。
FIG. 1 is a block system diagram of an embodiment of the present invention.
The second section is a block system diagram of an example of a conventional circuit, and the third section is a block system diagram of an example of a conventional circuit.
This figure shows an example of envelope waveforms output from the circuits shown in FIGS. 1 and 2, respectively. 1...CPU, 3...Multiplexer, 4a to 4n
...Sampling hold circuit, 5a to 5n, 13
...terminal, 10...square circuit, 11, 12...D/A converter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 時系列的に供給されるデイジタルデータを順次
アナログ値に変換してエンベロープ波形を生成す
るエンベロープ発生回路において、該デイジタル
データ又は該アナログ値を累乗する累乗回路を設
けてなり、該供給されるデイジタルデータの累乗
値に比例したレベルのエンベロープ波形を生成す
るエンベロープ発生回路。
An envelope generation circuit that sequentially converts digital data supplied in time series into analog values to generate an envelope waveform, is provided with a power circuit that raises the digital data or the analog value to a power, and converts the supplied digital data into analog values. An envelope generation circuit that generates an envelope waveform with a level proportional to the power of .
JP17479984U 1984-11-17 1984-11-17 Pending JPS6189897U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17479984U JPS6189897U (en) 1984-11-17 1984-11-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17479984U JPS6189897U (en) 1984-11-17 1984-11-17

Publications (1)

Publication Number Publication Date
JPS6189897U true JPS6189897U (en) 1986-06-11

Family

ID=30732410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17479984U Pending JPS6189897U (en) 1984-11-17 1984-11-17

Country Status (1)

Country Link
JP (1) JPS6189897U (en)

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