JPS639644U - - Google Patents
Info
- Publication number
- JPS639644U JPS639644U JP10322686U JP10322686U JPS639644U JP S639644 U JPS639644 U JP S639644U JP 10322686 U JP10322686 U JP 10322686U JP 10322686 U JP10322686 U JP 10322686U JP S639644 U JPS639644 U JP S639644U
- Authority
- JP
- Japan
- Prior art keywords
- analog
- memory
- data acquisition
- digital
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の全体構成を示すブロツク図
、第２図は従来のＡ／Ｄ変換回路のブロツク図、
第３図は従来のＡ／Ｄ変換回路の動作フローチヤ
ート、第４図はこの考案の動作フローチヤート、
第５図はこの考案によるＡＣＱメモリへのデータ
の格納方法を示すメモリマツプである。
１：プリアンプ、２：Ａ／Ｄ変換器、３：スイ
ツチ回路、４：ラツチ回路、５：ＡＣＱメモリ、
６：Ｄ／Ａ変換器、７：クロツクジエネレータ、
８：メモリコントローラ、９：アドレスカウンタ
、１０：ＣＰＵ、１１：入力端子、１２：出力端
子、１３：アドレス、１４：ＡＣＱメモリ領域。
Figure 1 is a block diagram showing the overall configuration of this invention, Figure 2 is a block diagram of a conventional A/D conversion circuit,
FIG. 3 is an operation flowchart of a conventional A/D conversion circuit, and FIG. 4 is an operation flowchart of this invention.
FIG. 5 is a memory map showing the method of storing data in the ACQ memory according to this invention. 1: Preamplifier, 2: A/D converter, 3: Switch circuit, 4: Latch circuit, 5: ACQ memory,
6: D/A converter, 7: Clock generator,
8: memory controller, 9: address counter, 10: CPU, 11: input terminal, 12: output terminal, 13: address, 14: ACQ memory area.
Claims (1)
グ・デイジタル変換器により変換されたデイジタ
ル信号を格納するデータアクイジシヨンメモリに
、そのメモリ自身のアドレスを格納することで、
データアクイジシヨンメモリをセルフチエツクで
きることを特徴としたアナログデジタル変換回路
。 By storing the address of the memory itself in the data acquisition memory that stores the digital signal converted by the analog-to-digital converter that converts the analog signal into a digital signal,
An analog-to-digital conversion circuit characterized by the ability to self-check data acquisition memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10322686U JPS639644U (en) | 1986-07-07 | 1986-07-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10322686U JPS639644U (en) | 1986-07-07 | 1986-07-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639644U true JPS639644U (en) | 1988-01-22 |
Family
ID=30975584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10322686U Pending JPS639644U (en) | 1986-07-07 | 1986-07-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639644U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01150659U (en) * | 1988-04-08 | 1989-10-18 |
-
1986
- 1986-07-07 JP JP10322686U patent/JPS639644U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01150659U (en) * | 1988-04-08 | 1989-10-18 |