JPS6326116U - - Google Patents
Info
- Publication number
- JPS6326116U JPS6326116U JP12061086U JP12061086U JPS6326116U JP S6326116 U JPS6326116 U JP S6326116U JP 12061086 U JP12061086 U JP 12061086U JP 12061086 U JP12061086 U JP 12061086U JP S6326116 U JPS6326116 U JP S6326116U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- output
- outputs
- latch circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Radar Systems Or Details Thereof (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案に係る周波数掃引回路の構成例
を示した図、第２図は第１図ステツプ発生部の具
体的構成例を示した図、第３図は本考案の別の構
成例を示した図、第４図と第５図は従来の周波数
掃引回路の構成例を示した図である。
１…ステツプ発生部、２…加算器、３，１４…
ラツチ回路、４，１２…メモリ、５…Ｄ／Ａコン
バータ、１０…アドレスカウンタ、１６…コンパ
レータ。
FIG. 1 is a diagram showing a configuration example of a frequency sweep circuit according to the present invention, FIG. 2 is a diagram showing a specific configuration example of the step generator shown in FIG. 1, and FIG. 3 is another configuration example of the present invention. FIGS. 4 and 5 are diagrams showing configuration examples of conventional frequency sweep circuits. 1...Step generator, 2...Adder, 3, 14...
Latch circuit, 4, 12...Memory, 5...D/A converter, 10...Address counter, 16...Comparator.
Claims (1)
モリ４の出力をアナログ信号に変換するＤ／Ａコ
ンバンタと、前記メモリ４のアドレス信号を出力
するラツチ回路３と、このラツチ回路３の出力と
ステツプ信号ＳＡとを加算して前記ラツチ回路３
に出力する加算器とを備えた周波数掃引回路にお
いて、 アドレスカウンタ１０と、 周波数に対応したステツプの値が書き込まれ、
前記アドレスカウンタ１０の出力に応じて前記加
算器にステツプ信号ＳＡを出力するメモリ１２と
、 を備えたことを特徴とする周波数掃引回路。[Claims for Utility Model Registration] A memory 4 in which waveform data is written, a D/A converter that converts the output of the memory 4 into an analog signal, a latch circuit 3 that outputs an address signal of the memory 4, and By adding the output of the latch circuit 3 and the step signal SA, the latch circuit 3 is
In a frequency sweep circuit equipped with an adder that outputs an output to an address counter 10 and a step value corresponding to the frequency,
A frequency sweep circuit comprising: a memory 12 that outputs a step signal SA to the adder in accordance with the output of the address counter 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12061086U JPS6326116U (en) | 1986-08-06 | 1986-08-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12061086U JPS6326116U (en) | 1986-08-06 | 1986-08-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6326116U true JPS6326116U (en) | 1988-02-20 |
Family
ID=31009086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12061086U Pending JPS6326116U (en) | 1986-08-06 | 1986-08-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326116U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58172004A (en) * | 1982-04-26 | 1983-10-08 | テクトロニクス・インコ−ポレイテツド | Digital signal generator |
-
1986
- 1986-08-06 JP JP12061086U patent/JPS6326116U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58172004A (en) * | 1982-04-26 | 1983-10-08 | テクトロニクス・インコ−ポレイテツド | Digital signal generator |
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