JPH0163225U - - Google Patents
Info
- Publication number
- JPH0163225U JPH0163225U JP1987157785U JP15778587U JPH0163225U JP H0163225 U JPH0163225 U JP H0163225U JP 1987157785 U JP1987157785 U JP 1987157785U JP 15778587 U JP15778587 U JP 15778587U JP H0163225 U JPH0163225 U JP H0163225U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- output
- terminal
- holds
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Description
第１図はこの考案による実施例の回路図、第２
図は従来技術による回路図、第３図と第４図は第
２図各部の波形図、第５図は第１図各部の波形図
である。
１……ＦＦ、２……ＦＦ、３Ａ〜３Ｄ……ゲー
ト、４……ゲート、５……ＦＦ、６……ＦＦ、１
１，１２……入力端子、１３……出力端子。
Figure 1 is a circuit diagram of an embodiment according to this invention, Figure 2 is a circuit diagram of an embodiment according to this invention.
3 is a circuit diagram according to the prior art, FIGS. 3 and 4 are waveform diagrams of various parts in FIG. 2, and FIG. 5 is a waveform diagram of various parts in FIG. 1. 1...FF, 2...FF, 3A~3D...gate, 4...gate, 5...FF, 6...FF, 1
1, 12...input terminal, 13...output terminal.
Claims (1)
Ｆ１と、 前記クロツク信号で第１のＦＦ１の出力を保持
する第２のＦＦ２と、 第２のＦＦ２の出力を第２の端子３２に接続す
る第１のゲート３Ａと、 第２のＦＦ２の出力を第３の端子３３に接続し
、第１のＦＦ１の出力を第４の端子３４に接続す
る第２のゲート３Ｂと、 第１のＦＦ１の出力を第５の端子３５に接続す
る第３のゲート３Ｃと、 第１のゲート３Ａの出力、第２のゲート３Ｂの
出力及び第３のゲート３Ｃの出力を入力とする第
４のゲート４と、 第４のゲート出力を入力とする第３のＦＦ５と
を備え、 第３のＦＦ５の出力を第１のゲート３Ａの第１
の端子３１と第３のゲート３Ｃの第６の端子３６
に接続することを特徴とするパルス性ノイズ除去
回路。[Claims for Utility Model Registration] First F that holds a data signal using a clock signal
F1, a second FF2 that holds the output of the first FF1 with the clock signal, a first gate 3A that connects the output of the second FF2 to the second terminal 32, and an output of the second FF2. is connected to the third terminal 33, and the output of the first FF1 is connected to the fourth terminal 34, and the third gate 3B is connected to the output of the first FF1 to the fifth terminal 35. a fourth gate 4 whose inputs are the output of the first gate 3A, the output of the second gate 3B, and the output of the third gate 3C; and a third gate 4 whose inputs are the output of the fourth gate. FF5, and the output of the third FF5 is connected to the first gate of the first gate 3A.
terminal 31 and the sixth terminal 36 of the third gate 3C
A pulse noise removal circuit characterized by being connected to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157785U JPH0163225U (en) | 1987-10-15 | 1987-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157785U JPH0163225U (en) | 1987-10-15 | 1987-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0163225U true JPH0163225U (en) | 1989-04-24 |
Family
ID=31437530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987157785U Pending JPH0163225U (en) | 1987-10-15 | 1987-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0163225U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009124380A (en) * | 2007-11-14 | 2009-06-04 | Seiko Epson Corp | Noise reduction circuit and electronic equipment |
-
1987
- 1987-10-15 JP JP1987157785U patent/JPH0163225U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009124380A (en) * | 2007-11-14 | 2009-06-04 | Seiko Epson Corp | Noise reduction circuit and electronic equipment |
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