JPS63185322U - - Google Patents
Info
- Publication number
- JPS63185322U JPS63185322U JP7557887U JP7557887U JPS63185322U JP S63185322 U JPS63185322 U JP S63185322U JP 7557887 U JP7557887 U JP 7557887U JP 7557887 U JP7557887 U JP 7557887U JP S63185322 U JPS63185322 U JP S63185322U
- Authority
- JP
- Japan
- Prior art keywords
- utility
- model registration
- level
- transistor
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の回路図、第２図と
第３図は第１図の回路を説明するための信号波形
図である。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining the circuit of FIG. 1.
Claims (1)
接続して該両抵抗の共通接続点から３値信号を取
り出すように構成したことを特徴とする論理回路
。 (2) 上記共通接続点が、レベル検知回路を介し
てトランジスタに接続されていることを特徴とす
る実用新案登録請求の範囲第１項記載の論理回路
。 (3) 上記レベル検知回路が、上記３値信号の中
間値と「Ｈ」値との間のレベルを検知して上記ト
ランジスタをオンさせることを特徴とする実用新
案登録請求の範囲第２項記載の論理回路。 (4) 上記レベル検知回路が、上記３値信号の中
間値と「Ｌ」値との間のレベルを検知して上記ト
ランジスタをオンさせることを特徴とする実用新
案登録請求の範囲第２項記載の論理回路。[Claims for Utility Model Registration] (1) A logic characterized in that the output sides of two inverters are connected through two resistors and a ternary signal is extracted from a common connection point between the two resistors. circuit. (2) The logic circuit according to claim 1, wherein the common connection point is connected to a transistor via a level detection circuit. (3) Claim 2 of the utility model registration, characterized in that the level detection circuit detects a level between the intermediate value and the "H" value of the ternary signal and turns on the transistor. logic circuit. (4) Claim 2 of the utility model registration, characterized in that the level detection circuit detects a level between the intermediate value and the "L" value of the ternary signal and turns on the transistor. logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7557887U JPS63185322U (en) | 1987-05-20 | 1987-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7557887U JPS63185322U (en) | 1987-05-20 | 1987-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185322U true JPS63185322U (en) | 1988-11-29 |
Family
ID=30921852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7557887U Pending JPS63185322U (en) | 1987-05-20 | 1987-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185322U (en) |
-
1987
- 1987-05-20 JP JP7557887U patent/JPS63185322U/ja active Pending
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