JP2009124380A - Noise reduction circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce noise included in both the voltage levels of signals entering a transmission path. <P>SOLUTION: A noise reduction circuit includes: a delay unit 14 delaying an input signal; an AND unit 10 for calculating the AND of the input signal and the output signal of the delay unit; an OR unit 12 for calculating the OR of the input signal and the output signal of the delay unit; and a selection unit SEL for selecting and outputting one of a first output signal output from the AND unit and a second one output from the OR unit. The selection unit outputs the first and second output signals, when the output signals of the selection unit are first and second voltage levels, respectively. In the delay unit, a plurality of delay circuits DL10_1 to DL10_N are cascade-connected, and taps Tp1 to Tp (N-1) among respective delay circuits are connected to the input terminals of the AND and OR units each. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a noise reduction circuit, an electronic device, and the like.

  When various types of signals such as control signals and image signals are transmitted along with the recent improvement in performance of various electronic devices such as image processing apparatuses such as printers, digital cameras, electronic notebooks, electronic dictionaries, and portable information terminals. Higher accuracy is required. When transmitting signals from these electronic devices, extra signal components that were not included in the original signal are added as noise due to the characteristics of the transmission path such as communication cables and the external environment. May be. If such noise is added to the signal and transmitted, the desired performance output by the transmission of the original signal cannot be obtained, and problems such as malfunctions occur in the electronic devices. It was.

In order to prevent malfunction when such noise is added to the signal, when the internal pulse generation circuit receives noise from the clock terminal, the internal pulse signal is generated, and the noise change canceling circuit is added to the internal pulse signal. Accordingly, Patent Document 1 discloses a conventional technique for generating a pulse signal so as to cancel a logical change due to noise of an internal synchronization signal.
JP-A-6-060670

  However, in the prior art disclosed in Patent Document 1 described above, a pulse signal is generated so as to cancel a logical change due to noise, so that malfunction due to noise is prevented, and noise itself is not reduced. In the related art, a digital signal having a waveform in which an input signal reciprocates between two voltage levels of a high voltage side and a low voltage side (hereinafter, the respective voltage levels are referred to as a high voltage side level and a low voltage side level). In this case, the noise reduction of the signal at either the high voltage side or the low voltage side of the digital signal is stopped. In other words, in the related art, the reduction of noise at both the high voltage side and the low voltage side of the digital signal (hereinafter, noise at each voltage level is referred to as high voltage side noise and low voltage side noise). Not executed. That is, the noise of the other voltage level different from the one voltage level at which noise reduction is performed remains in the signal, and the reduction of the noise included in the signal is insufficient.

  According to some aspects of the present invention, noise included in both voltage levels of a signal entering a transmission line with a simple circuit configuration is reduced.

  The present invention relates to a noise reduction circuit that reduces noise included in an input signal, a delay unit that delays the input signal, a logical product unit that takes a logical product of the input signal and the output signal of the delay unit, and an input signal. Selecting one of a logical sum unit that takes a logical sum of the output signal of the delay unit and a first output signal output from the logical product unit or a second output signal output from the logical sum unit. And a selection unit that outputs a first output signal when the output signal of the selection unit is at a first voltage level, and when the output signal of the selection unit is at a second voltage level. The second output signal is output, and the delay unit is configured by cascading a plurality of delay circuits, and taps between the delay circuits are AND units and Related to the noise reduction circuit, characterized in that are connected to the input terminal of Liwa unit.

  According to the noise reduction circuit of the present invention, two logic circuits having opposite noise reduction characteristics according to the voltage level of the signal are arranged in parallel, and the logic with the better noise reduction is based on the voltage level of the output signal. The output signal from the unit is output. With this configuration, when a signal on which high-voltage side noise and low-voltage side noise are superimposed is input, the noise reduction efficiency at the voltage level depends on the voltage level of the output signal of the selection unit. The output signal from the better logic unit is output from the selection unit. For this reason, noise superimposed on both voltage levels of the signal can be efficiently reduced. Further, in order to adjust the delay amount of the input signal to a desired magnitude, the noise reduction circuit of the present embodiment has a configuration in which the delay unit is configured by cascading a plurality of delay circuits, and the output signals of the plurality of delay circuits. The logical sum and logical product with the input signal are taken. Therefore, in the logical product unit and the logical sum unit, noise can be reduced in accordance with various noise generation patterns such as the pulse width and number of noise superimposed on the signal. Furthermore, the noise reduction circuit of the present embodiment is configured to share a delay unit that is connected to the logical product unit and the logical sum unit and is used when the input signal is delayed. Therefore, it is possible to efficiently reduce noise superimposed on both voltage levels of the signal after reducing the circuit scale.

  In the present invention, the logical product unit includes an AND circuit to which the input signal and the output signals of the plurality of delay circuits provided in the delay unit are input, respectively, and the logical sum unit is provided in the input signal and the delay unit. It is possible to include an OR circuit to which the output signals of the delay circuit are respectively input.

  In this way, the low voltage side noise is reduced by taking the logical product of the input signal from the AND circuit and the output signal of the delay unit, and the logical sum of the input signal from the OR circuit and the output signal of the delay unit is taken. Accordingly, the reduction of the high-voltage side noise is performed in each logic unit. For this reason, even when the number of noise pulses superimposed on the input signal is large, noise at both voltage levels of the input signal can be efficiently reduced.

  In the present invention, the delay unit is configured by cascading N (N is an integer) delay circuits, and the logical product unit is configured by cascading N AND circuits. The unit is configured by cascading N OR circuits, and the first AND circuit from the input stage takes the logical product of the input signal and the output signal from the first delay circuit from the input stage. The i-th (2 ≦ i ≦ N) AND circuit takes the logical product of the output signal of the (i−1) -th AND circuit from the input stage and the output signal of the i-th delay circuit from the input stage, and The first OR circuit takes the logical sum of the input signal and the output signal from the first delay circuit from the input stage, and the i-th OR circuit from the input stage is the i-1th OR circuit from the input stage. I-th output signal and input stage It may take the logical sum of the output signal of the extending circuit.

  In this way, even when the number of noise pulses superimposed on the input signal is large, the low voltage side noise reduction in the logical product unit and the high voltage side noise reduction in the logical sum unit are more reliably performed. After that, the output signal is selected by the selection unit. For this reason, even when the number of noise pulses superimposed on the input signal is large, the noise superimposed on both voltage levels of the signal can be more reliably reduced.

  In the present invention, the delay unit is configured by cascading 2M (M is an integer) delay circuits via inverter circuits, and the logical product unit includes M logical NAND circuits. The M logical NOR circuits are cascaded so as to be alternately arranged so that the logical AND NAND circuits are arranged first from the input stage, and the logical sum unit includes M logical NOR circuits. And M logical NAND circuits are arranged in cascade so that they are alternately arranged from the input stage so that the logical NOR circuits are arranged first, and the first logical NAND circuit from the input stage is The negative AND of the input signal and the output signal from the first delay circuit from the input stage is taken, and the jth (2 ≦ j ≦ M) AND NAND circuit from the input stage is j−1 from the input stage. Number The logical product of the output signal of the logical product NOR circuit and the output signal from the 2j-1st delay circuit from the input stage is obtained, and the kth (1 ≦ k ≦ M) logical product NOR circuit of the input stage is obtained. Takes the negative OR of the output signal of the k-th NAND circuit from the input stage and the output signal from the 2k-th delay circuit from the input stage, and the first NOR circuit from the input stage is: The negative OR of the input signal and the output signal from the first delay circuit from the input stage is taken, and the jth (2 ≦ j ≦ M) NOR circuit for the logical sum is j−1th from the input stage. NAND gate of the output signal from the 2j-1st delay circuit from the input stage and the kth (1 ≦ k ≦ M) logical sum NAND circuit from the input stage Is the output signal of the k-th NOR circuit from the input stage and the 2k-th from the input stage. It may take the negative logical sum of the output signals from the extension circuit.

  In this way, since the negative logic circuits that are opposite to each other between the logical product unit and the logical sum unit are cascade-connected, the characteristics of the logical product unit and the logical sum unit can be made substantially the same. For this reason, it is possible to more reliably reduce noise on both voltage levels included in the input signal.

  At this time, in the present invention, the selection unit includes first and second AND circuits serving as input stages, and a selection OR circuit serving as an output stage, and the first AND circuit is connected to one input terminal. The first output signal is input, the inverted signal of the output signal of the selection OR circuit is input to the other input terminal, and the logical product of the first output signal and the inverted signal of the output signal of the selection OR circuit is obtained. The second AND circuit receives the second output signal at one input terminal and the output signal from the selection OR circuit at the other input terminal. The logical product of the second output signal and the output signal of the selection OR circuit is taken and output to the other input terminal of the selection OR circuit, and the selection OR circuit receives the output signal of the first AND circuit and the first AND circuit. Select the logical sum with the output signal of 2 AND circuit and select May be an output signal of the OR circuit is output as an output signal of the selection unit.

  In the present invention, the selection unit includes first and second AND circuits serving as input stages, and a selection NOR circuit serving as an output stage. 1 is input, the output signal of the selection NOR circuit is input to the other input terminal, and one of the selection NOR circuits is obtained by ANDing the first output signal and the output signal of the selection NOR circuit. In the second AND circuit, the second output signal is input to one input terminal, the inverted signal of the output signal of the selection NOR circuit is input to the other input terminal, and the second AND circuit The logical product of the output signal and the inverted signal of the output signal of the selection NOR circuit is obtained and output to the other input terminal of the selection NOR circuit, and the selection NOR circuit outputs the output signal of the first AND circuit and the second signal. The signal is output by taking the negative logical sum with the output signal of the AND circuit May be inverted signal of the output signal of the NOR circuit is output as an output signal of the selection unit.

  Further, according to the present invention, the selection unit includes first and second OR circuits serving as input stages, and a selection AND circuit serving as an output stage, and the first OR circuit includes a first OR circuit connected to one input terminal. The inverted signal of the output signal of 1 is input, the inverted signal of the output signal of the selection AND circuit is input to the other input terminal, the inverted signal of the first output signal and the inverted signal of the output signal of the selection AND circuit, Is output to one input terminal of the selection AND circuit, and the second OR circuit receives the inverted signal of the second output signal at one input terminal and the selection at the other input terminal. The output signal of the AND circuit is input, and the logical sum of the inverted signal of the second output signal and the output signal of the selection AND circuit is output to the other input terminal of the selection AND circuit. , The output signal of the first OR circuit and the second OR circuit Outputs a signal takes a logical product of the force signal, may be inverted signal of the output signal of the selection AND circuit is output as an output signal of the selection unit.

  In the present invention, the selection unit includes first and second OR circuits serving as input stages and a selection NAND circuit serving as an output stage, and the first OR circuit includes a first OR circuit connected to one input terminal. The inverted signal of the output signal of 1 is input, the output signal of the selection NAND circuit is input to the other input terminal, and the logical sum of the inverted signal of the first output signal and the output signal of the selection NAND circuit is obtained. Output to one input terminal of the selection NAND circuit, and the second OR circuit receives the inverted signal of the second output signal at one input terminal and the output signal of the selection NAND circuit at the other input terminal. The inverted signal is input, the logical sum of the inverted signal of the second output signal and the inverted signal of the output signal of the selection NAND circuit is taken and output to the other input terminal of the selection NAND circuit, and the selection NAND circuit The output signal of the first OR circuit and the output of the second OR circuit Outputs a signal takes a negative logical product of the signal may be the output signal of the NAND circuit selected is output as an output signal of the selection unit.

  As described above, when the output signal from the selection unit is at the first voltage level, the selection unit selects the output signal from the AND unit having the characteristics excellent in reducing the low-voltage side noise. When the output signal is at the second voltage level, it is possible to select and output the output signal from the OR unit having the characteristics excellent in reducing the high-voltage side noise. For this reason, it becomes possible to output the output signal of the noise reduction circuit as a signal with reduced noise superimposed on both voltage levels.

  In the present invention, the delay circuit may be configured by connecting a plurality of delay elements in series.

  In this way, the delay amount of the input signal from the previous stage can be adjusted to a desired magnitude by the delay circuit included in the delay unit, so that the signal corresponding to various noise pulse widths and number of pulses can be adjusted. It becomes possible to reduce the noise contained in.

  According to another aspect of the invention, there is provided an electronic apparatus comprising: the noise reduction circuit according to any one of the above; and a device that operates based on a signal whose noise is reduced by the noise reduction circuit.

  According to the electronic apparatus including the noise reduction circuit of the present invention, noise on both voltage levels included in the signal is reduced by the noise reduction circuit, so that the signal transmitted to each device included in the electronic apparatus It is possible to suppress malfunction of the device due to inclusion of noise.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as means for solving the present invention. Not necessarily.

1. First Configuration Example FIG. 1 shows a first configuration example of the noise reduction circuit of this embodiment. The noise reduction circuit of this embodiment is provided in an interface unit or the like that receives an input signal from a transmission line such as a communication cable, and includes a logical product unit 10, a logical sum unit 12, a delay unit 14, and a selection unit SEL. It is the structure containing these. In this configuration example, as shown in FIG. 1, the delay unit 14 has a configuration in which a plurality (N: N is an integer) of delay circuits DL10 are cascade-connected, and the logical product unit 10 and the logical sum unit 12 are delayed. The delay circuits DL10 of the unit 14 are provided in parallel so as to share them. In these logic units 10 and 12, the logical product and logical sum of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10 are respectively taken, and the output signal ANDS10 that is the logical product / logical sum result. , ORS10 is input to the selection unit SEL. The noise reduction circuit of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The delay unit 14 has a function of delaying the input signal S10, and has a configuration in which N delay circuits DL10 are cascade-connected as described above. Output signals DLS10_1 to DLS10_N of each delay circuit DL10 are input to the logical product unit 10 and the logical sum unit 12, respectively. In addition, the delay circuit DL10 included in the delay unit 14 has, for example, a plurality of inverters INV1, INV2 as delay elements, as shown in FIG. 2, in order to adjust the delay amount of the input signal S10 to a desired magnitude. ,... INVn is connected in series. In this configuration example, for example, the delay amount by the delay circuit DL10 is adjusted to a delay amount larger than the pulse width of the desired noise. In this way, the delay amount of the input signal S10 can be adjusted to a desired magnitude by connecting the plurality of inverters INV1, INV2,..., INVn in series to the delay circuit DL10. For this reason, it is possible to reduce the noise included in the input signal S10 in accordance with various pulse widths and the number of noises. The delay circuit DL10 is not limited to the configuration shown in FIG. 2, and various modifications such as omitting some of the components or adding other components are possible. A delay circuit included in another configuration example of the noise reduction circuit of the present invention to be described later also has the same configuration as the delay circuit of the above-described configuration example.

  The logical product unit 10 takes a logical product of the input signal S10 and the output signals DLS10_1 to S10_N of each delay circuit DL10, and outputs the output signal ANDS10 (first output signal in a broad sense) to the selection unit SEL. In this configuration example, the logical product unit 10 includes an AND circuit AND10 to which the input signal S10 and the output signals DLS10_1 to DLS10_N of the delay circuit DL10 are input. The input terminal of the AND circuit AND10 is connected to the taps Tp1 to Tp (N-1) between the delay circuits DL10. The AND circuit AND10 takes a logical product of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10, and outputs a signal ANDS10 that is the output result of the logical product to the selection unit SEL.

  The logical sum unit 12 takes a logical sum of the input signal S10 and the output signals DLS10_1 to DLS10_N of the delay circuit DL10, and outputs the output signal ORS10 (second output signal in a broad sense) to the selection unit SEL. In this configuration example, the OR unit 12 includes an OR circuit OR10 to which the input signal S10 and the output signals DLS10_1 to DLS10_N of the delay circuit DL10 are input. The input terminal of the OR circuit OR10 is connected to the taps Tp1 to Tp (N-1) between the delay circuits DL10. Then, the OR circuit OR10 takes the logical sum of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10, and outputs the signal ORS10 that is the output result of the logical sum to the selection unit SEL.

  The selection unit SEL selects and outputs either the output signal ANDS10 from the logical product unit 10 or the output signal ORS10 from the logical sum unit 12 based on the voltage level of the output signal S12 from the selection unit SEL. The selection unit SEL selects the signal ANDS10 that is the output result of the AND unit 10 when the output signal S12 of the selection unit SEL is at the low voltage side level (first voltage level in a broad sense), and the selection unit SEL When the output signal S12 is at the high voltage side level (second voltage level in a broad sense), the signal ORS10 that is the output result of the OR unit 12 is selected. Details of the configuration of the selection unit SEL will be described later.

  In the noise reduction circuit of this configuration example described above, the input signal S10 is a digital signal that reciprocates between two voltage levels, a high voltage side level and a low voltage side level, and the digital signal S10 includes a high voltage side noise NZH10 and a low voltage level. Assume that the voltage side noise NZL10 is input in a state where both are superimposed.

  In this case, in the logical product unit 10, the logical product of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10 that delays the input signal S10 is obtained by the AND circuit AND10. As described above, the AND operation of AND circuit AND10 reduces the number of pulses of low-voltage side noise NZL10 while increasing the number of pulses of high-voltage side noise NZH10. That is, in the logical product unit 10, the input signal S10 is output as the signal ANDS10 in which the number of pulses of the low voltage side noise NZL10 is reduced.

  On the other hand, in the OR unit 12, the OR circuit OR10 takes the logical sum of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10 that delays the input signal S10. In this manner, by taking the logical sum of the input signal S10 and the output signals DLS10_1 to DLS10_N of each delay circuit DL10 in the OR circuit OR10, the number of pulses of the high voltage side noise NZH10 is reduced, while the low voltage side noise NZL12 The number of pulses increases. That is, in the logical sum unit 12, the input signal S10 is output as the signal ORS10 in which the number of pulses of the high-voltage side noise NZH10 is reduced.

  Thereafter, the signals ANDS10 and ORS10 output from the logical product unit 10 and the logical sum unit 12 are input to the selection unit SEL. The selection unit SEL selects either the signal ANDS10 output from the logical product unit 10 or the signal ORS10 output from the logical sum unit 12 based on the voltage level of the output signal S12 of the selection unit SEL. Output.

  In the present configuration example, when the voltage level of the output signal S12 of the selection unit SEL is the low voltage side level, the selection unit SEL outputs the output signal from the logical product unit 10 having excellent characteristics for reducing the low voltage side noise NZL10. The ANDS 10 is selected and output. On the other hand, when the output signal S12 of the selection unit SEL is at the high voltage side level, the selection unit SEL selects the output signal ORS10 from the logical sum unit 12 having excellent characteristics in reducing the high voltage side noise NZH10. Output. That is, in the selection unit SEL, the output signal from the logic unit having the better noise reduction efficiency at the voltage level is selected according to the voltage level of the output signal S12. The high voltage side noise NZH10 and the low voltage side noise NZL10 are reduced signals. In other words, even when the signal S10 on which the high voltage side noise NZH10 and the low voltage side noise NZL10 are superimposed is input, it is superimposed on both voltage levels of the signal S10 according to the voltage level of the output signal S12 from the selection unit SEL. Noise NZH10 and NZL10 can be reduced efficiently.

  In particular, in the present configuration example, as described above, the taps Tp1 to Tp (N−1) between the plurality of delay circuits DL10 cascaded to adjust the input signal S10 to a desired delay amount are connected to the AND unit 10. And it is the structure connected to the input terminal of the logical sum unit 12, respectively. In other words, the logical product unit 10 and the logical sum unit 12 can perform a logical product / logical sum of all the output signals DLS10_1 to DLS10_N of each delay circuit DL10 and the input signal S10. For this reason, in the logical product unit 10 and the logical sum unit 12, noise can be reduced in accordance with various noise generation patterns such as the pulse width and number of noises superimposed on the input signal S10. Further, since the delay unit DL10 used by the logical product unit 10 and the logical sum unit 12 is shared, it is possible to efficiently reduce noise superimposed on both voltage levels of the signal after reducing the circuit scale. Become.

2.1. Second Configuration Example FIG. 3 shows a second configuration example of the noise reduction circuit of this embodiment. In the noise reduction circuit of this configuration example, N AND circuits AND10_1 to AND10_N each including N in the logical product unit 20, the logical sum unit 22, and the delay unit 24 in order to reduce noise at both voltage levels more reliably. The configuration includes OR circuits OR10_1 to OR10_N and delay circuits DL10_1 to DL10_N. That is, the AND unit 20 cascades N AND circuits AND10_1 to AND10_N, the OR unit 22 cascades N OR circuits OR10_1 to OR10_N, and the delay unit 24 includes N delay circuits. In this configuration, DL10_1 to DL10_N are cascade-connected. The taps Tp1 to Tp (N−1) between the delay circuits DL10_1 to DL10_N of the delay unit 24 are the AND circuits AND10_1 to AND10_N of the AND unit 20 and the OR circuits OR10_1 to OR10_N of the OR unit 22, respectively. The input terminal is connected to each other. In this configuration example, the AND circuit AND10_1 to AND10_N and the OR circuits OR10_1 to OR10_N are cascade-connected to each of the N logical product units 20 and the logical sum units 22, and therefore, the logical configuration unit 20 and the logical sum unit 22 are logically connected to the first configuration example. Is equivalent.

  When connecting the taps Tp1 to Tp (N−1) between the delay circuits DL10 to the input terminal of the AND unit 20, the first tap Tp1 from the input stage is connected to the first AND circuit AND10_1 from the input stage. Connected to input terminal. Therefore, the first AND circuit AND10_1 from the input stage takes a logical product of the input signal S20 and the output signal DLS10_1 from the first delay circuit DL10_1 from the input stage. The i-th tap Tpi (for example, Tp2) from the input stage is connected to the input terminal of the i-th AND circuit AND10_i (for example, AND10_2) from the input stage. Therefore, the i-th AND circuit AND10_i from the input stage is connected to the output signal ANDS10_ (i-1) (for example, ANDS10_1) of the (i-1) -th AND circuit AND10_ (i-1) (for example, AND10_1) from the input stage. The logical product of the output signal DLS10_i (for example, DLS10_2) from the i-th delay circuit DL10_i (for example, DL10_2) from the input stage is obtained.

  On the other hand, when these taps Tp1 to Tp (N−1) are connected to the input terminal of the OR unit 22, the first tap Tp1 from the input stage is connected to the input terminal of the first OR circuit OR10_1 from the input stage. Connected. Therefore, the first OR circuit OR10_1 from the input stage takes a logical sum of the input signal S20 and the output signal DLS10_1 from the first delay circuit DL10_1 from the input stage. The i-th tap Tpi from the input stage is connected to the input terminal of the i-th OR circuit OR10_i (for example, OR10_2) from the input stage. Therefore, the i-th OR circuit OR10_i from the input stage is connected to the output signal ORS10_ (i-1) (for example, ORS10_1) of the i-1th OR circuit OR10_ (i-1) (for example, OR10_1) from the input stage. The logical sum of the output signal DLS10_i (for example, DLS10_2) from the i-th delay circuit DL10_i (for example, DL10_2) from the input stage is calculated.

  As described above, in this configuration example, the logical product unit 20 and the logical sum unit 22 are configured to cascade N AND circuits AND10_1 to AND10_N and OR circuits OR10_1 to OR10_N, respectively. The i-th tap Tpi from the input stage between the delay circuits DL10_1 to DL10_N of the delay unit 24 is connected to the input terminal of the i-th AND circuit AND10_i and the OR circuit OR10_i from the input stage. With such a configuration, even when the number of noise pulses superimposed on the input signal S20 is large or the pulse width is large, the low voltage side noise is reduced by the logical product unit 20, and the logical sum unit 22 increases the noise. After the voltage side noise is more reliably reduced, one of the output signals ANDS10_N and ORS10_N of each of the logic units 20 and 22 is selected by the selection unit SEL, and the selected signal becomes the output signal S22. For this reason, even when the number of pulses of noise superimposed on the input signal S20 is large or when the pulse width is large, the noise superimposed on both voltage levels of the signal is further reduced. Further, since the delay units DL10_1 to DL10_N of the delay unit 24 used by the logical product unit 20 and the logical sum unit 22 are shared, noise superimposed on both voltage levels of the signal is reduced after the circuit scale is reduced. It can be reduced efficiently.

2.2. Comparative Example of First and Second Configuration Examples Next, a comparative example studied for creating first and second configuration examples of the noise reduction circuit of the present embodiment will be described with reference to the drawings. Here, in order to facilitate the explanation of the examination results with each comparative example, first, an example in the case of N = 2 in the second configuration example of the noise reduction circuit of this embodiment is shown in FIG.

  As shown in FIG. 4, the noise reduction circuit according to an embodiment of the second configuration example includes two AND circuits AND10_1 and AND10_2, two OR circuits OR10_1 and OR10_2 in cascade connection with the logical product unit 20a and the logical sum unit 22a. Thus, the logical units 20a and 22a share the delay unit 24a including the two delay circuits DL10_1 and DL10_2. The tap Tp1 between the two delay circuits DL10_1 and DL10_2 is connected to the input terminal of the AND circuit AND10_1 of the AND unit 20a and the OR circuit OR10_1 of the OR unit 22a.

  Next, the logical unit 10a of the comparative example 1 shown in FIG. 5 has a configuration in which the delay circuit DL10 and the AND circuit AND10 of the logical product unit 10 in the first configuration example shown in FIG. ing. In the logical unit 10a of the comparative example 1, although the number of pulses of the low-voltage side noise NZL10 is decreased as shown by A1 in FIG. 5, the number of pulses of the high-voltage side noise NZH10 is increased as shown by A2. The signal S10a is output. In other words, it can be seen that the logic unit 10a including the AND circuit AND10 and the delay circuit DL10 has characteristics excellent in reducing the low-voltage side noise NZL10.

  The logic unit 10b of the comparative example 2 shown in FIG. 6 has a configuration in which one delay circuit DL10 and one OR circuit OR10 of the OR unit 12 in the first configuration example shown in FIG. In the logic unit 10b of the comparative example 2, although the number of pulses of the high voltage side noise NZH10 is decreased as shown by A4 in FIG. 4, the number of pulses of the low voltage side noise NZL10 is increased as shown by A3. The signal S10b is output. In other words, it can be seen that the logic unit 10b including the OR circuit OR10 and the delay circuit DL10 has characteristics excellent in reducing the high-voltage side noise NZH10.

  The logic unit 10c of the third comparative example shown in FIG. 7 is different from the noise reduction circuit of the first configuration example shown in FIG. 1 in that the delay unit 10c3 is one delay circuit DL10, the AND unit 10c1 is an AND circuit AND10, and The OR unit 10c2 is an OR circuit OR10. Then, two logic units 10c1, 10c2 having opposite noise reduction characteristics according to the voltage level of the input signal S10 share the delay circuit DL10 of the delay unit 10c3 in parallel, and the voltage level of the output signal S12 of the selection unit SEL. Based on the above, the selection unit SEL selects and outputs one of the output signals ANDS10 and ORS10.

  In this comparative example 3, in the OR unit 10c2 having the characteristics excellent in reducing the high-voltage side noise NZH10, the OR of the input signal S10 and the signal DLS10 obtained by delaying the input signal S10 by the delay circuit DL10 is ORed. Taken in circuit OR10. The OR circuit OR10 calculates the number of pulses of the high-voltage side noise NZH10 as shown by A5 in FIG. 8, while the number of pulses of the low-voltage side noise NZL10 as shown by A6 in FIG. Increase. Thus, in the OR unit 10c2, the input signal S10 is output as the signal ORS10 in which the number of pulses of the high-voltage side noise NZH10 is reduced.

  On the other hand, in the logical product unit 10c1 having excellent characteristics for reducing the low-voltage side noise NZL10, an AND circuit AND10 takes the logical product of the input signal S10 and the signal DLS10 obtained by delaying the input signal S10 by the delay circuit DL10. It is done. By ANDing the AND circuit AND10, the number of pulses of the low voltage side noise NZL10 is reduced as shown in A7 of FIG. 8, while the number of pulses of the high voltage side noise NZH10 is reduced as shown in A8 of FIG. Increase. Thus, in the logical product unit 10c1, the input signal S10 is output as the signal ANDS10 in which the number of pulses of the low voltage side noise NZL10 is reduced.

  Thereafter, in the selection unit SEL, based on the voltage level of the output signal S12 of the selection unit SEL, either the signal ANDS10 output from the logical product unit 10c1 or the signal ORS10 output from the logical sum unit 10c2 is selected. Select and output. Therefore, the output signal S12 of the selection unit SEL is a signal S12 in which the high-voltage side noise NZH10 and the low-voltage side noise NZL10 are reduced, as shown by A9 and A10 in FIG. In this way, the logic unit 10c of the comparative example 3 reduces the high voltage side noise NZH10 and the low voltage side noise NZL10 superimposed on the input signal S10.

  However, as shown in FIG. 9, when the number of noise pulses of the input signal S10 is large, the output signal ORS10 from the OR unit 10c2 increases the number of pulses of the low-voltage side noise NZL10 as indicated by A11. On the other hand, as indicated by A12, although the number of pulses of the high voltage side noise NZH10 decreases, the high voltage side noise NZH10 remains. On the other hand, the output signal ANDS10 from the logical product unit 10c1 increases the number of pulses of the high voltage side noise NZH10 as indicated by A13, while the number of pulses of the low voltage side noise NZL10 decreases as indicated by A14. The low voltage side noise NZL10 remains. For this reason, the output signal S12 of the logic unit 10c includes residual noise as indicated by A15 and A16, and noise removal is insufficient.

  In order to study the circuit configuration of a noise reduction circuit that sufficiently performs noise reduction even when the number of noise pulses superimposed on the input signal S10 is large, the logic unit 10d of Comparative Example 4 shown in FIG. The two logical units 10a of the first comparative example shown in FIG. With such a configuration, even when noise pulses included in the input signal S10 are included in succession, first, as shown in A21, the number of pulses of the low-voltage side noise NZL10 is reduced, as shown in A22. In addition, a signal S10a1 in which the number of pulses of the high-voltage side noise NZH10 is increased is output from the preceding logic unit 10a1. Then, this signal S10a1 is inputted to the logic unit 10a2 on the rear stage side. Then, as shown in A23, the number of pulses of the low voltage side noise NZL10 remaining in the signal S10a1 is further reduced, and as shown in A24, the number of pulses of the high voltage side noise NZH10 is further increased and outputted. . In other words, the logic unit 10d of the comparative example 4 further improves the excellent characteristic of the low voltage side noise NZL10 reduction of the logic unit 10a of the comparative example 1.

  On the other hand, the logical unit 10e of the comparative example 5 shown in FIG. 11 has a configuration in which two logical units 10b of the comparative example 2 shown in FIG. 6 are cascade-connected. By adopting such a configuration, even when noise pulses included in the input signal S10 are included in succession, the number of pulses of the high-voltage side noise NZH10 is reduced as shown in A25 of FIG. As described above, the signal S10b1 in which the number of pulses of the low-voltage side noise NZL10 is increased is output from the preceding logic unit 10b1. When this signal S10b1 is input to the subsequent logic unit 10b2, the number of pulses of the high-voltage noise NZH10 remaining in the signal S10b1 is further reduced as indicated by A27, and as indicated by A28. The number of pulses of the low voltage side noise NZL10 is further increased and output. In other words, the logical unit 10e of the comparative example 5 further improves the excellent characteristic of the reduction of the high-voltage side noise NZH10 of the logical unit 10b of the comparative example 2.

  Therefore, the logical unit 10f of the comparative example 6 shown in FIG. 12 is based on the examination results of the comparative examples 4 and 5, in order to increase the noise reduction amount of both voltage levels in the logical unit 10c of the comparative example 3. The product unit 10f1 has a configuration in which a logic unit 10f3 similar to that of the first comparative example is connected to the rear stage side of the AND circuit AND10f1. Then, the logical unit 10f2 is configured to be connected to the logical unit 10f4 similar to the comparative example 2 on the rear stage side of the OR circuit OR10f1.

  With this configuration, when the signal S10 on which noise is superimposed is input, first, in the AND unit 10f1, the number of pulses of the high-voltage side noise NZH10 is reduced as indicated by A31 in FIG. As shown in A32, a signal ANDS10f1 in which the number of pulses of the low-voltage side noise NZL10 is increased is output from the preceding AND circuit AND10f1. When this signal ANDS10f1 is input to the AND circuit AND10f2 on the subsequent stage side, the number of pulses of the low-voltage side noise NZL10 remaining in the signal ANDS10f1 is further reduced as indicated by A33, and as indicated by A34. The number of pulses of the high-voltage noise NZH10 is further increased and output.

  On the other hand, in the OR unit 10f2, first, as shown in A35 of FIG. 13, the number of pulses of the high voltage side noise NZH10 is decreased, and as shown in A36, the number of pulses of the low voltage side noise NZL10 is increased. The ORS 10f1 is output from the preceding OR circuit OR10f1. When this signal ORS10f1 is input to the subsequent OR circuit OR10f2, the number of pulses of the high-voltage side noise NZH10 remaining in the signal ORS10f1 is further reduced as indicated by A37, and as indicated by A38. The number of pulses of the low voltage side noise NZL10 is further increased and output.

  Thereafter, in the selection unit SEL, based on the voltage level of the output signal S12 of the selection unit SEL, either the signal ANDS10f2 output from the logical product unit 10f1 or the signal ORS10f2 output from the logical sum unit 10f2 is selected. Select and output. Therefore, the output signal S12 of the selection unit SEL is a signal in which the high-voltage side noise NZH10 and the low-voltage side noise NZL10 are reduced, as indicated by A39 and A40 in FIG.

  In this way, even when the number of noise pulses superimposed on the input signal S10 is large, the logic unit 10f of the comparative example 6 increases the amount of noise reduction at both voltage levels and then outputs the output signal at the selection unit SEL. By selecting and outputting, the high voltage side noise NZH10 and the low voltage side noise NZL10 are efficiently reduced. Accordingly, in the logical product unit 10f1 and the logical sum unit 10f2, noise at both voltage levels is further reduced by increasing the number of logical units 10f3 and 10f4 connected to the subsequent stage of the AND circuit AND10f1 and the OR circuit OR10f1, respectively. I guess it can be done. However, since the logical product unit 10f1 and the logical sum unit 10f2 are provided with the delay circuits DL10f1 and DL10f2, respectively, the circuit scale of the logical unit 10f becomes large.

  Therefore, in one embodiment of the second configuration example described above, as shown in FIG. 4, delay circuits DL10f1 and DL10f2 provided in each of the logical product unit 10f1 and the logical sum unit 10f2 of the comparative example 6 are provided as one unit. As a configuration shared by the delay circuit DL10_2, the circuit scale is reduced. Thus, it was found that the operation result shown in FIG. 13 was obtained in the same manner as in Comparative Example 6 after reducing the circuit scale.

  Based on the examination results of the comparative examples 1 to 6, the noise reduction circuit of the second configuration example of the present embodiment has two logic units 20 and 22 whose noise reduction characteristics conflict with each other according to the voltage level of the signal. Are configured so as to share a delay unit 14 in which a plurality of delay circuits DL10_1 to DL10_N are cascade-connected. Then, the output signals ANDS20 and ORS20 of these logic units 20 and 22 are input to the selection unit SEL, and the selection unit SEL is one of the logic units 20 and 22 based on the voltage level of the output signal S22 of the selection unit SEL. The output signals ANDS20 and ORS20 are selected and output. At that time, taps Tp1 to Tp (N-1) between the delay circuits DL10_1 to DL10_N of the delay unit 24 are connected to the input terminals of the AND circuits AND10_1 to AND10_N and the input terminals of the OR circuits OR10_1 to OR10_N, respectively. The configuration.

  For this reason, it is possible to increase the amount of noise reduction superimposed on both voltage levels of the signal while suppressing an increase in circuit scale. Further, in the logical product unit 20 and the logical sum unit 22, the noise can be reduced in accordance with various noise generation patterns such as the magnitude and number of noise pulses superimposed on the input signal S10 and the generation interval. Become. As described above, since the second configuration example is logically equivalent to the first configuration example, the same operations and effects can be obtained.

3.1. Third Configuration Example FIG. 14 shows a third configuration example of the noise reduction circuit of this embodiment. In the noise reduction circuit of this embodiment, in order to reduce noise at both voltage levels more surely, a plurality (M pieces) of negative logic circuits NAND and NOR that conflict with the logical product unit 30 and the logical sum unit 32 respectively. : M is an integer).

  As shown in FIG. 14, the logical product unit 30 includes M logical NAND circuits NAND30_1 to NAND30_M and M logical NOR circuits NOR30_1 to NOR30_M which are the first logical product NAND circuit NAND30_1 from the input stage. Are arranged in cascade with each other so that the arrangement of

  On the other hand, in the OR unit 32, the M OR gate circuits NOR32_1 to NOR32_M and the M OR gate circuits NAND32_1 to NAND32_M are arranged as the first OR gate NOR32_1 from the input stage. It is configured to be cascaded alternately.

  The delay unit 34 is configured by cascading 2M delay circuits DL10_1 to DL10_2M via inverter circuits INV30_1 to INV30_ (2M−1), respectively. That is, the output signals DLS10_1 to DLS10_ (2M-1) of the delay circuits DL10_1 to DL10_ (2M-1) are inverted by the inverter circuits INV30_1 to INV30_ (2M-1), respectively, and then sent to the subsequent delay circuits DL10_2 to DL10_2M. Entered. Further, taps Tp1 to Tp (2M-1) between the delay circuits DL10_1 to DL10_2M of the delay unit 34 are connected to the logical product unit 30 with the logical product NAND circuits NAND30_1 to NAND30_M or the logical product NORs. The circuits NOR30_1 to NOR30_M are respectively connected. These taps Tp1 to Tp (2M-1) are connected to the logical sum unit 32 also to the input terminals of the logical sum NOR circuits NOR32_1 to NOR32_M or the logical sum NAND circuits NAND32_1 to NAND32_M, respectively. The

  Specifically, the odd-numbered taps Tp1 to Tp (2M−1) from the input stage include the logical product NAND circuits NAND30_1 to NAND30_M of the logical product unit 30 and the logical sum NOR circuits NOR32_1 of the logical sum unit 32. To the input terminal of NOR32_M. On the other hand, even-numbered taps Tp <b> 2 to Tp (2M−2) from the input stage are input to the logical product NOR circuits NOR <b> 30 </ b> _ <b> 1 to NOR <b> 30 </ b> _M of the logical product unit 30 and the logical sum NAND circuits NAND <b> 32 </ b> 1 to NAND <b> 32 </ Connected to the terminal.

  With this configuration, in the logical product unit 30, the first NAND circuit NAND30_1 from the input stage negates the input signal S30 and the output signal DLS10_1 from the first delay circuit DL10_1 from the input stage. Logical AND. Then, the jth (2 ≦ j ≦ M) AND NAND circuit NAND30_j (for example, NAND30_2) from the input stage is j−1th NOR circuit NOR30_ (j−1) (for example, NAND) from the input stage (for example, NOR30_1) output signal NORS30_ (j-1) (for example, NORS30_1) and output signal DLS10_ (2j-1) (for example, DL10_3) from the 2j-1st delay circuit DL10_ (2j-1) (for example, DL10_3) from the input stage. , DLS10_3) and NANDed. On the other hand, the k-th (1 ≦ k ≦ M) logical product NOR circuit NOR30_k (for example, NOR30_1) from the input stage is an output signal NANDS30_k (for example, NAND30_1) of the kth logical product NAND circuit NAND30_k (for example, NAND30_1). For example, the NAND of the NANDS 30_1) and the output signal DLS10_2k (for example, DLS10_2) from the 2k-th delay circuit DL10_2k (for example, DL10_2) from the input stage is calculated.

  On the other hand, in the logical sum unit 32, the first logical sum NOR circuit NOR32_1 from the input stage performs a negative logical sum of the input signal S30 and the output signal DLS10_1 from the first delay circuit DL10_1 from the input stage. The j-th (2 ≦ j ≦ M) OR circuit NOR32_j (for example, NOR32_2) from the input stage is the j−1th NAND circuit NAND32_ (j−1) (for example, the input stage). The NAND signal of the output signal NANDS32_ (j-1) (for example, NANDS32_1) of the NAND32_1) and the output signal DLS10_ (2j-1) from the 2j-1st delay circuit DL10_ (2j-1) from the input stage is obtained. . On the other hand, the k-th (1 ≦ k ≦ M) NAND circuit NAND32_k (for example, NAND32_1) from the input stage has an output signal NANDS32_k of the k-th NOR circuit NAND32_k from the input stage and the 2kth from the input stage. Of the output signal from the delay circuit DL10_2k.

  As described above, in this configuration example, the logical unit 30 and the logical unit 32 are cascade-connected so that a plurality (M) of negative logic circuits NAND and NOR that are opposite to each other are alternately arranged. The two logic units 30 and 32 having opposite noise reduction characteristics according to the voltage level of the input signal S30 share a delay unit 34 having a configuration in which 2M delay circuits DL10_1 to DL10_2M are cascade-connected in parallel. The selection unit SEL selects and outputs one of the output signals of the logic units 30 and 32.

  With such a configuration, even when the number of noise pulses superimposed on the input signal S30 is large or the pulse width is large, the low voltage side noise is reduced by the logical product unit 30 and the logical sum unit 32 increases the noise. After the voltage side noise is more reliably reduced, the output signal of each of the logic units 30 and 32 is selected by the selection unit SEL. For this reason, even when the number of noise pulses superimposed on the input signal S30 is large or the pulse width is large, the signal S32 in which the noise superimposed on both voltage levels of the signal is further reduced is output.

  In addition, the delay circuits DL10_1 to DL10_2M of the delay unit 34 used by the logical product unit 30 and the logical sum unit 32 are shared. For this reason, it is possible to efficiently reduce noise superimposed on both voltage levels of the signal while reducing the circuit scale.

  Further, since the logical product unit 30 and the logical sum unit 32 are configured by cascading negative logic circuits NAND and NOR that are opposite to each other in a staggered manner, the characteristics of the logical product unit 30 and the logical sum unit 32 are almost the same. Can be. For this reason, it is possible to more reliably reduce noise on both voltage levels included in the input signal S30.

  Further, as described above, the delay unit 34 has a configuration in which the delay circuits DL10_1 to DL10_2M are cascade-connected via the inverter circuits INV30_1 to INV30_ (2M-1). With such a configuration, the delay due to the inverter circuits INV30_1 to INV30_ (2M-1) is added to the output signals DLS10_1 to DL10_ (2M-1) of the delay circuits DL10_1 to DL10_ (2M-1). Noise with a larger pulse width can be reduced.

3.2. Comparative Example of Third Configuration Example Next, a comparative example studied for creating a third configuration example of the noise reduction circuit of the present embodiment will be described with reference to the drawings. The logic unit 30a of Comparative Example 7 shown in FIG. 15 has a configuration in which one NAND circuit NAND30 and one delay circuit DL30 included in each logic unit of the third configuration example shown in FIG. 14 are provided. In the logic unit 30a of the comparative example 8, the low voltage side noise NZL30 has the number of pulses decreased and the low voltage side level is inverted to the high voltage side level as indicated by C1 in FIG. On the other hand, in the high-voltage side noise NZH30, as indicated by C2, the number of pulses increases and the high voltage side level is inverted to the low voltage side level. In this way, when the signal S30 including noise is input, the logic unit 30a outputs the signal S30a including the low voltage side noise NZL30 having an increased number of pulses.

  On the other hand, the logical unit 30b of the comparative example 8 shown in FIG. 16 is provided with one NOR circuit NOR30 and one delay circuit DL30 included in each logical unit of the third structural example shown in FIG. It has become. In the logic unit 30b of the comparative example 8, the number of pulses of the high voltage side noise NZH30 is decreased and the high voltage side level is inverted to the low voltage side level as indicated by C3 in FIG. On the other hand, in the low-voltage side noise NZL30, as indicated by C4, the number of pulses increases and the low-voltage side level is inverted to the high-voltage side level. In this way, when the signal S30 including noise is input, the logic unit 30b outputs the signal S30b including the high-voltage noise NZH30 having an increased number of pulses.

  In Comparative Example 9 shown in FIG. 17, the logical unit 30c is configured to cascade the logical unit 30a of Comparative Example 7 shown in FIG. 15 and the logical unit 30b of Comparative Example 8 shown in FIG. In the logic unit 30c, first, when an input signal S30 including the high voltage side noise NZH30 and the low voltage side noise NZL30 is input to the logic unit 30a, the NAND circuit NAND30a outputs the input signal S30 and the output signal of the delay circuit DL30a. NANDed with DLS 30a. In this way, by taking a negative logical product in the NAND circuit NAND30a, the low voltage side noise NZL30 is reduced in the number of pulses and inverted from the low voltage side level to the high voltage side level, as indicated by C5 in FIG. The On the other hand, as shown in C6 of FIG. 17, the high-voltage side noise NZH30 increases in the number of pulses, the high-voltage side level is inverted to the low-voltage side level, and becomes the low-voltage-side noise NZL30.

  Thereafter, the signal S30a output from the NAND circuit NAND30a is input to the NOR circuit NOR30b of the subsequent logic unit 30b. In the NOR circuit NOR30b, by taking a negative OR of the input signal S30a and the output signal DLS30b of the delay circuit DL30b, the low voltage side noise NZL30 has an increased number of pulses as shown by C7 in FIG. The low voltage side level is inverted to the high voltage side level. On the other hand, the high voltage side level from which noise has already been removed is inverted to become the low voltage side level as indicated by C8 in FIG. In this way, the signal S30c including the high-voltage side noise NZH30 having an increased number of pulses is output from the NOR circuit NOR30b. That is, the logic unit 30c functions as an AND unit that reduces the low-voltage side noise NZL30 while increasing the high-voltage side noise NZH30.

  On the other hand, in the comparative example 10 shown in FIG. 18, the logical unit 30d has a configuration in which the logical unit 30b of the comparative example 8 shown in FIG. 16 and the logical unit 30a of the comparative example 7 shown in FIG. Yes. In this logic unit 30d, in the preceding logic unit 30b, the high-voltage noise NZH30 of the input signal S30 is reduced in the number of pulses and the high-voltage side level becomes the low-voltage side level, as indicated by C9 in FIG. Is inverted. On the other hand, the low voltage side noise NZL30, as indicated by C10 in FIG. 18, the number of pulses increases, the low voltage side level is inverted to the high voltage side level, and becomes the high voltage side noise NZH30. In this way, when the signal S30 including noise is input, the logic unit 30b outputs the signal S30b including the high voltage side noise NZH30 having an increased number of pulses.

  Thereafter, the output signal S30b from the NOR circuit NOR30b is input to the subsequent NAND circuit NAND30a. In the NAND circuit NAND30a, a negative logical product of the input signal S30b and the output signal DLS30a of the delay circuit DL30a is obtained. By taking the negative logical product in this way, as shown in C11 of FIG. 18, the high voltage side noise NZH30 is increased in the number of pulses, and the high voltage side level is inverted to the low voltage side level. The noise becomes NZL30. On the other hand, the low voltage side level from which noise has already been removed is inverted and becomes the high voltage side level as indicated by C12 in FIG. In this way, in the logic unit 30d, the signal S30d including the low-voltage side noise NZL30 having an increased number of pulses is output from the NAND circuit NAND30a. That is, the logic unit 30d functions as an OR unit that reduces the high-voltage side noise NZH30 while increasing the low-voltage side noise NZL30.

  Based on the examination results of Comparative Examples 7 to 10 described above, in the third configuration example of the present embodiment shown in FIG. 14, in order to reduce noise at both voltage levels more reliably, A plurality of (M) negative logic circuits NAND and NOR that are opposite to each other in the sum unit 32 are cascade-connected. Then, two logic units 30 and 32 having opposite noise reduction characteristics according to the voltage level of the input signal S30 share a delay unit 34 having a configuration in which 2M delay circuits DL10_2M are cascade-connected in parallel and are selected. The unit SEL is configured to select and output one of the output signals of the logic units 30 and 32. For this reason, in the noise reduction circuit of the third configuration example, noise at both voltage levels can be reduced more reliably.

4). Configuration example of selection unit 4.1. First Configuration Example FIG. 19A shows a first configuration example of the selection unit SEL provided in the noise reduction circuit of this embodiment. In the selection unit SEL of this configuration example, the input stage side has the first and second AND circuits AND15 and AND16, and the output stage side has one input of the selection OR circuit OR15 and the first AND circuit AND15. An inverter INV15 is provided on each input stage side of the terminal.

  In the first AND circuit AND15, the first output signal A (ANDS10, ANDS21, NORS31) which is the output signal of the AND unit 10 (20, 30) is input to one input terminal, and the other input terminal selects the first output signal A A signal INVS15 obtained by inverting the output signal of the OR circuit OR15 by the inverter INV15 is input. The first AND circuit AND15 takes the logical product of these signals A and INVS15, and the output signal ANDS15 is input to one input terminal of the selection OR circuit OR15. In the second AND circuit AND16, the second output signal B (ORS10, ORS21, NANDS31), which is the output signal of the logical sum unit 12 (22, 32), is input to one input terminal, and the other input terminal is selected. The output signal ORS15 of the OR circuit OR15 is input, and the logical product of these signals B and ORS15 is obtained. The logical product output signal ANDS16 taken by the second AND circuit AND16 is input to the other input terminal of the selection OR circuit OR15. The selection OR circuit OR15 calculates the logical sum of the output signal ANDS15 of the first AND circuit AND15 and the output signal ANDS16 of the second AND circuit AND16. In this configuration example, the output signal ORS15 of the selection OR circuit OR15 is output as the output signal S12 (22, 32) of the selection unit SEL.

  FIG. 19B shows a truth table of each signal output from each component of the selection unit SEL of this configuration example. Note that X1 in the truth table of FIG. 19B indicates the voltage level before the change of the output signal S12 (22, 32) of the selection unit SEL, and X2 is the output signal S12 (22, 32) of the selection unit SEL. ) Shows the voltage level after the change.

  As shown in FIG. 19B, when the voltage level X1 before the change of the output signal 12 (22, 32) of the selection unit SEL is the low voltage side level (0), the output signal from the logical product unit indicated by D1. The voltage level of A coincides with the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL indicated by D2. From this, it is understood that the output signal A of the logical product unit 10 (20, 30) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  On the other hand, when the voltage level X1 after the change of the output signal 12 (22, 32) of the selection unit SEL is the high voltage side level (1), the voltage level of the output signal B from the OR unit indicated by D3 is , D4 coincides with the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL. From this, it can be seen that the output signal B of the logical sum unit 12 (22, 32) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  As described above, the selection unit SEL is configured as shown in FIG. 19A, so that when the output signal S12 (22, 32) of the selection unit SEL is at the low voltage side level, the low voltage side noise is reduced. The output signal from the logical product unit 10 (20, 30) having excellent characteristics is selected and output. When the output signal S12 (22, 32) of the selection unit SEL is at the high voltage side level, the output signal from the logical sum unit 12 (22, 32) having characteristics excellent in reducing the high voltage side noise is selected. And output. For this reason, the output signal S12 (22, 32) of the noise reduction circuit output via the selection unit SEL of this configuration example is output as a signal in which noise superimposed on both voltage levels is reduced. .

4.2. Second Configuration Example FIG. 20A shows a second configuration example of the selection unit SEL provided in the noise reduction circuit of this embodiment. The selection unit SEL of this configuration example has the first and second AND circuits AND25 and AND26 on the input stage side, the selection NOR circuit NOR25 on the output stage side, and the output stage side of the selection NOR circuit NOR25. Are each provided with an inverter INV25.

  In the first AND circuit AND25, the first output signal A (ANDS10, ANDS21, NORS31), which is the output signal of the AND unit 10 (20, 30), is input to one input terminal, and the other input terminal is selected. An output signal NORS25 of the NOR circuit NOR25 is input. The first AND circuit AND25 calculates the logical product of these signals A and NORS25, and the output signal ANDS25 is input to one input terminal of the selection NOR circuit NOR25. In the second AND circuit AND26, the second output signal B (ORS10, ORS21, NANDS31), which is the output signal of the logical sum unit 12 (22, 32), is input to one input terminal, and the other input terminal is selected. A signal INVS25 obtained by inverting the output signal NORS25 of the NOR circuit NOR25 by the inverter INV25 is input. Then, the logical product of these signals B and INVS25 is obtained, and the output signal ANDS26 is input to the other input terminal of the selection NOR circuit NOR25. The selection NOR circuit NOR25 takes a negative OR of the output signal ANDS25 of the first AND circuit AND25 and the output signal ANDS26 of the second AND circuit AND26. In this configuration example, the inverted signal INVS25 of the output signal NORS25 of the selection NOR circuit NOR25 is output as the output signal S12 (22, 32) of the selection unit SEL.

  FIG. 20B shows a truth table of each signal output from each component of the selection unit SEL of this configuration example. As shown in FIG. 20B, when the voltage level X1 before the change of the output signal 12 (22, 32) of the selection unit SEL is the low voltage side level (0), the output from the logical product unit indicated by E1. The voltage level of the signal A coincides with the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL indicated by E2. From this, it is understood that the output signal A of the logical product unit 10 (20, 30) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  On the other hand, when the voltage level X1 after the change of the output signal 12 (22, 32) of the selection unit SEL is the high voltage side level (1), the voltage level of the output signal B from the OR unit indicated by E3. Coincides with the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL indicated by E4. From this, it can be seen that the output signal B of the logical sum unit 12 (22, 32) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  As described above, the selection unit SEL is configured as shown in FIG. 20A, so that when the output signal S12 (22, 32) of the selection unit SEL is at the low voltage side level, the low voltage side noise is reduced. The output signal from the logical product unit 10 (20, 30) having excellent characteristics is selected and output. When the output signal S12 (22, 32) of the selection unit SEL is at the high voltage side level, the output signal from the logical sum unit 12 (22, 32) having characteristics excellent in reducing the high voltage side noise is selected. And output. For this reason, the output signal S12 (22, 32) of the noise reduction circuit output via the selection unit SEL of this configuration example is output as a signal in which noise superimposed on both voltage levels is reduced. .

4.3. Third Configuration Example FIG. 21A shows a third configuration example of the selection unit SEL provided in the noise reduction circuit of this embodiment. The selection unit SEL of this configuration example has one input terminal of the first and second OR circuits OR35 and OR36 on the input stage side, and one of the input terminals of the selection AND circuit AND35 and OR circuits OR35 and OR36 on the output stage side. Inverters INV35 and INV36 are provided on the input stage side, and an inverter INV37 is provided on the output stage side of the selection AND circuit AND35.

  The first OR circuit OR35 has a signal INVS35 obtained by inverting the first output signal A (ANDS10, ANDS21, NORS31), which is an output signal of the logical product unit 10 (20, 30), at one input terminal by the inverter INV35. The signal INVS37 obtained by inverting the output signal ANDS35 of the selection AND circuit AND35 by the inverter INV37 is input to the other input terminal. The first OR circuit OR35 takes a logical sum of these signals INVS35 and INVS37, and the output signal ORS35 is input to one input terminal of the selection AND circuit AND35. The second OR circuit OR36 has, at one input terminal, a signal INVS36 obtained by inverting the second output signal B (ORS10, ORS21, NANDS31), which is an output signal of the OR unit 12 (22, 32), by the inverter INV36. The output signal ANDS35 of the selection AND circuit AND35 is input to the other input terminal. Then, the logical sum of these signals INVS36 and ANDS35 is calculated, and the output signal ORS36 is input to the other input terminal of the selection AND circuit AND35. The selection AND circuit AND35 takes a logical product of the output signal ORS35 of the first OR circuit OR35 and the output signal ORS36 of the second OR circuit OR36. In this configuration example, the inverted signal INVS37 of the output signal ANDS35 of the selection AND circuit AND35 is output as the output signal S12 (22, 32) of the selection unit SEL.

  FIG. 21B shows a truth table of each signal output from each component of the selection unit SEL of this configuration example. As shown in FIG. 21B, when the voltage level X1 before the change of the output signal 12 (22, 32) of the selection unit SEL is the low voltage side level (0), the output signal from the AND unit indicated by F1. The voltage level of A matches the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL indicated by F2. From this, it is understood that the output signal A of the logical product unit 10 (20, 30) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  On the other hand, when the voltage level X1 after the change of the output signal 12 (22, 32) of the selection unit SEL is the high voltage side level (1), the voltage level of the output signal B from the OR unit indicated by F3 is , F4 matches the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL. From this, it can be seen that the output signal B of the logical sum unit 12 (22, 32) is selected and output as the output signal S12 (22, 32) of the selection unit SEL.

  As described above, the selection unit SEL is configured as shown in FIG. 21A, so that when the output signal S12 (22, 32) of the selection unit SEL is at the low voltage side level, the low voltage side noise is reduced. The output signal from the logical product unit 10 (20, 30) having excellent characteristics is selected and output. When the output signal S12 (22, 32) of the selection unit SEL is at the high voltage side level, the output signal from the logical sum unit 12 (22, 32) having characteristics excellent in reducing the high voltage side noise is selected. And output. For this reason, the output signal S12 (22, 32) of the noise reduction circuit output via the selection unit SEL of this configuration example is output as a signal in which noise superimposed on both voltage levels is reduced. .

4.4. Fourth Configuration Example FIG. 22A shows a fourth configuration example of the selection unit SEL provided in the noise reduction circuit of this embodiment. The selection unit SEL of this configuration example has first and second OR circuits OR45 and OR46 on the input stage side, and a selection NAND circuit NAND45 and first and second OR circuits OR45 and OR46 on the output stage side. The inverters INV45 and INV46 are provided on the input stage side of one input terminal, and the inverter INV47 is provided on the input stage side of the other input terminal of the second OR circuit OR46.

  The first OR circuit OR45 has a signal INVS45 obtained by inverting the first output signal A (ANDS10, ANDS21, NORS31), which is an output signal of the AND unit 10 (20, 30), at one input terminal by the inverter INV45. The output signal NANDS45 of the selection NAND circuit NAND45 is input to the other input terminal. The first OR circuit OR45 takes the logical sum of these signals INVS45 and NANDS45, and the output signal ORS45 is input to one input terminal of the selection NAND circuit NAND45. The second OR circuit OR46 has a signal INVS46 obtained by inverting the second output signal B (ORS10, ORS21, NANDS31), which is an output signal of the logical sum unit 12 (22, 32), at one input terminal by the inverter INV46. The signal INVS47 obtained by inverting the output signal NANDS45 of the selection NAND circuit NAND45 by the inverter INV47 is input to the other input terminal. Then, the logical sum of these signals INVS 46 and INVS 47 is taken, and the output signal ORS 46 is input to the other input terminal of the selection NAND circuit NAND 45. The selection NAND circuit NAND45 takes a negative logical product of the output signal ORS45 of the first OR circuit OR45 and the output signal ORS46 of the second OR circuit OR46. In this configuration example, the output signal NANDS45 of the selection NAND circuit NAND45 is output as the output signal S12 (22, 32) of the selection unit SEL.

  FIG. 22B shows a truth table of each signal output from each component of the selection unit SEL of this configuration example. As shown in FIG. 22B, when the voltage level X1 before the change of the output signal 12 (22, 32) of the selection unit SEL is the low voltage side level (0), the output signal from the AND unit indicated by G1. The voltage level of A matches the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL indicated by G2. From this, it is understood that the output signal A of the logical product unit 10 (20, 30) is output as the output signal S12 (22, 32) of the selection unit SEL.

  On the other hand, when the voltage level X1 after the change of the output signal 12 (22, 32) of the selection unit SEL is the high voltage side level (1), the voltage level of the output signal B from the OR unit indicated by G3 is , G4 coincides with the voltage level X2 of the output signal S12 (22, 32) of the selection unit SEL. From this, it can be seen that the output signal B of the logical sum unit 12 (22, 32) is output as the output signal S12 (22, 32) of the selection unit SEL.

  As described above, the selection unit SEL is configured as shown in FIG. 22A, so that when the output signal S12 (22, 32) of the selection unit SEL is at the low voltage side level, the low voltage side noise is reduced. The output signal from the logical product unit 10 (20, 30) having excellent characteristics is selected and output. When the output signal S12 (22, 32) of the selection unit SEL is at the high voltage side level, the output signal from the logical sum unit 12 (22, 32) having characteristics excellent in reducing the high voltage side noise is selected. And output. For this reason, the output signal S12 (22, 32) of the noise reduction circuit output via the selection unit SEL of this configuration example is output as a signal in which noise superimposed on both voltage levels is reduced. .

5). FIG. 23 illustrates an example of a performance evaluation apparatus that performs performance evaluation of each configuration example of the noise reduction circuit described in the above embodiment. When evaluating the performance of each configuration example of the noise reduction circuit of this embodiment, a performance evaluation apparatus 70 shown in FIG. 23 was used.

  As shown in FIG. 23, the performance evaluation apparatus 70 includes a clock generator 80, a signal edge counter 82, a noise generator 90, a noise edge counter 92, an exclusive OR circuit XOR, and an output edge counter 72. In the performance evaluation apparatus 70, first, an exclusive OR circuit XOR takes the exclusive OR of the clock signal output from the clock generator 80 in a predetermined cycle and the pseudo noise randomly output from the noise generator 90. Then, the output signal of the exclusive OR circuit XOR is input to the noise reduction (NR) circuit 114 of this embodiment, and the rising or falling edge of the output signal of the NR circuit 114 is detected. The output edge counter 72 counts.

When the performance evaluation device 70 evaluates the performance of the noise reduction circuit of the present embodiment, the noise generator 90 generates the following expression (1) indicating the range of the signal width Sig that becomes the pseudo-noise generation interval shown below. The pseudo noise is generated based on the random number calculated by the equation (2) indicating the range of the pulse width Ns of the pseudo noise. Note that P_ResStep indicates the resolution of pseudo noise generation.
P_ResStep × PN15 {1 to (2 ^{(SNex + 7)} −1)} (1)
P_ResStep × PN7 {1- (2 ⁷ -1)} (2)

Note that SNex in the above equation (1) represents a numerical value in which S / N is expressed by a power of 2, as shown in the following equation (3).
S / N = Sig / Ns = 2 ^SNex (3)

  Further, the number of rising or falling edges of the clock signal output from the clock generator 80 within a predetermined time is counted by the signal edge counter 82, and the predetermined pseudo noise output from the noise generator 90 is determined. The number of rising or falling edges in the time is counted by the noise edge counter 92. Here, the predetermined time indicates a time sufficient for calculating the error rate.

When random pseudo noise is input to the NR circuit 114 of the present embodiment by the performance evaluation device 70, the number of edges of either the rising edge or falling edge of the output signal of the NR circuit 114 counted by the output edge counter 72 The error rate is calculated by the following equation (4) based on the count value of the signal edge, the count value of the signal edge counter 82, and the count value of the noise edge counter 92. Then, the noise reduction performance of the NR circuit 114 is evaluated using the calculated error rate as an index. In the following equation (4), ER represents the error rate, S_EdCnt represents the count value of the output edge counter 72, IS_EdCnt represents the count value of the signal edge counter 82, and NS_EdCnt represents the count value of the noise edge counter 92.
ER = (S_EdCnt−IS_EdCnt) / NS_EdCnt (4)

The error rate evaluation was performed by changing P_ResStep or S / N. P_ResStep is a numerical value that determines the maximum width of pseudo-noise (hereinafter referred to as the maximum pseudo-noise width). In the performance evaluation at one place, both P_ResStep and S / N are fixed, and performance evaluation for a predetermined time is performed. The error rate was calculated. The maximum pseudo noise width is calculated by the following equation (5). In the following formula (5), NWmax represents the maximum pseudo noise width.
NWmax = P_ResStep × (2 ⁷ −1) (5)

  The evaluation results obtained by the performance test described above are shown in the graphs of FIGS. FIG. 24 shows the relationship between the S / N and the error rate in the first configuration example of the noise reduction circuit of this embodiment and its comparative example, and FIG. 25 shows the second and second examples of the noise reduction circuit of this embodiment. 3 shows a relationship between the maximum pseudo noise width and the error rate in the configuration example 3 and the comparative example. In the performance test for obtaining the evaluation results shown in FIGS. 24 and 25, the evaluation environment is that the delay amount of the delay circuit DL1 is 1461 ps, the delay amount of the delay circuit DL3 is 5019 ps, and the performance of the noise reduction circuit is 1461 × 6 = The noise width was set to 8766 ps. Moreover, in FIG. 24, S / N was evaluated in four places of 4, 8, 16, 32. Furthermore, in FIG. 25, S / N is fixed to 16, P_ResStep is 60 locations from 5 ps to 300 ps in 5 ps increments, that is, NWmax of the maximum pseudo noise width is 60 locations from 635 ps to 38100 ps in 635 ps increments. It is the evaluated graph.

  First, the relationship between the S / N and the error rate in the first configuration example of the noise reduction circuit of the present embodiment shown in FIG. 24 and the comparative example will be described. Note that the logic unit for which performance evaluation was performed in the performance test for obtaining the evaluation results shown in FIG. 24 is the logic unit in which NR1 is a logic unit in which the delay circuit DL10 of Comparative Example 1 shown in FIG. Correspond. NR2 corresponds to the logical unit in which the delay circuits included in the delay unit of the first configuration example shown in FIG. 26B are set in the six delay circuits DL1, and NR3 is the logical product shown in FIG. Each of the logical sum units corresponds to a logical unit in which six logical units of comparative example 2 and comparative example 3 are cascade-connected. NR4 corresponds to the logical unit obtained by replacing the delay circuit DL10 of the first comparative example shown in FIG. 26A with two delay circuits DL3, and NR5 is the delay unit of the first configuration example shown in FIG. Corresponds to the logic unit in which the delay circuits included in the two delay circuits DL3 are set.

  As shown in FIG. 24, the logic unit NR2 that is the configuration of the noise reduction circuit of the first configuration example has a lower error rate than the logic unit NR5 that is also the configuration of the noise reduction circuit of the first configuration example, and is logically It can be seen that the unit NR5 tends to have a lower error rate than the logical units NR1 and NR4 which are comparative examples. From this, it can be seen that if the delay amount by the delay unit is substantially the same, the error rate decreases as the number of division of the delay unit increases, that is, as the number of taps between delay circuits constituting the delay unit increases. In other words, it can be seen that as the number of taps between the delay circuits constituting the delay unit increases, the noise superimposed on the signal decreases. Further, as shown in FIG. 24, the error rates of the logical units NR2 and NR3 are almost the same. However, since the number of delay circuits DL1 of NR2 is doubled in NR3, the circuit scale becomes large. From this, it can be seen that NR2, which is the first configuration example of the present embodiment, can further reduce the noise superimposed on the signal while suppressing the expansion of the circuit scale to the necessary minimum.

  Next, the relationship between the maximum pseudo noise width and the error rate in the second and third configuration examples of the noise reduction circuit of this embodiment shown in FIG. 25 and the comparative example will be described. Note that logical units that have been subjected to performance evaluation in the performance test for obtaining the evaluation results shown in FIG. 25 correspond to NR6 to NR9 described below. That is, as shown in FIG. 27, NR6 is a logical unit configured by cascading one logical unit 40 of Comparative Example 9 on the front side and two logical units 42 and 44 of Comparative Example 10 on the rear side. Correspondingly, NR7 corresponds to a logical unit obtained by replacing the delay circuit DL10 of Comparative Example 3 shown in FIG. 7 with a delay unit in which six DL1s are cascade-connected. NR8 corresponds to a logical unit in which each logic circuit is six in the second configuration example of the NR circuit of the present embodiment, and NR9 corresponds to each of the third configuration example of the NR circuit of the present embodiment. Corresponds to a logic unit having six logic circuits.

  As shown in FIG. 25, the noise reduction circuits NR8 and NR9 of the second and third configuration examples of the present embodiment tend to reduce the error rate at any maximum pseudo noise width than the logical unit NR6 shown in FIG. I understand that there is. That is, rather than a configuration in which two logical units having opposite noise reduction characteristics according to the voltage level are cascade-connected, these two logical units are arranged in parallel, and the output signals from these logical units are output from the selected unit. It can be seen that the error rate is reduced by selecting and outputting according to the voltage level of the signal.

  Further, the noise reduction circuits NR8 and NR9 of the second and third configuration examples tend to reduce the error rate as compared with the logical unit NR7 of the comparative example 1, and in particular, in the range where the maximum pseudo noise width is 30 ns or less. It can be seen that this tendency appears remarkably. From this, it can be seen that if the delay amount by the delay unit is almost the same, the error rate decreases as the number of division of the delay unit increases, that is, as the number of taps between delay circuits constituting the delay unit increases. In particular, this action / effect appears remarkably when the maximum pseudo noise width is in a range of 30 ns or less. From this, it can be seen that the noise reduction circuits NR8 and NR9 of the second and third configuration examples are appropriate for noise reduction up to a maximum pseudo noise width of about 30 ns. Note that, as indicated by P25 in FIG. 25, the noise reduction circuit NR9 of the third configuration example can reduce noise with a larger maximum pseudo noise width than NR8 of the second configuration example. Specifically, noise having a maximum pseudo noise width of about 31 ns can be reduced. This is because the NR8 of the third configuration example is provided with the inverters INV30_1 to INV30_ (2M-1) between the delay circuits as shown in FIG. 14, so that these inverters INV30_1 to INV30_ (2M-1) are provided. It can be seen that the amount of delay due to) is added to reduce noise with a larger maximum pseudo-noise width.

6). Electronic Device FIG. 28 shows an example of an electronic device including the noise reduction circuit described in the above embodiment. FIG. 28 is a block diagram illustrating an outline of an electrical configuration of an electronic apparatus including an image processing unit and a display unit as a device that operates based on a signal in which noise is reduced by a noise reduction circuit.

  In the electronic device 100, a ROM (Read Only Memory) (not shown) that stores a control program for controlling each device and component in the apparatus, and various data are temporarily written when the control operation is performed. A CPU (Central Processing Unit) 102 including a RAM (Random Access Memory) is provided. A memory 104, an image processing unit 106, an operation unit 108, a display unit 110, and an interface unit 112 are connected to the CPU 102, and the CPU 102 controls operations of these devices and components. Note that the electronic apparatus may include devices and components (for example, a power source) other than those shown in FIG.

  When power is supplied from a power supply (not shown), the CPU 102 controls each device in the electronic device 100 connected to the CPU 102 according to a program written in advance in the ROM. Then, by the control, the processing operation of each device is executed, and various data such as image data input / output during this time is temporarily stored in a predetermined memory area of a RAM (not shown), and the program read from the ROM Execute.

  The memory 104 has a function of storing various data such as image processed image data output from the image processing unit 106. The image processing unit 106 performs various image processing such as image data transmitted from an external device 116 such as a PC connected via a communication cable (transmission path) L10 such as a LAN so that the image data can be expanded. It has a function to apply. The operation unit 108 includes an input key (not shown) and the like, and has a function of executing a user operation using the input key. The display unit 110 has a function of displaying image processed image data and the like output from the image processing unit 106.

  The interface (I / F) unit 112 serves as a connector for receiving various data such as image data transmitted from an external device 116 such as a PC connected via a communication cable (transmission path) L10 such as a LAN. It has a function. The I / F unit 112 is provided with a noise reduction (NR) circuit 114 according to the present embodiment. Therefore, noise on both voltage levels included in various signals such as image data transmitted from the external device 116 is reduced by the noise reduction circuit. Accordingly, it is possible to suppress the malfunction of the device due to the noise superimposed on the signal transmitted to each device included in the electronic apparatus.

  Note that the noise reduction circuit according to the present embodiment includes the image processing unit 106 and the display unit 110 inside the electronic device 100, in addition to the interface unit 112 used in data transmission between the electronic device 100 and the external device 116. It is also possible to apply to the interface part of each device. By applying the noise reduction circuit of the present embodiment to such a device, noise included in various signals such as a control signal such as a reset signal and a clock signal transmitted and received between devices inside the electronic apparatus 100 is reduced. Thus, malfunction of each device can be suppressed.

  Also, the electronic device to which the noise reduction circuit of this embodiment is applied is not limited to the configuration of FIG. That is, a device that operates based on various signals such as a control signal such as a reset signal, a clock signal, or a data signal received from the interface unit via the noise reduction circuit by including a noise reduction circuit at least in the interface unit or the like. (For example, an image processing unit, a display unit, a memory, etc.) may be included. Specifically, as electronic devices to which the present embodiment can be applied, various types of image processing devices such as multifunction peripherals, information processing devices, portable information terminals, AV devices, portable AV devices, game devices, and portable game devices can be used. Can be considered.

  Although the present embodiment has been described in detail as described above, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. Let's go. Therefore, all such modifications are included in the scope of the present invention.

  For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the noise reduction circuit and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1 is a first configuration example of a noise reduction circuit according to the present embodiment. Configuration example of a delay unit. 2 shows a second configuration example of a noise reduction circuit according to the present embodiment. An example of the 2nd structural example of the noise reduction circuit of this embodiment. The comparative example 1 of the 1st structural example of the noise reduction circuit of this embodiment. The comparative example 2 of the 1st structural example of the noise reduction circuit of this embodiment. Comparative example 3 of the 1st structural example of the noise reduction circuit of this embodiment. 10 is a signal waveform example for explaining the operation of the noise reduction circuit of Comparative Example 3; 10 is a signal waveform example for explaining the operation of the noise reduction circuit of Comparative Example 3; Comparative example 4 of the 1st structural example of the noise reduction circuit of this embodiment. Comparative example 5 of the 1st structural example of the noise reduction circuit of this embodiment. Comparative Example 6 of the first configuration example of the noise reduction circuit of this embodiment. 10 is a signal waveform example for explaining the operation of the noise reduction circuit of Comparative Example 6; The 3rd structural example of the noise reduction circuit of this embodiment. Comparative example 7 of the 3rd structural example of the noise reduction circuit of this embodiment. Comparative example 8 of the 3rd structural example of the noise reduction circuit of this embodiment. Comparative example 9 of the 3rd structural example of the noise reduction circuit of this embodiment. The comparative example 10 of the 3rd structural example of the noise reduction circuit of this embodiment. FIG. 19A is a first configuration example of the selection unit of the noise reduction circuit of this embodiment, and FIG. 19B is a truth table of each signal output by the selection unit of this configuration example. 20A is a second configuration example of the selection unit of the noise reduction circuit of the present embodiment, and FIG. 20B is a truth table of each signal output by the selection unit of the configuration example. FIG. 21A is a third configuration example of the selection unit of the noise reduction circuit of this embodiment, and FIG. 21B is a truth table of each signal output by the selection unit of this configuration example. FIG. 22A is a fourth configuration example of the selection unit of the noise reduction circuit of this embodiment, and FIG. 22B is a truth table of each signal output by the selection unit of this configuration example. An example of the performance evaluation apparatus which performed the performance evaluation of each structural example of the noise reduction circuit of this embodiment. The graph which shows the relationship between S / N and an error rate in the 1st structural example of the noise reduction circuit of this embodiment, and its comparative example. The graph which shows the relationship between the maximum pseudo noise width and error rate in the 2nd and 3rd structural example of the noise reduction circuit of this embodiment, and its comparative example. 26A shows a configuration example of the logical unit NR1, FIG. 26B shows a configuration example of the logical unit NR2, FIG. 26C shows a configuration example of the logical unit NR3, and FIG. 26D shows NR5. Configuration example. The structural example of logical unit NR6 used as a comparative example. Configuration example of an electronic device.

Explanation of symbols

AND10, AND10_1 to AND10_N AND circuit,
OR10, OR10_1 to OR10_N OR circuit,
NAND30_1 to NAND30_M NAND circuit,
NOR30_1 to NOR30_M NOR circuit,
DL10_1 to DL10_N delay circuit,
Tp1 to Tp (N-1) taps 10, 20, 30 logical product units, 12, 22, 32 logical sum units,
14, 24, 34 Delay unit, 100 Electronic equipment

Claims (10)

A noise reduction circuit that reduces noise contained in an input signal,
A delay unit for delaying the input signal;
A logical product unit that takes a logical product of the input signal and the output signal of the delay unit;
A logical sum unit that takes a logical sum of the input signal and the output signal of the delay unit;
A selection unit that selects and outputs either the first output signal output from the logical product unit or the second output signal output from the logical sum unit;
The selection unit is
Outputting the first output signal when the output signal of the selection unit is at a first voltage level;
Outputting the second output signal when the output signal of the selection unit is at a second voltage level;
The delay unit is configured by cascading a plurality of delay circuits, and taps between the delay circuits are respectively connected to input terminals of the logical product unit and the logical sum unit. circuit. In claim 1,
The logical product unit includes AND circuits to which the input signal and output signals of the plurality of delay circuits provided in the delay unit are respectively input.
The logical OR unit includes an OR circuit to which the input signal and output signals of the plurality of delay circuits provided in the delay unit are input, respectively. In claim 1,
The delay unit is configured by cascading N delay circuits (N is an integer),
The logical product unit is configured by cascading N AND circuits,
The OR unit is configured by cascading N OR circuits,
The first AND circuit from the input stage takes the logical product of the input signal and the output signal from the first delay circuit from the input stage,
The i-th (2 ≦ i ≦ N) AND circuit from the input stage takes the logical product of the output signal of the (i−1) -th AND circuit from the input stage and the output signal of the i-th delay circuit from the input stage,
The first OR circuit from the input stage takes the logical sum of the input signal and the output signal from the first delay circuit from the input stage,
The i th OR circuit from the input stage takes a logical sum of the output signal of the (i−1) th OR circuit from the input stage and the output signal of the i th delay circuit from the input stage. In claim 1,
The delay circuit is configured by cascading 2M delay units (M is an integer) via inverter circuits,
The logical product unit is configured such that M logical AND circuits and M logical NOR circuits are alternately cascade-connected so that the logical product NAND circuits are arranged first from the input stage.
The logical sum unit is configured by alternately cascading M logical OR circuits and M logical NAND circuits so that the logical OR NOR circuits are arranged first from the input stage.
The NAND circuit for the first logical product from the input stage takes a negative logical product of the input signal and the output signal from the first delay circuit from the input stage,
The j-th (2 ≦ j ≦ M) logical product NAND circuit from the input stage outputs the output signal of the j−1th logical NOR circuit from the input stage and the output from the 2j−1th delay circuit from the input stage. Take the NAND of the signal and
The k-th (1 ≦ k ≦ M) AND circuit from the input stage negates the output signal from the k-th NAND circuit from the input stage and the output signal from the 2k-th delay circuit from the input stage. Logical OR
The first OR circuit from the input stage takes a negative OR of the input signal and the output signal from the first delay circuit from the input stage,
The j-th (2 ≦ j ≦ M) logical sum NOR circuit from the input stage outputs the output signal of the (j−1) th logical sum NAND circuit from the input stage and the output from the 2j−1th delay circuit from the input stage. Take the negative OR with the signal,
The k-th (1 ≦ k ≦ M) logical sum NAND circuit from the input stage negates the output signal from the k-th NOR circuit from the input stage and the output signal from the 2k-th delay circuit from the input stage. A noise reduction circuit characterized by taking a logical product. In any one of Claims 1 thru | or 4,
The selection unit is
Including first and second AND circuits serving as input stages, and a selection OR circuit serving as an output stage,
In the first AND circuit, the first output signal is input to one input terminal, the inverted signal of the output signal of the selection OR circuit is input to the other input terminal, and the first output signal Take the logical product of the inverted signal of the output signal of the selection OR circuit and output to the one input terminal of the selection OR circuit,
In the second AND circuit, the second output signal is input to one input terminal, the output signal of the selection OR circuit is input to the other input terminal, and the second output signal and the selection signal are input. Take the logical product with the output signal of the OR circuit and output to the other input terminal of the selection OR circuit,
The selection OR circuit outputs a signal by taking a logical sum of an output signal of the first AND circuit and an output signal of the second AND circuit. In any one of Claims 1 thru | or 4,
The selection unit is
Including first and second AND circuits serving as input stages, and a selection NOR circuit serving as an output stage,
In the first AND circuit, the first output signal is input to one input terminal, the output signal of the selection NOR circuit is input to the other input terminal, and the first output signal and the selection signal are input. Take the logical product with the output signal of the NOR circuit and output to the one input terminal of the selection NOR circuit,
In the second AND circuit, the second output signal is input to one input terminal, an inverted signal of the output signal of the selection NOR circuit is input to the other input terminal, and the second output signal Take the logical product of the inverted signal of the output signal of the selection NOR circuit and output to the other input terminal of the selection NOR circuit,
The noise reduction circuit according to claim 1, wherein the selection NOR circuit outputs a signal by taking a negative OR of the output signal of the first AND circuit and the output signal of the second AND circuit. In any one of Claims 1 thru | or 4,
The selection unit is
Including first and second OR circuits serving as input stages, and an AND circuit for selection serving as an output stage,
In the first OR circuit, an inverted signal of the first output signal is input to one input terminal, and an inverted signal of the output signal of the selection AND circuit is input to the other input terminal. Take the logical sum of the inverted signal of the output signal and the inverted signal of the output signal of the selection AND circuit, and output to the one input terminal of the selection AND circuit,
In the second OR circuit, an inverted signal of the second output signal is input to one input terminal, an output signal of the AND circuit for selection is input to the other input terminal, and the second output signal Take the logical sum of the inverted signal and the output signal of the selection AND circuit to output to the other input terminal of the selection AND circuit,
The noise reduction circuit according to claim 1, wherein the AND circuit for selection outputs a signal by taking a logical product of an output signal of the first OR circuit and an output signal of the second OR circuit. In any one of Claims 1 thru | or 4,
The selection unit is
Including first and second OR circuits serving as input stages, and a selection NAND circuit serving as an output stage,
In the first OR circuit, an inverted signal of the first output signal is input to one input terminal, an output signal of the selection NAND circuit is input to the other input terminal, and the first output signal Take the logical sum of the inverted signal and the output signal of the selection NAND circuit, and output to the one input terminal of the selection NAND circuit,
In the second OR circuit, an inverted signal of the second output signal is input to one input terminal, and an inverted signal of the output signal of the selection NAND circuit is input to the other input terminal. Take the logical sum of the inverted signal of the output signal and the inverted signal of the output signal of the selection NAND circuit, and output to the other input terminal of the selection NAND circuit,
The selection NAND circuit outputs a signal by taking a NAND of an output signal of the first OR circuit and an output signal of the second OR circuit, and outputs a signal. In any one of Claims 1 thru | or 8.
The delay circuit is configured by connecting a plurality of delay elements in series. A noise reduction circuit according to any one of claims 1 to 9,
A device that operates based on a signal whose noise is reduced by the noise reduction circuit;
An electronic device comprising:

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