JPH0553703A - Chattering eliminating circuit - Google Patents

Abstract

PURPOSE:To easily set a proper time constant in response to the change of the chattering time and also to improve the program developing efficiency by setting optionally the delay time of a shift register. CONSTITUTION:The external signal of the key input, etc., inputted from an input terminal is inputted to an input buffer 2, and a passed input signal (a) includes the noises like the chattering, etc., before end after an ON signal. The signal (a) including the chattering is reed at the rise of a clock CK received from a clock generating circuit a and then delayed by a shift register 3 by an extent equal to the relevant number of stages. The delayed signal serves as the output (b) of each stage end inputted to a NAND circuit 4 and a NOR circuit 5. The circuit 4 can el-iminate the chattering produced at the beginning of the ON signal of the input and the circuit 5 can eliminate the chattering produced at the end of the ON signal with proper selection of the frequency of the clock CK and the number of stages of the register 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chattering elimination circuit, and more particularly to a chattering elimination circuit in an input circuit of a microprocessor which handles key input data.

[0002]

2. Description of the Related Art In a microprocessor application example, the state of a key to be manually pressed is often input and determined by a program. Since this type of key is manually pressed by a human, chattering, which is an electrical noise, often occurs when the state changes from off to on or from on to off. If this chattering is read as it is in the program, it is determined that the key has been turned on / off the number of times of chattering, which causes a malfunction. Therefore, there is a need for a method of removing this chattering and determining the original key state.

As shown in FIG. 3, the conventional chattering elimination circuit uses CR integration consisting of a capacitor C connected to the key 11, a resistor R, and a waveform shaping circuit 10 as the simplest chattering elimination method. This circuit was connected to the key input terminal TI of the microprocessor 1. The combination of the capacitor C and the resistor R forms a filter with an appropriate time constant to eliminate chattering. Since the integrated signal changes slowly, it is usually necessary to additionally use the waveform shaping circuit 10 having a hysteresis characteristic. This circuit is not a reliable method because the pulse width of the chattering signal that can be removed also changes when the impedance of the signal source, that is, the key side, changes.

A second example of a conventional chattering removing circuit which is an improvement on this is disclosed in Japanese Patent Publication No. 59-2206. As shown in FIG. A CR integrator circuit including an input circuit 12 connected to 11 and including a vertically stacked four-stage FET, a capacitor C connected to the output side thereof, and a resistor R;
There is a circuit provided with three stages of inverter circuits 13. This circuit controls chattering by controlling the charging / discharging direction of the capacitor C with a combination of FETs.

Next, the operation of the conventional chattering elimination circuit will be described.

FIG. 5 is a time chart showing an example of the operation of the circuit shown in FIG.

The maximum pulse width of chattering that can be removed is the time t determined by CR. Further, according to this method, the capacitor C and the input signal I are separated by the input circuit 12 in which the FETs are vertically stacked, so that it is possible to realize a chattering elimination circuit which is not affected by the change in impedance on the key side.

For chattering removal, usually, in addition to the connection of the integration circuit described above, chattering removal by programming is often used together. For example, there is a method in which the state of the key is read again after a fixed time after the first change in the state of the key is detected, and if the state continues to be the same, it is determined that the state of the key has changed for the first time. At this time, if the state of the key is different from the time when the change is detected, it is removed as chattering. According to this formula, the chattering removal time can be changed by a program. According to the program, the chattering removal performance is determined by the timing of detecting the first key state change.

The chattering time of the key varies greatly depending on the type of material, the mechanism, and the pressing method. It is good if the characteristics of the key to be used in advance are clear and the chattering time can be accurately predicted, but in many cases it cannot be judged unless the system is actually operated.

When only the above-mentioned integrating circuit is used, it is very difficult to set the time constant. If the time constant is made too large to surely eliminate chattering, keystrokes with a short width will be missed. On the contrary, if the time constant is made small, chattering cannot be removed, resulting in malfunction. Also,
Regarding the accuracy of the time constant, there are many problems in terms of manufacturing variations and temperature changes when integrated.

When the chattering is removed by the program, it is performed while executing other processing, so that the program considering the chattering removal becomes more complicated. Since the chattering time differs depending on the key characteristics, it is necessary to determine in advance what kind of key to use at the time of designing the program and incorporate the predicted time into the flow of the program. In addition, when changing the key to be used, it may be necessary to modify the entire program. Further, when the priority of other processing is high, the chattering processing time varies, and reliable key input may not be possible. Also, if the program for removing chattering affects the entire program,
It was necessary to verify it when debugging.

[0012]

The conventional chattering elimination circuit described above has a drawback in that it is difficult to set an appropriate time constant in response to a change in chattering time depending on the material and mechanism of the key and the pressing method. there were. Further, the program method has a drawback that the chattering is removed while executing other processing, so that the program becomes complicated and debugging is troublesome.

[0013]

A chattering elimination circuit of the present invention delays an input signal by a preset delay time and has a plurality of stages of shift registers each having an output terminal,
A first logic circuit that performs a first logical operation that is a logical product or a negative logical product of the input signal and the output from the output terminal of each stage of the shift register, and each of the input signal and the shift register. A second logical circuit that performs a second logical operation that is a logical sum or a negative logical sum with the output from the output terminal of the stage, and a set by the output of the first logical circuit and the second logical circuit. A flip-flop circuit that is reset, a determination circuit that determines the output state of the flip-flop circuit, and a clock supply circuit that supplies a variable frequency clock that arbitrarily sets the delay time of the shift register are configured. ing.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the chattering elimination circuit of the present invention.

The chattering elimination circuit of this embodiment is shown in FIG.
As shown in FIG. 3, an input buffer 2 is input to the input side of the microprocessor 1 and a shift register 3 of four stages in this example, which has an input signal a via the input buffer 2 and has an output terminal in each stage. , Input signal a and shift register 3
Of the NAND circuit 4 which receives the outputs b to e of each stage and performs a logical product operation thereof, and the input of the input signal a and the outputs b to e of each stage of the shift register 3 from which a logical sum operation is performed.
The outputs of the R circuit 5 and the NAND circuit 4 are input to the set terminal, and the output of the NOR circuit 5 is input to the reset terminal.
An S flip-flop 6, an output circuit of the RS flip-flop 6, a determination circuit 7 that outputs the state to the data bus 9 in synchronization with the control signal C, and a clock generation circuit 8 that supplies an operation clock of the shift register 3. , And a data bus 9.

The frequency of the clock generation circuit 8 is set by the frequency setting data output to the data bus 9 in synchronization with the control signal D.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart of the circuit of this embodiment shown in FIG.

An external input signal such as a key input input from the input terminal TI is input to the input buffer 2. The input signal a that has passed through the input buffer 2 includes noise such as chattering before and after the ON signal that is the original input signal. The signal a including this chattering is read at the rising edge of the clock CK from the clock generation circuit 8, and the shift register 3 delays the number of stages, that is, four stages in this example. The delayed signals become the outputs b to e of each stage of the shift register 3 and are input to the NAND circuit 4 and the NOR circuit 5.

The output f of the NAND circuit 4 becomes low level only when the outputs b to e of each stage of the shift register 3 and the signal a all become high level. As a result, the set input of the RS flip-flop 6 is triggered and the output signal h is brought to a high level state. That is, in order to bring the signal h into the high level state, it is necessary to hold the signal a at the high level for at least the number of clocks obtained by adding 1 to the number of stages of the shift register 3, in the present embodiment, 5 clocks. .. Accordingly, by appropriately selecting the frequency of the clock CK and the number of stages of the shift register 3, it is possible to eliminate chattering that occurs at the beginning of the input ON signal.
The microprocessor 1 reads the state of the chattering-free signal h through the determination circuit 7 and determines that the input signal is on.

Similarly, the output g of the NOR circuit 5 becomes high level only when the outputs b to e of each stage of the shift register 3 and the signal a all become low level. As a result, the reset input of the RS flip-flop 6 is triggered and the output signal h is set to the low level state. That is, in order to bring the signal h into the low level state, at least the number of clocks obtained by adding 1 to the number of stages of the shift register 3, that is, 5 in the present embodiment.
It is necessary to keep the signal a low level for the number of clocks. Thus, by appropriately selecting the frequency of the clock CK and the number of stages of the shift register 3, it is possible to eliminate chattering that occurs at the end of the input ON signal. The microprocessor 1 reads the state of the chattering-free signal h through the determination circuit 7 and determines that the input signal is off.

As mentioned above, the frequency of the clock CK is
It is arbitrarily set by the frequency setting data output to the data bus 9 in synchronization with the control signal D from the microprocessor 1 for the clock generation circuit 8.

The output f of the NAND circuit 4 changes to a high level even if noise as shown in FIG. 2 is superimposed on the input ON signal.
Output g does not change while holding high level,
The output signal h of the RS flip-flop 6 does not change, and no malfunction occurs.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made.

For example, it is also out of the scope of the present invention to provide an external clock terminal for inputting a clock from the outside and a clock switching circuit for switching the external and internal clocks so that they can be selected, in addition to the clock generation circuit. Of course, it can be applied unless it is done.

Further, instead of the NAND circuit and the NOR circuit, the AND circuit and the OR circuit may be used by reversing the logical values of the set and reset of the RS flip-flop.
Needless to say, the present invention can be applied without departing from the spirit of the present invention.

[0028]

As described above, the chattering elimination circuit of the present invention is provided with the shift register of a plurality of stages and the clock supply circuit of the variable frequency for arbitrarily setting the delay time of the shift register. There is an effect that it is possible to easily set an appropriate time constant in response to a change in chattering time due to a material or mechanism and a pressing method thereof. Further, in the program, since only the part that determines the frequency setting value needs to be modified, there is no effect on other processing, and there is an effect that the efficiency of program development can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a chattering removal circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the chattering removal circuit of the present embodiment.

FIG. 3 is a block diagram showing a first example of a conventional chattering removal circuit.

FIG. 4 is a block diagram showing a second example of a conventional chattering removal circuit.

FIG. 5 is a time chart showing an example of the operation of the chattering removal circuit of FIG.

[Explanation of symbols]

 1 Microprocessor 2 Input Buffer 3 Shift Register 4 NAND Circuit 5 NOR Circuit 6 RS Flip-Flop 7 Judgment Circuit 8 Clock Generation Circuit 9 Data Bus 10 Waveform Shaping Circuit 11 Key 12 Input Circuit 13 Inverter Circuit C Capacitor R Resistance

Claims (1)

[Claims] 1. A shift register having a plurality of stages each having an output terminal after delaying an input signal by a preset delay time, and a logical product or negation of the input signal and an output from the output terminal of each stage of the shift register. A first logic circuit that performs a first logical operation that is a logical product, and a second logical operation that is a logical sum or a negative logical sum of the input signal and the output from the output terminal of each stage of the shift register A second logic circuit for performing the above, a flip-flop circuit set and reset by the outputs of the first logic circuit and the second logic circuit, a determination circuit for determining the output state of the flip-flop circuit, And a clock supply circuit that supplies a variable frequency clock for arbitrarily setting the delay time of the shift register. Grayed removal circuit.