JPH0834417B2 - Input control circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an input control circuit that removes and outputs an external input signal including chattering and noise, for example, in a microcomputer. I / O
Used for port.

(B) Prior Art Generally, in various devices using a microcomputer, for example, in an electrophotographic copying machine, signals from peripheral circuits using switches, relays, etc. are input to the microcomputer. Since the input signal contains chattering and noise, it is necessary to process the input signal so that the microcomputer does not malfunction. Therefore, conventionally, a method of delaying an input signal by an integrating circuit composed of a capacitor and a resistor and a method of processing it by software in a microcomputer have been proposed.

(C) Problems to be solved by the invention By the way, since the frequency and duration of chattering and noise of the signal input from the peripheral circuit differ depending on the type of the signal, the signal can be promptly output without malfunction or false detection. In order to process, processing according to the type of each input signal is required. However, it is not easy to individually change or adjust the time constant of the integration circuit using capacitors and resistors according to the type of input signal, and in the processing by software, the processing corresponding to the type of input signal is not possible. There was a problem that it became frequent and the burden on the CPU increased.

The present invention has been made in consideration of such circumstances, and provides an input control circuit capable of easily and appropriately performing signal processing in accordance with the type of input signal.

(D) Means for Solving the Problems The present invention is directed to a plurality of serial registers that sequentially shift an external input signal from the first stage to the last stage in synchronization with a shift pulse, and an arbitrary serial register from the first stage of the registers. A designated circuit that designates the number of stages, a comparison circuit that compares the logical values of the designated stages and outputs when the logical values match, and a logical value of the first stage of the register is received in response to the output of the comparison circuit. An input control circuit comprising a latch circuit, delaying an external input signal, removing an unnecessary signal, and outputting as a true external input signal value.

(E) Operation When an external input signal is input to the register, it is sequentially shifted in synchronization with the shift pulse. The comparison circuit compares the logical values of the number of stages designated by the designating circuit, and when they match, the logical value of the external input signal is taken into the latch circuit and output. That is, the external input signal is output after it is confirmed that the same logical value is maintained for the shift period of the register having the number of stages designated by the designation circuit. Therefore, if the number of stages of the register is designated in accordance with the chattering or noise period included in the input signal, the chattering or noise is appropriately removed and the external input signal is output.

(F) Embodiment Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. This does not limit the present invention.

FIG. 1 is an electric circuit diagram showing an embodiment in which the present invention is applied to an input processing of a CPU. 1 is a buffer for receiving an input signal, 2 is an input from the buffer 1 sequentially shifted by a clock pulse CLOCK. A shift register that outputs each shift signal B0 to B4, 3a to 3d are signals B0 and B1, respectively.
Exclusively OR circuit that inputs B1 and B2, B2 and B3, B3 and B4 and outputs signals D1 to D4 (hereinafter referred to as EX / OR circuit), 4 is C
Signal when the designated signal input by the data signal DATA from the PU is latched and the write designated output ▲ ▼ is received.
Registers output as C1 to C4, 5a to 5d are signals
AND circuit to which each pair of C1 to C4 and signals D1 to D4 is input, 6 is A
OR circuit to which outputs E _{1 to} E ₄ of ND circuits 5a to 5d are input, 7 is an OR circuit
An AND circuit to which the output F of the circuit 6 and the clock signal CLOCK are input, 8 is a flip-flop circuit that outputs and holds the signal B0 when the output G of the AND circuit 7 is received, and 9 is an output Y of the flip-flop circuit 8. It is a three-state buffer that outputs as signal Y ₁ when it receives the read designation output ▲ ▼ from the CPU.

FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1. When the input signal X changes from "1" to "0" with a chattering waveform, the chattering waveform is removed and the signal Y is removed. Indicates the situation that is output as. That is,
When the input signal X is read into the shift register 2 and sequentially shifted, the output signals B0 to B4 are as shown in FIG.
Then, these signals B0 to B4 are input in pairs
The outputs D1 to D4 of the OR circuits 3a to 3d are "1" when the inputs do not match and "0" when the inputs match, as shown in FIG. By the way, now, register 4 is a CPU so that outputs C1 and C2 of register 4 are "1" and C3 and C4 are "0".
When set by the data signal DATA from
The outputs E3, E4 of the D circuits 5c, 5d are always "0" regardless of the inputs D3, D4. On the other hand, in the AND circuits 5a and 5b, the outputs E1 and E2 are "0" only when the inputs D1 and D2 are "0", respectively.
That is, when the logical values of the signals B0, B1 and B2 all match 0, the output F of the OR circuit 6 becomes "0", and the AND circuit 7 outputs "0" when both the signal F and the clock signal become "0". The signal G of "1" is output. Therefore, the flip-flop circuit 8 outputs the signal B0 as the read signal Y and holds the state when the signal G becomes "1". 3 states
The buffer 9 outputs the signal Y held in the flip-flop 8 when the designated output ▲ ▼ read from the CPU is output.
Is output as signal Y1.

In this way, the input signal X is detected after it has reached a sufficiently stable value, that is, after being delayed by the time Td (FIG. 2), so that chattering and noise occurring during the time Td are generated from the input signal X. Will be removed. The delay time Td can be arbitrarily controlled by setting the output of the register 4 by the data signal DATA from the CPU, as described above, and can be adjusted according to the chattering of the input signal X or the situation of noise. You can Also, time Td
By changing the period of the clock pulse,
Of course it is adjustable.

FIG. 3 shows another embodiment of the present invention and is an electric circuit diagram of a programmable I / O port capable of a plurality of inputs / outputs, which is constructed by using the input control circuit of FIG. 1 as a basic circuit. In the figure, PA _{0 to} PA _n are input / output terminals for external connection, PB _{0 to} PB ₇
Is a pin connected to the CPU data buses DB _{0 to} DB ₇ , K _{1 to} K ₇
Is an input processing circuit surrounded by a broken line K in FIG.
L ₁ ~L ₇ is input process signals from the terminal PA ₀ ~PA ₇ circuit K ₁ ~K ₇
A buffer (corresponding to the buffer 1 in FIG. 1), M _{1 to} M ₇ receives the outputs of the input processing circuits K _{1 to} K ₇ and outputs them to the data buses DB ₀ to DB ₇ (three state buffers). (Corresponding to the buffer 9 in FIG. 1), F _{1 to} F ₇ are data buses DB
Flip-flop circuit for holding signals output from _{0 to} DB ₇ , J _{1 to} J ₇ are 3-state buffers that output the outputs of the flip-flop circuits F _{1 to} F ₇ to terminals PA ₀ to PA ₇ , and 11 is a CPU
Data bus DB ₀ controls the signal receiving and 3-state buffer J ₁ through J ₇ of to DB ₇ register sets the input and output terminals PA ₀ ~PA ₇ of 12 data buses DB ₀ to DB ₇ of the CPU A register (corresponding to the register 4 in FIG. 1) for setting the processing time of the input processing circuits K _{1 to} K ₇ in response to the signal No. 13 and a register 11 for receiving the address bus signals AB _{0 to} AB ₇ from the CPU. Decoders controlling 12 and 12, 14 is a write designation output from the CPU ▲ ▼
Is an AND circuit which receives the outputs of the decoder 13 and the decoder 13 and sets the flip-flops F _{1 to} F ₇ when they are both “1”.

With this configuration, the data buses DB _{0 to} D
The signal input from B ₇ is once held in the flip-flops F _{1 to} F ₇ , and output to the terminals PA ₀ to PA ₇ at the timing designated by the register 11. On the other hand, after the signal inputted from the terminal PA ₀ ~PA ₇ is processed through an input signal X as well as the input processing circuit K ₁ ~K ₇ shown in FIG. 1, the read designated output from the CPU ▲ ▼ of Chattering and noise will be output to the data buses DB _{0 to} DB ₇ at the timing. In this way, a programmable I / O port using the input control circuit shown in FIG. 1 is constructed. Further, since the programmable I / O ports shown in FIG. 3 are all composed of logic circuits, they can be easily made into an LSI.

(G) Effect of the Invention According to the present invention, the input control circuit that reliably removes chattering and noise included in the input signal is configured by hardware, and the CPU simply reads the processed signal when necessary. Well, little software processing of the signal is required. Further, the input processing time, that is, the chattering or noise removal time is arbitrarily set according to the type of the input signal. In addition, since it can be configured with logic, it can be easily integrated into an LSI.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is an electric circuit diagram showing another embodiment of the present invention. 1 ... buffer, 2 ... shift register, 3a-3d ... Ex
Exclusively OR circuit, 4 ... Register, 5a-5d ... AND circuit, 6 ... OR circuit, 7 ... AND circuit, 8 ... Flip-flop, 9 ... 3-state buffer.

Claims (1)

[Claims] 1. A serial register having a plurality of stages for sequentially shifting an external input signal from a first stage to a last stage in synchronization with a shift pulse, and a designation circuit for designating an arbitrary number of stages from the first stage of the register. Comparing the logic values of each stage and outputting when the logic values match, and a latch circuit that receives the output of the comparison circuit and captures the logic value of the first stage of the register, delays the external input signal An input control circuit characterized by removing unnecessary signals and outputting as a true external input signal value.