JPH05243923A - Noise elimination circuit - Google Patents

Abstract

PURPOSE:To obtain true logical output by eliminating a noise signal due to induction, etc., from the outside in the input processing of a digital signal. CONSTITUTION:The OR circuit output 6 and the AND circuit output 7 of signal input 1 and a delay circuit 2 to delay this signal by a definite period of time are taken, and by connecting each OR and AND output 6,7 to a flip-flop 8, a specified value is outputted. Through this configuration, the continuity of the same logical level is judged, and the intermittent noise signal is eliminated. Namely, the noise is eliminated by constituting this noise elimination circuit so that the input signal is acknowledged as the signal only when both the OR output 6 and the AND output 7 are of the same logical level and it does not respond to instantaneous change due to the noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit, and more particularly to a circuit for removing noise input from the outside by induction or the like.

[0002]

2. Description of the Related Art Conventionally, removal of noise from a digital signal input has been realized by an integrating circuit 12 including a resistor 10 and a capacitor 11 and a logic circuit 14 having a hysteresis function as shown in FIG.

The operation will be described with reference to FIG. (1) When noise is input in the state where the signal input 1 is at the logic level 1 (a), the signal is integrated by the integrator circuit 12 including the resistor 10 and the capacitor 11, and its output 13 is a logic having a hysteresis function. The circuit 14 determines the logic level (two-dot chain line of the waveform of the output of the integration circuit 13) and holds the logic level 1. (2) When the logic level of the signal input 1 changes from 1 to 0 (b), the signal integration output 13 of the integration circuit 12 is changed to the threshold level of the logic circuit 14 (2 of the waveform of the integration circuit output 13).
Judgment is made by the broken line), and the noise removal output 9 is set to logic level 0. (3) When noise is input while the signal input 1 is at the logic level 0 (c), the integration circuit 12 outputs the signal integration output 13
Then, the logic level is judged by the logic circuit 14 (one-dot chain line of the waveform of the output 13 of the integration circuit), and the logic level 0 is held.

[0004]

In this conventional structure, the integration circuit has a large integration time constant, which makes it difficult to form an integrated circuit and becomes a structure with individual parts, resulting in a large number of signal lines. The scale becomes large.

Further, when the logic circuit is constructed by an element having a relatively small input impedance such as TTL, the resistance value of the integrating circuit must be reduced, and as a result, the value of the capacitor is reduced. However, there is a drawback that the device becomes large and the device becomes large in size, and the device becomes large in size.

It is an object of the present invention to provide a noise elimination circuit that eliminates a noise signal due to induction or the like from the outside in the input processing of a digital signal to obtain a true logic output.

[0007]

In order to achieve the above-mentioned object, a noise elimination circuit according to the present invention comprises a delay circuit for delaying a signal input for a fixed time, and a logic for ORing the signal input and the delay circuit output. And a storage circuit that outputs a specific value from the output of the logical sum circuit and the output of the logical product circuit. is there.

The delay circuit is composed of a plurality of logical inversion or non-inversion elements, and the memory circuit is R
An S (set / reset) type flip-flop, which outputs a logic 0 when the output of the OR circuit is a logic 0 and outputs a logic 1 when the output of the AND circuit is a logic 1 It is composed.

[0009]

As shown in FIG. 1, a logical sum and a logical product of a signal input 1 and an output of a delay circuit 2 which delays the signal for a predetermined time are calculated, and respective logical sum and logical product outputs 6 and 7 are obtained. A specific value is output by connecting to a storage circuit composed of a flip-flop or the like.

With this configuration, continuity of the same logic level is determined, and intermittent noise signals are removed. That is, the logical sum output 6 and the logical product output 7 are recognized as signals only when both have the same logical level, and noise is removed by configuring so as not to react to an instantaneous change due to noise.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the noise elimination circuit according to the present embodiment comprises a delay circuit 2 for delaying a signal input 1 for a fixed time,
The logical sum circuit 4 that takes the logical sum of the output 3 of the delay circuit 2 and the signal input 1, the logical product circuit 5 that takes the logical product of the output 3 of the delay circuit 2 and the signal input 1, and the output of the logical sum circuit 4. 6 and a memory circuit for outputting a specific value from the output 7 of the AND circuit 5, and the continuity of the same logic level is judged by the delay circuit 2 to eliminate intermittent noise. Is.

The delay circuit 2 is composed of a plurality of logic inversion or non-inversion elements.

The memory circuit is composed of an RS (set / reset) type flip-flop 8. When the output 6 of the logical sum circuit 4 is a logical 0, a logical 0 is output, and the output 7 of the logical product circuit 5 is a logical 1. Is configured to output a logical one.

(1) When noise is input in the state where the signal input 1 is at the logic level 1 (state (A) in FIG. 2), the output 3 of the delay circuit 2 composed of a plurality of buffer elements is present. , A signal delayed by a fixed time longer than the noise input time is output. The logical sum output 6 of the delay output 3 and the signal input 1
Remains at logic level one. On the other hand, the logical product output 7 becomes the logical product output 7 affected by the noise signal and its delayed output. For these two signals, the memory circuit configured based on the flip-flop 8 composed of two NANDs outputs the same value (logical level 1) to the noise elimination output (memory circuit output) despite the signal change of the logical product output 7. ) Continue to output to 9.

(2) When the signal input 1 changes from the logic level 1 to 0 (state (A) of FIG. 2), the delay circuit output 3
Becomes a logical level 0, the logical sum output 6 becomes a logical level 0, and as a result, the memory logic is inverted in the memory circuit 8, and the noise elimination output (memory circuit output) 9 outputs a logical level 0.

(3) When noise is input while the signal input 1 is at the logic level 0 (state (c) of FIG. 2), the logical sum output 6 of the delay circuit output 3 and the signal input 1 is The logical sum output 6 is affected by the noise signal and its delayed output. However, the logical product output 7 remains at the logical level 0. With respect to the logical sum output 6 and the logical product output 7, the storage circuit 8 holds the storage logic, and the noise elimination output (storage circuit output) 9 continues to output the logic level 0.

As described above, this circuit can remove noise.

[0019]

As described above, according to the present invention, all the logic elements can be easily configured. Furthermore, since the circuit structure of claim 2 is simple, even if it is added as an input part of the integrated circuit in advance, it does not burden the scale and can be configured by PAL (programmable array logic). There is an effect that there is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of operation signals of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is an operation signal waveform diagram in the circuit example shown in FIG.

[Explanation of symbols]

 1 signal input 2 delay circuit 4 logical sum circuit 5 logical product circuit 8 flip-flop (memory circuit)

Claims (2)

[Claims] 1. A delay circuit for delaying a signal input for a fixed time, a logical sum circuit for taking a logical sum of a signal input and the output of the delay circuit, and a logical product circuit for taking a logical product of a signal input and the output of the delay circuit And a memory circuit that outputs a specific value from the output of the logical sum circuit and the output of the logical product circuit. 2. The delay circuit is composed of a plurality of logical inversion or non-inversion elements, the storage circuit is composed of an RS (set / reset) type flip-flop, and the output of the OR circuit is a logical 0. If the output of the AND circuit is a logic 1, then a logic 0 is output.
The noise elimination circuit according to claim 1, wherein the noise elimination circuit is configured to output